LPC3220/30/40/50 - Static6.arrow
LPC3220/30/40/5016/32-bit ARM microcontrollers; hardware floating-pointcoprocessor, USB On-The-Go, and EMC memory interfaceRev. 2.1 — 24 June 2014Product data sheet1. General descriptionThe LPC3220/30/40/50 embedded microcontrollers were designed for low power, highperformance applications. NXP achieved their performance goals using a 90 nanometerprocess to implement an ARM926EJ-S CPU core with a vector floating point co-processorand a large set of standard peripherals including USB On-The-Go. TheLPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU providesthe virtual memory capabilities needed to support the multi-programming demands ofmodern operating systems. The ARM926EJ-S also has a hardware based set of DSPinstruction extensions, which includes single cycle MAC operations, and hardware basednative Jazelle Java Byte-code execution. The NXP implementation has a 32 kBinstruction cache and a 32 kB data cache.For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advancedtechnology development to optimize intrinsic power and uses software controlledarchitectural enhancements to optimize application based power management.The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flashinterface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and anexternal bus interface that supports SDR and DDR SDRAM as well as static devices. Inaddition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single outputPWMs, a motor control PWM, six general purpose timers with capture inputs and compareoutputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC)with a touch screen sense option.For additional documentation, see Section 15 “References”.2. Features and benefits Downloaded from Arrow.com.ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.Vector Floating Point (VFP) coprocessor.32 kB instruction cache and 32 kB data cache.Up to 256 kB of Internal SRAM (IRAM).Selectable boot-up from various external devices: NAND flash, SPI memory, USB,UART, or static memory.
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollers Multi-layer AHB system that provides a separate bus for each AHB master, includingboth an instruction and data bus for the CPU, two data busses for the DMA controller,and another bus for the USB controller, one for the LCD, and a final one for theEthernet MAC. There are no arbitration delays in the system unless two mastersattempt to access the same slave at the same time. External memory controller for DDR and SDR SDRAM as well as for static devices. Two NAND flash controllers: One for single-level NAND flash devices and the other formulti-level NAND flash devices. Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting74 interrupt sources. Eight channel General Purpose DMA (GPDMA) controller on the AHB that can beused with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPIinterfaces, as well as memory-to-memory transfers. Serial interfaces: 10/100 Ethernet MAC with dedicated DMA Controller. USB interface supporting either device, host (OHCI compliant), or On-The-Go(OTG) with an integral DMA controller and dedicated PLL to generate the required48 MHz USB clock. Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. Oneof the standard UARTs supports IrDA. Three additional high-speed UARTs intended for on-board communications thatsupport baud rates up to 921 600 when using a 13 MHz main oscillator. Allhigh-speed UARTs provide 64 byte FIFOs. Two SPI controllers. Two SSP controllers. Two I2C-bus interfaces with standard open-drain pins. The I2C-bus interfacessupport single master, slave, and multi-master I2C-bus configurations. Two I2S-bus interfaces, each with separate input and output channels. Eachchannel can be operated independently on three pins, or both input and outputchannels can be used with only four pins and a shared clock. Additional peripherals: LCD controller supporting both STN and TFT panels, with dedicated DMAcontroller. Programmable display resolution up to 1024 768. Secure Digital (SD) memory card interface, which conforms to the SD MemoryCard Specification Version 1.01. General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24GP output pins, and 51 GP I/O pins. 10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing fromthree pins. Optionally, the ADC can operate as a touch screen controller. Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator.NXP implemented the RTC in an independent on-chip power domain so it canremain active while the rest of the chip is not powered. The RTC also includes a32-byte scratch pad memory. 32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timerincludes one external capture input pin and a capture connection to the RTC clock.Interrupts may be generated using three match registers.LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.2 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollers Six enhanced timer/counters which are architecturally identical except for theperipheral base address. Two capture inputs and two match outputs are pinned outto four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out allfour match outputs, timer 4 has one match output, and timer 5 has no inputs oroutputs. 32-bit millisecond timer driven from the RTC clock. This timer can generateinterrupts using two match registers. WatchDog timer clocked by the peripheral clock. Two single-output PWM blocks. Motor control PWM. Keyboard scanner function allows automatic scanning of an up to 8 8 key matrix. Up to 18 external interrupts.Standard ARM test/debug interface for compatibility with existing tools.Emulation Trace Buffer (ETB) with 2048 24 bit RAM allows trace via JTAG.Stop mode saves power while allowing many peripheral functions to restart CPUactivity.On-chip crystal oscillator.An on-chip PLL allows CPU operation up to the maximum CPU rate without therequirement for a high frequency crystal. Another PLL allows operation from the32 kHz RTC clock rather than the external crystal.Boundary scan for simplified board testing.User-accessible unique serial ID number for each chip.TFBGA296 package with a 15 mm 15 mm 0.7 mm body.3. Applications LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.ConsumerMedicalIndustrialNetwork controlAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.3 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollers4. Ordering informationTable 1.Ordering informationType VersionTFBGA296plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1LPC3230FET296/01[2]TFBGA296plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1LPC3240FET296/01[2]TFBGA296plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1LPC3250FET296/01[2]TFBGA296plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1[1]F 40 C to 85 C temperature range. Note that Revision “A” parts with and without the /01 suffix are identical. For example,LPC3220FET296 Revision “A” is identical to LPC3220FET296/01 Revision “A”.[2]Available starting with Revision “A”.4.1 Ordering optionsTable 2.Part optionsType numberSRAM (kB)10/100 EthernetLCDcontrollerTemperature range ( C)PackageLPC3220FET296/0112800 40 to 85TFBGA296LPC3230FET296/0125601 40 to 85TFBGA296LPC3240FET296/0125610 40 to 85TFBGA296LPC3250FET296/0125611 40 to 85TFBGA296LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.4 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollers5. Block diagramETBVFP9ETM 9D-CACHE32 kBARM9EJSI-CACHE32 kBD-SIDECONTROLLERMMUI-SIDECONTROLLERDATA0master layerslave erfaceethernetPHYinterface32-bit 0MACUSB ER60port 31port 42port 03AHB slaves5SLCNANDMLCNANDAHBAPB slavesTOAPBBRIDGESPI 2SRAM256 kBSDCARDROM16 kBSSP 2I2S 26DMAUSBSDRAMETBETHERNETLCDregister interfacesAHBAPB slavesTOAPBBRIDGEI2C 2732-bit AHB matrix Master/Slave connection supportedby the multilayer AHB matrixSTANDARDUART 4WATCHDOG TIMERSPWMTIMER 6 2AHBFAB CONTROL PWMRTCHS UART 397Fig 1.Block diagram of LPC3220/30/40/50LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.5 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollers6. Pinning information6.1 Pinningball A1index area21436587910 12 14 16 1811 13 15 17ABCDEFGHJKLMNPRTUV002aae398Transparent top viewFig 2.Table 3.PinPin configuration for SOT1048-1 (TFBGA296)Pin allocation table (TFBGA296)SymbolPinSymbolPinSymbolA3I2C2 SCLRow AA4I2S1TX CLK/MAT3[0]A5I2C1 SCLA6MS BS/MAT2[1]A7MS DIO1/MAT0[1]A8MS DIO0/MAT0[0]A9SPI2 DATIO/MOSI1/LCDVD[20][1]A10 SPI2 DATIN/MISO1/LCDVD[21][1]/GPI 27A11 GPIO 1A12 GPIO 0A13 GPO 21/U4 TX/LCDVD[3][1]A14 GPO 15/MCOA1/LCDFP[1]A15 GPO 7/LCDVD[2][1]B2GPO 20B3GPO 5A16 GPO 6/LCDVD[18][1]Row BB4I2S1TX WS/CAP3[0]B5P0[0]/I2S1RX CLKB6I2C1 SDAB7MS SCLK/MAT2[0]B8MS DIO2/MAT0[2]B9SPI1 DATIO/MOSI0/MCI2B10SPI2 CLK/SCK1/LCDVD[23][1]B11GPIO 4/SSEL1/LCDVD[22][1]B12 GPO 12/MCOA2/LCDLE[1]B13 GPO 13/MCOB1/LCDDCLK[1]B14 GPO 2/MAT1[0]/LCDVD[0][1]B16 GPI 8/KEY COL6/SPI2 BUSY/ENET RX DV[2]B17 n.c.B15 GPI 19/U4 RXRow CC1FLASH RDC2GPO 19C3GPO 0/TST CLK1C4USB ATX INTC5USB SE0 VM/U5 TXC6TST CLK2C7GPI 6/HSTIM CAP/ENET RXD2[2]C8MS DIO3/MAT0[3]C9SPI1 CLK/SCK0LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.6 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 3.PinPin allocation table (TFBGA296)SymbolPinSymbolPinSymbolC10 SPI1 DATIN/MISO0/GPI 25/MCI1C11 GPIO 3/KEY ROW7/ENET MDIO[2]C12 GPO 9/LCDVD[9][1]C13 GPO 8/LCDVD[8][1]C14 GPI 2/CAP2[0]/ENET RXD3[2]C15 GPI 1/SERVICEC16 GPI 0/I2S1RX SDAC17 KEY ROW4/ENET TXD0[2]C18 KEY ROW5/ENET TXD1[2]Row DD1FLASH RDYD2FLASH ALED3GPO 14D4GPO 1D5USB DAT VP/U5 RXD6USB OE TPD7 P0[1]/I2S1RX WSD10 GPO 16/MCOB0/LCDENAB[1]/LCDM[1]D8 GPO 4D11 GPO 18/MCOA0/LCDLP[1]D9 GPIO 2/KEY ROW6/ENET MDC[2]D12 GPO 3/LCDVD[1][1]D13 GPI 7/CAP4[0]/MCABORTD14 PWM OUT1/LCDVD[16][1]D15 PWM OUT2/INTSTAT/LCDVD[19][1]D16 KEY ROW3/ENET TX EN[2]D17 KEY COL2/ENET RX ER[2]D18 KEY COL3/ENET CRS[2]Row EE1FLASH IO[3]E2FLASH IO[7]E3FLASH CEE4I2C2 SDAE5USB I2C SCLE6USB I2C SDAE7I2S1TX SDA/MAT3[1]E8GPO 11E9GPIO 5/SSEL0/MCI0E10 GPO 22/U7 HRTS/LCDVD[14][1]E11GPO 10/MCOB2/LCDPWR[1]E12 GPI 9/KEY COL7/ENET COL[2]E13 GPI 4/SPI1 BUSYE14 KEY ROW1/ENET TXD2[2]E15 KEY ROW0/ENET TX ER[2]E16 KEY COL1/ENET RX CLK[2]/ENET REF CLK[2]E17 U7 RX/CAP0[0]/LCDVD[10][1]/GPI 23E18 U7 TX/MAT1[1]/LCDVD[11][1]Row FF1FLASH IO[2]F2FLASH WRF3FLASH CLEF4GPI 3F5VSS IOCF6VSS IOBF7VDD IOCF8VDD IOBF9VDD IODF10 VSS IODF11 VSS IODF12 VSS IODF13 VDD IODF14 KEY ROW2/ENET TXD3[2]F15 KEY COL0/ENET TX CLK[2]F16 KEY COL5/ENET RXD1[2]F17 U6 IRRX/GPI 21F18 U5 RX/GPI 20Row GG1EMC DYCS1G2FLASH IO[5]G3FLASH IO[6]G4RESOUTG5VSS IOCG6VDD IOCG7VDD COREG8VSS COREG9VDD COREG10 VSS COREG11 VDD COREG12 VSS COREG13 U7 HCTS/CAP0[1]/LCDCLKIN[1]/GPI 22G14 DBGENG15 KEY COL4/ENET RXD0[2]G16 U6 IRTXG17 SYSCLKEN/LCDVD[15][1]G18 JTAG TMSRow HH1EMC OEH2FLASH IO[0]H3FLASH IO[1]H4FLASH IO[4]H5VSS IOCH6VDD IOCH7VSS COREH12 VSS IODH13 VDD IOALPC3220 30 40 50Product data sheetDownloaded from Arrow.com.H14 JTAG TCKH15 U5 TXAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.7 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 3.PinPin allocation table (TFBGA296)SymbolH16 HIGHCORE/LCDVD[17][1]PinSymbolPinSymbolH17 JTAG NTRSTH18 JTAG RTCKEMC A[20]/P1[20]J2EMC A[21]/P1[21]J3EMC A[22]/P1[22]J4EMC A[23]/P1[23]J5VDD IOCJ6VDD EMCJ7VDD COREJ12VDD CORERow JJ1J13VDD IOAJ14U3 RX/GPI 18J15JTAG TDOJ16JTAG TDIJ17U3 TXJ18U2 HCTS/U3 CTS/GPI 16Row KK1EMC A[19]/P1[19]K2EMC A[18]/P1[18]K3EMC A[16]/P1[16]K4EMC A[17]/P1[17]K5VSS EMCK6VDD EMCK7VDD EMCK12 VSS COREK13 VSS IOAK14 VDD RTCK15 U1 RX/CAP1[0]/GPI 15K16 U1 TXK17 U2 TX/U3 DTRK18 U2 RX/U3 DSR/GPI 17Row LL1EMC A[15]/P1[15]L2EMC CKE1L3EMC A[0]/P1[0]L4EMC A[1]/P1[1]L5VSS EMCL6VDD EMCL7VSS COREL12 VDD COREFXDL13 VDD RTCCOREL14 VSS RTCCOREL15 P0[4]/I2S0RX WS/LCDVD[6][1]L16 P0[5]/I2S0TX SDA/LCDVD[7][1]L17 P0[6]/I2S0TX CLK/LCDVD[12][1]L18 P0[7]/I2S0TX WS/LCDVD[13][1]Row MM1EMC A[2]/P1[2]M2EMC A[3]/P1[3]M3EMC A[4]/P1[4]M4EMC A[8]/P1[8]M5VSS EMCM6VDD EMCM7VDD COREM8VDD EMCM9VSS COREM10 VSS COREM11 VDD COREM12 VSS COREM13 VDD COREFXDM14 RESETM15 ONSWM16 GPO 23/U2 HRTS/U3 RTSM17 P0[2]/I2S0RX SDA/LCDVD[4][1]M18 P0[3]/I2S0RX CLK/LCDVD[5][1]Row NN1EMC A[5]/P1[5]N2EMC A[6]/P1[6]N3EMC A[7/P1[7]N4EMC A[12]/P1[12]N5VSS EMCN6VSS EMCN7VDD EMCN8VDD EMCN9VDD EMCN10 VDD EMCN11 VDD EMCN12 VDD ADN13 VDD ADN14 VDD FUSEN15 VDD RTCOSCN16 GPI 5/U3 DCDN17 GPI 28/U3 RIN18 GPO 17Row PP1EMC A[9]/P1[9]P2EMC A[10]/P1[10]P3EMC A[11]/P1[11]P4EMC DQM[1]P5EMC DQM[3]P6VSS EMCLPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.8 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 3.Pin allocation table (TFBGA296)PinSymbolPinSymbolPinSymbolP7VSS EMCP8VSS EMCP9VSS EMCP10 VSS EMCP11 VSS EMCP12 EMC BLS[3]P13 VSS ADP14 VSS OSCP15 VDD PLLUSBP16 RTCX INP17 RTCX OUTP18 VSS RTCOSCRow RR1EMC A[13]/P1[13]R2EMC A[14]/P1[14]R3EMC DQM[0]R4EMC WRR5EMC CASR6EMC DYCS0R7EMC D[1]R8EMC D[7]R9EMC D[17]/EMC DQS1R10 EMC D[24]/P2[5]R11 EMC CS1R12 EMC BLS[2]R13 TS XPR14 PLL397 LOOPR15 SYSX OUTR16 VSS PLLUSBR17 VDD PLLHCLKR18 VSS PLLHCLKRow TT1EMC DQM[2]T2EMC RAST3EMC CLKT4EMC CLKINT5EMC D[2]T6EMC D[6]T7EMC D[11]T8EMC D[14]T9EMC D[20]/P2[1]T10 EMC D[23]/P2[4]T11 EMC D[27]/P2[8]T12 EMC CS2T13 EMC BLS[1]T14 ADIN1/TS XMT15 VSS PLL397T16 VDD PLL397T17 SYSX INT18 VDD OSCRow UU2n.c.U3EMC CKE0U4EMC D[0]U5EMC D[3]U6EMC D[9]U7EMC D[12]U8EMC D[15]U9EMC D[19]/P2[0]U10 EMC D[22]/P2[3]U11 EMC D[26]/P2[7]U12 EMC D[30]/P2[11]U13 EMC CS0U14 EMC BLS[0]U15 ADIN0/TS YMU16 TS YPU17 n.c.Row VV3EMC D[4]V4EMC D[5]V5EMC D[8]V6EMC D[10]V7EMC D[13]V8EMC D[16]/EMC DQS0V9EMC D[18]/EMC CLKV10 EMC D[21]/P2[2]V11 EMC D[25]/P2[6]V12 EMC D[28]/P2[9]V13 EMC D[29]/P2[10]V14 EMC D[31]/P2[12]V15 EMC CS3V16 ADIN2/TS AUX IN[1]LCD on LPC3230 and LPC3250 only.[2]Ethernet on LPC3240 and LPC3250 only.LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.9 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollers6.2 Pin descriptionTable 4.Pin descriptionSymbolPinPower supplydomainTypeDescriptionADIN0/TS YMU15VDD ADanalog inADC input 0/touch screen Y minusADIN1/TS XMT14VDD ADanalog inADC input 0/touch screen X minusADIN2/TS AUX INV16VDD ADanalog inADC input 2/touch screen AUX inputDBGENG14VDD IODI: PDDevice test inputLOW JTAG in-circuit debug available; normaloperation.HIGH I/O cell boundary scan test; for boardassembly BSDL test.EMC A[0]/P1[0]L3VDD EMCEMC A[1]/P1[1]L4VDD EMCEMC A[2]/P1[2]M1VDD EMCEMC A[3]/P1[3]M2VDD EMCEMC A[4]/P1[4]M3VDD EMCEMC A[5]/P1[5]N1VDD EMCEMC A[6]/P1[6]N2VDD EMCEMC A[7/P1[7]N3VDD EMCEMC A[8]/P1[8]M4VDD EMCEMC A[9]/P1[9]P1VDD EMCEMC A[10]/P1[10]P2VDD EMCI/OEMC address bit 0I/OPort 1 GPIO bit 0I/OEMC address bit 1I/OPort 1 GPIO bit 1I/OEMC address bit 2I/OPort 1 GPIO bit 2I/OEMC address bit 3I/OPort 1 GPIO bit 3I/OEMC address bit 4I/OPort 1 GPIO bit 4I/OEMC address bit 5I/OPort 1 GPIO bit 5I/OEMC address bit 6I/OPort 1 GPIO bit 6I/OEMC address bit 7I/OPort 1 GPIO bit 7I/OEMC address bit 8I/OPort 1 GPIO bit 8I/OEMC address bit 9I/OPort 1 GPIO bit 9I/OEMC address bit 10I/OPort 1 GPIO bit 10EMC A[11]/P1[11]P3VDD EMCI/OEMC address bit 11I/OPort 1 GPIO bit 11EMC A[12]/P1[12]N4VDD EMCI/OEMC address bit 12I/OPort 1 GPIO bit 12EMC A[13]/P1[13]R1VDD EMCI/OEMC address bit 13I/OPort 1 GPIO bit 13EMC A[14]/P1[14]R2VDD EMCI/OEMC address bit 14I/OPort 1 GPIO bit 14LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.10 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionEMC A[15]/P1[15]L1VDD EMCI/OEMC address bit 15I/OPort 1 GPIO bit 15EMC A[16]/P1[16]EMC A[17]/P1[17]EMC A[18]/P1[18]EMC A[19]/P1[19]EMC A[20]/P1[20]EMC A[21]/P1[21]EMC A[22]/P1[22]EMC A[23]/P1[23]K3K4K2K1J1J2J3J4VDD EMCVDD EMCVDD EMCVDD EMCVDD EMCVDD EMCVDD EMCVDD EMCI/OEMC address bit 16I/OPort 1 GPIO bit 16I/OEMC address bit 17I/OPort 1 GPIO bit 17I/OEMC address bit 18I/OPort 1 GPIO bit 18I/OEMC address bit 19I/OPort 1 GPIO bit 19I/OEMC address bit 20I/OPort 1 GPIO bit 20I/OEMC address bit 21I/OPort 1 GPIO bit 21I/OEMC address bit 22I/OPort 1 GPIO bit 22I/OEMC address bit 23I/OPort 1 GPIO bit 23EMC BLS[0]U14VDD EMCOStatic memory byte lane 0 selectEMC BLS[1]T13VDD EMCOStatic memory byte lane 1 selectEMC BLS[2]R12VDD EMCOStatic memory byte lane 2 selectEMC BLS[3]P12VDD EMCOStatic memory byte lane 3 selectEMC CASR5VDD EMCOSDRAM column address strobe out, active LOWEMC CKE0U3VDD EMCOClock enable out for SDRAM bank 0EMC CKE1L2VDD EMCOClock enable out for SDRAM bank 1EMC CLKT3VDD EMCOSDRAM clock outEMC CLKINT4VDD EMCISDRAM clock feedbackEMC CS0U13VDD EMCOEMC static memory chip select 0EMC CS1R11VDD EMCOEMC static memory chip select 1EMC CS2T12VDD EMCOEMC static memory chip select 2EMC CS3V15VDD EMCOEMC static memory chip select 3EMC D[0]U4VDD EMCI/O: BKEMC data bit 0EMC D[1]R7VDD EMCI/O: BKEMC data bit 1EMC D[2]T5VDD EMCI/O: BKEMC data bit 2EMC D[3]U5VDD EMCI/O: BKEMC data bit 3EMC D[4]V3VDD EMCI/O: BKEMC data bit 4EMC D[5]V4VDD EMCI/O: BKEMC data bit 5EMC D[6]T6VDD EMCI/O: BKEMC data bit 6EMC D[7]R8VDD EMCI/O: BKEMC data bit 7EMC D[8]V5VDD EMCI/O: BKEMC data bit 8LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.11 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionEMC D[9]U6VDD EMCI/O: BKEMC data bit 9EMC D[10]V6VDD EMCI/O: BKEMC data bit 10EMC D[11]T7VDD EMCI/O: BKEMC data bit 11EMC D[12]U7VDD EMCI/O: BKEMC data bit 12EMC D[13]V7VDD EMCI/O: BKEMC data bit 13EMC D[14]T8VDD EMCI/O: BKEMC data bit 14EMC D[15]U8VDD EMCI/O: BKEMC data bit 15EMC D[16]/EMC DQS0V8VDD EMCI/O: BKEMC data bit 16I/O: BKDDR data strobe 0EMC D[17]/EMC DQS1R9VDD EMCI/O: BKEMC data bit 17I/O: BKDDR data strobe 1EMC D[18]/EMC CLKV9VDD EMCI/O: PEMC data bit 18I/O: PDDR inverted clock outputEMC D[19]/P2[0]U9VDD EMCI/O: PEMC data bit 19EMC D[20]/P2[1]T9VDD EMCEMC D[21]/P2[2]V10VDD EMCEMC D[22]/P2[3]U10VDD EMCEMC D[23]/P2[4]T10VDD EMCEMC D[24]/P2[5]R10VDD EMCEMC D[25]/P2[6]V11VDD EMCEMC D[26]/P2[7]U11VDD EMCEMC D[27]/P2[8]T11VDD EMCEMC D[28]/P2[9]V12VDD EMCEMC D[29]/P2[10]V13VDD EMCEMC D[30]/P2[11]U12VDD EMCI/O: PPort 2 GPIO bit 0I/O: PEMC data bit 20I/O: PPort 2 GPIO bit 1I/O: PEMC data bit 21I/O: PPort 2 GPIO bit 2I/O: PEMC data bit 22I/O: PPort 2 GPIO bit 3I/O: PEMC data bit 23I/O: PPort 2 GPIO bit 4I/O: PEMC data bit 24I/O: PPort 2 GPIO bit 5I/O: PEMC data bit 25I/O: PPort 2 GPIO bit 6I/O: PEMC data bit 26I/O: PPort 2 GPIO bit 7I/O: PEMC data bit 27I/O: PPort 2 GPIO bit 8I/O: PEMC data bit 28I/O: PPort 2 GPIO bit 9I/O: PEMC data bit 29I/O: PPort 2 GPIO bit 10I/O: PEMC data bit 30I/O: PPort 2 GPIO bit 11EMC D[31]/P2[12]V14VDD EMCI/O: PEMC data bit 31I/O: PPort 2 GPIO bit 12EMC DQM[0]R3VDD EMCOSDRAM data mask 0 outLPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.12 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionEMC DQM[1]P4VDD EMCOSDRAM data mask 1 outEMC DQM[2]T1VDD EMCOSDRAM data mask 2 outEMC DQM[3]P5VDD EMCOSDRAM data mask 3 outEMC DYCS0R6VDD EMCOSDRAM active LOW chip select 0EMC DYCS1G1VDD EMCOSDRAM active LOW chip select 1EMC OEH1VDD EMCOEMC static memory output enableEMC RAST2VDD EMCOSDRAM row address strobe, active LOWEMC WRR4VDD EMCOEMC write strobe, active LOWFLASH ALED2VDD IOCOFlash address latch enableFLASH CEE3VDD IOCOFlash chip enableFLASH CLEF3VDD IOCOFlash command latch enableFLASH IO[0]H2VDD IOCI/O: BKFlash data bus, bit 0FLASH IO[1]H3VDD IOCI/O: BKFlash data bus, bit 1FLASH IO[2]F1VDD IOCI/O: BKFlash data bus, bit 2FLASH IO[3]E1VDD IOCI/O: BKFlash data bus, bit 3FLASH IO[4]H4VDD IOCI/O: BKFlash data bus, bit 4FLASH IO[5]G2VDD IOCI/O: BKFlash data bus, bit 5FLASH IO[6]G3VDD IOCI/O: BKFlash data bus, bit 6FLASH IO[7]E2VDD IOCI/O: BKFlash data bus, bit 7FLASH RDC1VDD IOCOFlash read enableFLASH RDYD1VDD IOCIFlash ready (from flash device)FLASH WRF2VDD IOCOFlash write enableGPI 0/I2S1RX SDAC16VDD IODGPI 1/SERVICEGPI 2/CAP2[0]/ENET RXD3C15C14VDD IODVDD IODIGeneral purpose input 0II2S1 Receive dataIGeneral purpose input 1IBoot select inputIGeneral purpose input 2ITimer 2 capture input 0IEthernet receive data 3 (LPC3240 and LPC3250only)GPI 3F4VDD IOCIGeneral purpose input 3GPI 4/SPI1 BUSYE13VDD IODIGeneral purpose input 4ISPI1 busy inputGPI 5/U3 DCDN16VDD IOAIGeneral purpose input 5IUART 3 data carrier detect inputGPI 6/HSTIM CAP/ENET RXD2C7VDD IOBI: BKGeneral purpose input 6I: BKHigh-speed timer capture inputI : BKEthernet receive data 2 (LPC3240 and LPC3250only)LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.13 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionGPI 7/CAP4[0]/MCABORTD13VDD IODIGeneral purpose input 7ITimer 4 capture input 0IMotor control PWM LOW-active fast abort inputGPI 8/KEY COL6/SPI2 BUSY/ENET RX DVB16IGeneral purpose input 8IKeyscan column 6 inputISPI2 busy inputIEthernet receive data valid input (LPC3240 andLPC3250 only)IGeneral purpose input 9IKeyscan column 7 inputIEthernet collision input (LPC3240 and LPC3250only)IGeneral purpose input 19IUART 4 receiveGPI 9/KEY COL7/ENET COLGPI 19/U4 RXGPI 28/U3 RIE12B15N17VDD IODVDD IODVDD IODVDD IOAIGeneral purpose input 28IUART 3 ring indicator inputGPIO 0A12VDD IODI/OGeneral purpose input/output 0GPIO 1A11VDD IODI/OGeneral purpose input/output 1GPIO 2/KEY ROW6/ENET MDCD9VDD IODI/OGeneral purpose input/output 2OKeyscan row 6 outputOEthernet PHY interface clock (LPC3240 andLPC3250 only)GPIO 3/KEY ROW7/ENET MDIOC11GPIO 4/SSEL1/LCDVD[22]B11GPIO 5/SSEL0/MCI0E9GPO 0/TST CLK1C3GPO 1D4GPO 2/MAT1[0]/LCDVD[0]B14GPO 3/LCDVD[1]D12GPO 4D8LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.VDD IODVDD IODVDD IODI/OGeneral purpose input/output 3I/OKeyscan row 7 outputI/OEthernet PHY interface data (LPC3240 andLPC3250 only)I/OGeneral purpose input/output 4I/OSSP1 Slave SelectI/OLCD data bit 22 (LPC3230 and LPC3250 only)I/OGeneral purpose input/output 5I/OSSP0 Slave SelectI/OMotor control channel 0 inputOGeneral purpose output 0OTest clock 1 outVDD IOCOGeneral purpose output 1VDD IODOGeneral purpose output 2OTimer 1 match output 0OLCD data bit 0 (LPC3230 and LPC3250 only)VDD IOCVDD IODVDD IOBOGeneral purpose output 3OLCD data bit 1 (LPC3230 and LPC3250 only)OGeneral purpose output 4All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.14 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionGPO 5B3VDD IOCOGeneral purpose output 5GPO 6/LCDVD[18]A16VDD IODOGeneral purpose output 6OLCD data bit 18 (LPC3230 and LPC3250 only)GPO 7/LCDVD[2]A15VDD IODOGeneral purpose output 7OLCD data bit 2 (LPC3230 and LPC3250 only)GPO 8/LCDVD[8]C13VDD IODOGeneral purpose output 8OLCD data bit 8 (LPC3230 and LPC3250 only)GPO 9/LCDVD[9]C12VDD IODOGeneral purpose output 9OLCD data bit 9 (LPC3230 and LPC3250 only)GPO 10/MCOB2/LCDPWRE11OGeneral purpose output 10GPO 11E8VDD IOBGPO 12/MCOA2/LCDLEB12VDD IODGPO 13/MCOB1/LCDDCLKB13GPO 14D3GPO 15/MCOA1/LCDFPA14GPO 16/MCOB0/LCDENAB/LCDMD10GPO 17N18VDD IOAGPO 18/MCOA0/LCDLPD11VDD IODGPO 19C2VDD IOCOGeneral purpose output 19GPO 20B2VDD IOCOGeneral purpose output 20GPO 21/U4 TX/LCDVD[3]A13VDD IODOGeneral purpose output 21OUART 4 transmitOLCD data bit 3 (LPC3230 and LPC3250 only)LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.VDD IODVDD IODOMotor control PWM channel 2, output BOLCD panel power enable (LPC3230 and LPC3250only)OGeneral purpose output 11OGeneral purpose output 12OMotor control PWM channel 2, output AOLCD line end signal (LPC3230 and LPC3250 only)OGeneral purpose output 13OMotor control PWM channel 1, output BOLCD clock output (LPC3230 and LPC3250 only)VDD IOCOGeneral purpose output 14VDD IODOGeneral purpose output 15VDD IODOMotor control PWM channel 1, output AOLCD frame/sync pulse (LPC3230 and LPC3250only)OGeneral purpose output 16OMotor control PWM channel 0, output BOLCD STN AC bias/TFT data enable (LPC3230 andLPC3250 only)OGeneral purpose output 17OGeneral purpose output 18OMotor control PWM channel 0, output AOLCD line sync/horizontal sync (LPC3230 andLPC3250 only)All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.15 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionGPO 22/U7 HRTS/LCDVD[14]E10VDD IODOGeneral purpose output 22OHS UART 7 RTS outOLCD data bit 14 (LPC3230 and LPC3250 only)GPO 23/U2 HRTS/U3 RTSM16OGeneral purpose output 23OHS UART 2 RTS outOUART 3 RTS outHIGHCORE/LCDVD[17]H16I2C1 SCLA5I2C1 SDAVDD IOAVDD IODOCore voltage control outOLCD data bit 17 (LPC3230 and LPC3250 only)VDD IOBI/O TI2C1 serial clock input/outputB6VDD IOBI/O TI2C1 serial data input/outputI2C2 SCLA3VDD IOCI/O TI2C2 serial clock input/outputI2C2 SDAE4VDD IOCI/O TI2C2 serial data input/outputI2S1TX CLK/MAT3[0]A4VDD IOBI/OI2S1 transmit clockOTimer 3 match output 0I2S1TX SDA/MAT3[1]E7I/OI2S1 transmit dataOTimer 3 match output 1I2S1TX WS/CAP3[0]B4I/OI2S1 transmit word selectI/OTimer 3 capture input 0JTAG NTRSTH17VDD IODI: PUJTAG1 reset input. Must be LOW during power-onreset. See Section 12.1 “Connecting theJTAG NTRST pin”.JTAG RTCKH18VDD IODOJTAG1 return clock outVDD IOBVDD IOBJTAG TCKH14VDD IODIJTAG1 clock inputJTAG TDIJ16VDD IODI: PUJTAG1 data inputJTAG TDOJ15VDD IODOJTAG1 data outJTAG TMSG18VDD IODI: PUTAG1 test mode select inputKEY COL0/ENET TX CLKF15VDD IODIKeyscan column 0 inputIEthernet transmit clock (LPC3240 and LPC3250only)KEY COL1/ENET RX CLK/ENET REF CLKE16IKeyscan column 1 inputIEthernet receive clock (MII mode, LPC3240 andLPC3250 only)IEthernet reference clock (RMII mode, LPC3240 andLPC3250 only)KEY COL2/ENET RX ERD17KEY COL3/ENET CRSD18LPC3220 30 40 50Product data sheetDownloaded from Arrow.com.VDD IODVDD IODVDD IODIKeyscan column 2 inputIEthernet receive error input (LPC3240 andLPC3250 only)IKeyscan column 3 inputIEthernet carrier sense input (LPC3240 andLPC3250 only)All information provided in this document is subject to legal disclaimers.Rev. 2.1 — 24 June 2014 NXP Semiconductors N.V. 2014. All rights reserved.16 of 80
LPC3220/30/40/50NXP Semiconductors16/32-bit ARM microcontrollersTable 4.Pin description continuedSymbolPinPower supplydomainTypeDescriptionKEY COL4/ENET RXD0G15VDD IODIKeyscan column 4 inputIEthernet receive data 0 (LPC3240 and LPC3250only)KEY COL5/ENET RXD1F16IKeyscan column 5 inputIEthernet receive data 1 (LPC3240 and LPC3250only)KEY ROW0/ENET TX ERE15KEY ROW1/ENET TXD2E14KEY ROW2/ENET TXD3F14KEY ROW3/ENET TX END16KEY ROW4/ENET TXD0C17KEY ROW5/ENET TXD1C18MS BS/MAT2[1]A6MS DIO0/MAT0[0]A8MS DIO1/MAT0[1]A7MS DIO2/MAT0[2]B8MS DIO3/MAT0[3]C8MS SCLK/MAT2[0]B7n.c.B17,VDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODVDD IODI/O TKeyscan row 0 outI/O TEthernet transmit error (LPC3240 and LPC3250only)I/O TKeyscan row 1 outI/O TEthernet transmit data 2 (LPC3240 and LPC3250only)I/O TKeyscan row 2 outI/O TEthernet transmit data 3 (LPC3240 and LPC3250only)I/O TKeyscan row 3 outI/O TEthernet transmit enable (LPC3240 and LPC3250only)I/O TKeyscan row 4 out
to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs. 32-bit millisecond timer driven from th e RTC clock. This timer can generate interrupts using two match registers. WatchDog timer clocked by the peripheral clock.
range. Combining PFC and HBC controllers in a single IC makes the TEA1713 ideal for controlling power supplies in LCD and plasma televisions. Highly efficient and reliable power supplies pr oviding over 100 W can be designed easily using the TEA1713, with a minimum of external components. TEA1713T R
Marking Examples C 10 µF C 10µF Approvals Approval marks Standards Certificate EN 60384-14, IEC 6038
The following document contains information on Cypress products. The document has the series QDPH SURGXFWQ
Designed for applications acc. MIL-STD Certificate Number: 202F Method 107G, 202F Method 204D, 202F Method 213B, 416D Method RS103, 810E Method 501.3, 810E
Page 2 ams Datasheet Document Feedback [v1-01] 2018-Jan-23 TSL2541 Š General Description . 1.5 ms Electrical Characteristics Downloaded from Arrow.com. Page 6 ams Datasheet Document Feedback [v1-01] 2018-Jan-23 . 300 400 500 600 700 800 900 1000 1100 Normalized Responsivity Wavelength (n
General tolerances according to ISO 2768 cL Dimensions in mm B84143A0066R105 (66 A) General tolerances according to ISO 2768 cL Dimensions in mm 3-line filters B84143A*R105 for converters and power elect
Specifications (characteristics) Item Symbol Specifications *2 Conditions / Remarks PT / ST PH / SH PC / SC Output frequency range f 0 1 MHz to 125 MHz -V CC 4.5 V to 5.5 V (except SG-8002LB) -1 MHz to 80 MHz -V CC 4.5 V to 5.5 V (SG-8002LB only) - - 1 MHz to 125 MHz V CC 3.0 V to 3.6 V - - 1 MHz to 66.7 MHz V CC 2.7 V t
Amrit Hindi Pathmala Series Jagriti Sulekhmala Series Jagriti Hindi Vyakaran Series Semester Series General Knowledge Series Value Education Series Toddler Trot Series Story Books AUP Worksheets General Books Effective from 1st Nov 2018 School Books Price List About Happy Hour Books There is nothing more precious in this world than our children, and nothing more enjoyable than happy children .
