AN 8 BIT, 100MS/s PIPELINE ADC WITH PARTIAL POSITIVE FEEDBACK AMPLIFIER .

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AN 8 BIT, 100MS/s PIPELINE ADC WITH PARTIAL POSITIVE FEEDBACKAMPLIFIER FOR COGNITIVE RADIO APPLICATIONSA ThesisbySYLVESTER ANKAMAH-KUSISubmitted to the Office of Graduate and Professional Studies ofTexas A&M Universityin partial fulfillment of the requirements for the degree ofMASTER OF SCIENCEChair of Committee,Committee Members,Head of Department,Aydin KarsilayanEdgar Sanchez-SinencioPeng LiHank WalkerMiroslav M. BegovicDecember 2016Major Subject: Electrical EngineeringCopyright 2016 Sylvester Ankamah-Kusi

ABSTRACTThis thesis focuses on designing a low power Pipeline Analog to DigitalConverter (ADC) for use in a Cognitive radio network. The Pipeline ADC architectureis one of the most suitable ADC architectures for applications requiring moderate tohigh operating speeds and resolution while consuming low power. The designed ADCintroduces a Partial Positive Feedback amplifier which yields high gain with minimalpower consumption without a need for a common mode feedback. A multiplexer–based Multiplying Digital to Analog Converter (MDAC) is also introduced. Themultiplexer–based MDAC mitigates the capacitor mismatch effect encountered in theconventional MDAC. Clocked bootstrapped switches are designed to maintainconstant on-resistance desired in switches.With a power supply of 2.4V, the Pipeline ADC consumed a total power of8.2mW and achieved a Signal-to-Noise-and-Distortion Ratio (SNDR) of 48.08 dBwhich corresponds to an Effective Number of Bits (ENOB) of 7.69 bits at the Nyquistfrequency. A Differential Non-Linearity error (DNL) of less than 1 LSB ensuringthat all codes corresponding to an 8 bit ADC are available. The Partial PositiveFeedback amplifier used achieved an open loop gain of 51 dB while consuming1.8mA of current. The designed Pipeline ADC achieved a Figure of Merit (FoM) of0.38 pJ/conversion step.ii

ACKNOWLEDGEMENTSMy foremost gratitude goes to the almighty God whose mercies have seen methrough this journey. I will also like to thank my family for the constant supportextended to me throughout my graduate school education.I am exceedingly thankful to my advisor, Professor Aydin Karsilayan, for theguidance and support throughout my time at Texas A&M University. I couldn’t askfor a better advisor.My sincerest appreciation goes to Dee Hunter, Tuli Dake, Benjamin Sarpongand all the pioneers of the Texas Instruments African Analog University RelationsProgram (TI-AAURP) for the opportunity given to me to pursue my graduateeducation.I also want to thank Professor Jose Silva Martinez for assisting me in thecourse of my research work with ideas and suggestions to help improve my design. Iam grateful to all members of the Analog and Mixed Signal Center of Texas A &MUniversity for all the knowledge they imparted to me in the course of my stay. I amalso sincerely thankful to Dr. Edgar Sanchez-Sinencio, Dr. Peng Li and Dr. HankWalker for serving as members on my thesis committee.Finally, I want to say a big thank you to Jeffrey Okyere, Samuel AnnorFordjour, Renato Gabriel Barbosa Perreira and Junning Jiang for their immensesupport during my stay at TAMU. God richly bless you.iii

TABLE OF CONTENTSPageABSTRACT . iiACKNOWLEDGEMENTS .iiiTABLE OF CONTENTS . ivLIST OF FIGURES . viLIST OF TABLES . viiiINTRODUCTION . 1Thesis Organization . 2OVERVIEW. 3ADC Architectures. 3Flash ADC. 4Successive Approximation Register (SAR) Architecture . 5ADC Resolution Limiting Factor . 7Figure of Merit . 9PIPELINE ADC ARCHITECTURE OVERVIEW. 10Pipelined ADC Introduction . 10Multiplying Digital to Analog Converter (MDAC) . 12Operational Amplifier (Op-amp) DC Gain Requirement . 15Op-amp Gain Bandwidth Product (GBW) Requirement . 17Operational Amplifier Topologies . 18Thermal Noise Requirement . 19Capacitor Mismatch. 20Sub–ADC Design . 21Frontend Sample and Hold . 22PIPELINE POWER EFFICIENCY . 24iv

PagePower Consumption in Switched Capacitor Networks . 24Power Consumption in Pipeline ADC . 25Power Reduction Techniques. 26Sample and Hold-less Approach . 26Stage Scaling and Optimized Stage Resolution . 30Open Loop Amplifier Approach . 31Capacitive Charge Pump Based MDAC . 33THE DESIGNED 8 BIT PIPELINE ADC . 36Design Considerations . 36Topology of the Designed Pipeline ADC . 38Sub–ADC Comparator . 39Multiplexer Based Thermometer to Binary Decoder . 40Operational Amplifier . 41Multiplying Digital to Analog Converter . 53Bootstrapped Switch . 55Final Block Level Schematic of Designed ADC . 58Simulation Results . 59CONCLUSION . 63REFERENCES . 64v

LIST OF FIGURESPageFigure 2.1: Flash ADC architecture . 4Figure 2.2: Block diagram of the SAR ADC [6] . 6Figure 2.3: Operation of a 4 bit SAR ADC, Reprinted from [2]. . 6Figure 2.4: Effect of noise and distortion on ENOB, Reprinted from [7] . 8Figure 3.1: Block diagram of a Pipeline ADC. 10Figure 3.2: 7 clock cycle latency of a Pipelined ADC, Reprinted from [10] . 12Figure 3.3: Conventional N-Bit MDAC . 13Figure 3.4: Ideal residue curve of a 1.5 bit MDAC with 1V input full scale voltage. . 14Figure 3.5: Effect of gain error on 1.5 bit residue curve. . 16Figure 3.6: RC model with noise sources . 19Figure 3.7: Effect of capacitor mismatch on the residue curve of the 1.5 bit MDAC 21Figure 3.8: Different instantaneous voltages sampled by Sub-ADC and MDAC . 23Figure 4.1: Same input sampling switch for time constant matching[20] . 27Figure 4.2: Separate input sampling switches for time constant matching[21] . 29Figure 4.3: Pipeline structure resolving 1 bit per stage, Reprinted from [22] . 30Figure 4.4: Closed loop amplifier. 32Figure 4.5: 4-bit MDAC using an amplifier in open loop, Reprinted from [24] . 32Figure 4.6: Capacitive Charge Pump based MDAC [2] . 34Figure 5.1: Block diagram of the designed Pipeline ADC . 38Figure 5.2:Dynamic Comparator with kickback noise reduction[26] . 40Figure 5.3: Multiplexer based Encoder for a 3 bit Flash ADC [27] . 41Figure 5.4: Conventional Single Stage Amplifier . 42Figure 5.5: Proposed Partial Positive Feedback Amplifier . 43Figure 5.6: Maximum gain condition against varying resistor ratio. . 46Figure 5.7: Maximum gain condition against varying resistor values . 47Figure 5.8: Gain variation against varying resistor values . 47vi

PageFigure 5.9: Gain variation for varying resistor values across all corners .48Figure 5.10: AC response of Partial Positive Feedback amplifier. . 48Figure 5.11: Gate voltage not changing as a function of output voltage. . 50Figure 5.12: Gate voltage changing as a function of output voltage. . 51Figure 5.13: Layout of Partial Positive Feedback Amplifier . 52Figure 5.14: Post layout AC response . 53Figure 5.15: Multiplexer based MDAC . 54Figure 5.16: NMOS Switch . 55Figure 5.17: Transmission gate . 56Figure 5.18: Clocked Bootstrap Switch [29] . 56Figure 5.19: Operation of Clocked bootstrap switch . 57Figure 5.20: Final Block Level Schematic of Designed ADC . 58Figure 5.21: Frequency spectrum at 24.9MHz . 60Figure 5.22: DNL and INL at 8 bits . 61Figure 5.23: SFDR and SNDR across the input frequency range . 62vii

LIST OF TABLESPageTable 2.1 Comparison of ADC Topologies . 3Table 3.1: Comparison of Op-amp topologies . 18Table 5.1: Proposed amplifier against conventional single stage amplifier . 49Table 5.2: Results summary and comparison . 59viii

INTRODUCTIONThe recent increase in the number of wireless communication devices, as wellas the fixed allocation of communication channels to licensed users has led to overcrowdedness and inefficient utilization of the Radio Frequency (RF) spectrum. Thereis the need for a dynamic approach of spectrum allocation to ensure a more efficientutilization of the RF spectrum. The concept of cognitive radio has been proposed asan approach for efficient spectrum utilization.A cognitive radio network refers to a communication system equipped withthe capability to sense the RF spectrum, identify vacant communication channels anddynamically adjust its operating parameters to transmit within the available channelwithout affecting the Quality of Service (QoS) of the licensed user. Its main objectiveis to improve spectrum-usage efficiency [1]. In the operation of any cognitive radionetwork, the sensed spectrum needs to be digitized by an Analog to Digital Converter(ADC) before subsequent processing can take place.An ADC refers to a system that converts an analog signal into a digital signal.ADC architectures, notably the Flash ADC, Successive Approximation Register (SAR)ADC and the Pipeline ADC have evolved over the years, each offering one advantageover the other. High speed of operation while resolving a high number of bits withlittle power consumption are the desirable features in any ADC.The Pipeline ADC architecture is suitable for applications requiring mediumhigh resolutions while operating at sampling rates in the order of MS/s [2]. Forhigher resolution, the Pipeline architecture requires a significantly reduced numberof comparators making it even more attractive than the Flash, despite the ability ofthe Flash to operate at higher speed. The SAR ADC has the capability of operating atsimilar resolutions to the Pipeline architecture but limited to medium speedapplications.1

Due to the continuous nature of the Cognitive radio network, reducing thepower consumption of the ADC is very important to ensure that the Cognitive radionetwork can operate with as minimal power consumption as possible. The pipelinearchitecture offers the best trade-off between high operating speed, resolution andpower consumption [3].In this thesis, various types of ADCs are reviewed along with the advantagesand disadvantages of each. An in-depth review of the Pipeline ADC is presentedhighlighting techniques that have been used in previous designs. The designedPipeline ADC with a proposed Partial Positive Feedback Amplifier which consumesvery little power while achieving high gain is presented.Thesis OrganizationThis thesis is organized into six chapters: Chapter one introduces theproblem. In Chapter two, the Successive Approximation Register (SAR) ADC and theFlash ADC architectures are reviewed. The factors limiting the achievable ADCresolution are highlighted. The chapter also outlines the most popular figure of meritby which ADCs are compared. Chapter three gives an in-depth analysis of the PipelineADC, outlining all the design requirements of the major building blocks. In Chapterfour, power consumption of the Pipeline ADC and techniques to reduce it arereviewed. Chapter five presents the designed 8 bits 100MS/s Pipeline ADC,describing all building blocks and innovations. The simulation results of the designedconverter is presented in this chapter. The thesis is concluded in Chapter 6 with asummary of the major techniques used and results obtained.2

OVERVIEWIn this chapter, the SAR and Flash ADCs are reviewed and the limiting factorsto the achievable ADC resolution is outlined. The most popular figure of merit bywhich ADCs are compared is also presented.ADC ArchitecturesThe main factors that affect the choice of a particular architecture are powerconsumption, resolution and speed of operation. Ideally, a low power consumptionwhile resolving more bits at a high sampling rate is desired. Unfortunately, there aretradeoffs between each of these and hence several architectures have over the yearsevolved to achieve the optimal performance.The ADC architectures focused on in this section are the SuccessiveApproximation Register (SAR) and the Flash ADC. The advantages and disadvantagesof each is reviewed. A table of comparison summarizing the tradeoffs between thevarious ADC architectures is shown in Table 2.1.Table 2.1 Comparison of ADC HighMediumMedium-High3

Flash ADCThe Flash ADC architecture is shown in Figure 2.1. It deploys the use of fixedreference voltages, usually generated by a resistive ladder to digitize an analog inputsignal by comparing it with each of the fixed references. The number of referencesgenerated is dependent on the resolution of the ADC according to the relation 2𝑁 1; where N is the resolution of the Flash ADC. For example, a 10 bit Flash ADC wouldrequire 210 1 1023 reference values. Each reference value corresponds to oneunique comparator. Therefore, for a 10 bit resolution, the Flash ADC would require1023 comparators. Each comparator is biased to compare the input voltage to aunique reference voltage [4]. The decision taken by all comparators is collectivelyknown as a Thermometer code. A Digital Encoder is subsequently needed to convertthe Thermometer code to the N-bit binary code which is to be read out.Figure 2.1: Flash ADC architecture4

As the number of references increases, the resolution increases and subsequentlythe accuracy of conversion increases. However, the comparator count and hencepower consumption of the Flash ADC increases exponentially with resolution. Thisconstraint puts a limitation on the maximum number of bits practically realizablewith the Flash ADC. As previously stated, to resolve 10 bits a Flash ADC wouldrequire 1023 comparators. This would consume an excessive amount of power andmakes the Flash topology unsuitable for high resolutions.A major advantage of the Flash topology lies in its speed. The Flash ADC is avery attractive choice for analog to digital conversion in high speed applications likeradar detection, wide band radio receivers and optical communication links [5]. Thelatency of the Flash architecture is limited to one clock cycle (i.e., the n-bit binarycode is available exactly one clock cycle after sampling the input), making it thefastest ADC available.Successive Approximation Register (SAR) ArchitectureThe block diagram of the SAR ADC is shown in Figure 2.2. It consists of aSample and Hold (S/H), a single comparator, an N bit Digital to Analog Converter(DAC), an N bit register and a digital control logic. In its operation, the analog inputvoltage is first sampled by a Sample and Hold circuit operating at the Nyquist rate.The digital control logic determines the value of each bit based on the output of thecomparator. It initially sets the most significant bit (MSB) to ‘1’ and all other bits to‘0’. This digital word is applied to the DAC, which generates an analog signal which isat the mid-point of the full scale input voltage (Vfull-scale/2). If the sampled inputvoltage happens to be greater than Vfull-scale/2, the MSB of the N-bit register5

Figure 2.2: Block diagram of the SAR ADC [6]remains at ‘1’, otherwise it changes to ‘0’. This is repeated successively until all N bitsare resolved, each time resetting the current bit to be resolved in the N-bit registerto ‘1’ and all other bits yet to be resolved to ‘0’. In all, N iterations of the algorithmare performed to resolve all N bits. The operation of a 4 bit SAR ADC is shown inFigure 2.3.Figure 2.3: Operation of a 4 bit SAR ADC, Reprinted from [2].6

The MSB is initially set to 1 and all other bits set to 0. The digital word isapplied to the DAC which generates an analog voltage of 0.5𝑉𝑟𝑒𝑓 with which thecomparator compares the input voltage. Since the input voltage is less than the initialreference, the output of the comparator is low and the MSB is changed to 0 by thedigital control logic. This completes the first step in the approximation sequence. Thesequence is repeated 4 times till all 4 bits are resolved. The major advantage of theSAR ADC architecture is the reduced number of analog components used, mostnotably a single comparator regardless of the number of bits to be resolved. Asanalog components consume the most power, this advantage helps in reducingpower consumption, as well as area.The design of the SAR logic, DAC and comparator however proves to be verychallenging. For the ADC to operate effectively at Nyquist sampling rate of fs, each ofthe above mentioned components must operate at N.fs ; where N is the number ofbits and fs is the sampling rate [2]. For instance, to operate at a sampling rate of500MHz with a resolution of 10 bits, each component would be required to operateat 5GHz which proves quite challenging. This limits the realizable speed of the SARarchitecture to low-to-medium speed applications. However, it is very suitable formedium to high accuracy applications.ADC Resolution Limiting FactorThe Effective Number of Bits (ENOB) achievable by an ADC is limited by theSignal to Noise and Distortion Ratio (SNDR) as shown below;𝐸𝑁𝑂𝐵 𝑆𝑁𝐷𝑅 1.766.02[7](2.1)The Signal to Noise and distortion Ratio is the ratio of the signal power to thesummation of the power of all noise sources and total distortion. From (2.1), it is7

evident that the effective resolution of the ADC is dependent on the signal amplitude,linearity of the ADC and the total noise. Ideal ENOB is only obtained with zeroelectronic noise and no distortion which is practically not achievable. Hence toachieve a high ENOB, a highly linear and low noise ADC design is required.Figure 2.4: Effect of noise and distortion on ENOB, Reprinted from [7]Figure 2.4 shows the difference between the actual bits designed for and theeffective bits obtained due to degradation by noise across a range of frequencies.Ideally, this difference should be zero. This is however practically not possible toattain. An average difference of 1.43 bits is observed across all sampling frequencies.8

Figure of MeritThe Figure of Merit (FoM) provides a basis for comparing the performance ofvarious ADCs. The most popular Figure of Merit by which ADCs are compared is givenby;𝐹𝑜𝑀𝑝 𝑃𝑜𝑤𝑒𝑟(pJ/conv. bit) [8]2𝐸𝑁𝑂𝐵 . 𝑓𝑠(2.2)To normalize (2.2) with respect to the supply voltage, a new Figure of Merit is givenby;𝑖𝐹𝑜𝑀 𝐶𝑢𝑟𝑟𝑒𝑛𝑡(pA/conv. bit)2𝐸𝑁𝑂𝐵 . 𝑓𝑠9(2.3)

PIPELINE ADC ARCHITECTURE OVERVIEWThe Pipeline ADC architecture is presented in this chapter. The variousbuilding blocks are analyzed and the effects of non-idealities on the performance ofthe ADC is evaluated.Pipelined ADC IntroductionPipeline architectures mainly resolve medium-to-high resolutions (8 – 14bits) while operating at medium-to-high sampling rates (a few MHz to hundreds ofMHz). The generic block diagram of the Pipeline ADC is shown in Figure 3.1. Itconsists of a number of identical stages, each resolving n number of bits cascaded toresolve a total of N bits. Each stage consists of a sub–ADC (usually a Flash), S/H, DAC,summer and an operational amplifier.Figure 3.1: Block diagram of a Pipeline ADC10

The Sub–ADC resolves n bits in each stage as shown in Figure 3.1. The resolved digitalbits are converted back into an analog signal and compared with the sampled inputsignal. The difference, known as the residue, is amplified by the operational amplifierand fed to the next stage. The residue is amplified to full scale in order to maximizethe dynamic range of the ADC. The amplification factor is 2𝑛 ; where n is the numberof bits resolved in a stage. The functions of the S/H, DAC, summer and operationalamplifier are all combined in one switched capacitor network known as MultiplyingDigital to Analog Converter (MDAC). Due to the reduced number of bits resolved perstage, the comparator count for the Pipeline architecture is significantly reduced ascompared to the Flash architecture. For medium to high resolutions (8 – 14 bits), thePipeline architecture shows considerable power savings over the Flash architecture.The resolution of the Pipeline ADC is typically comparable to that of the SAR.However, the Pipeline architecture is more favored for higher sampling rates since itdoes not require components operating N. fs, unlike the SAR which requires multiplecomponents operating at N. fs. Precision requirements for each of the componentsdecrease along the Pipeline making design of subsequent stages simpler [9]. Latencyis however more pronounced in the Pipeline structure than it is in the SAR or Flasharchitectures. The digital word in the pipelined architecture is obtained after n clockcycles; where n is the number of stages, whereas in the Flash, it only takes one clockcycle to obtain the digital data.11

Figure 3.2: 7 clock cycle latency of a Pipelined ADC, Reprinted from [10]Figure 3.2 shows the timing diagram of a 7 stage Pipeline ADC. The digital word inthis Pipeline structure would be obtained after 7 clock cycles as shown.Multiplying Digital to Analog Converter (MDAC)As stated in the previous section, the functions of the S/H, DAC, summer andoperational amplifier can be combined into one switched capacitor network knownas the MDAC. The MDAC and Sub–ADC make up each Pipeline stage as shown inFigure 3.3.12

Figure 3.3: Conventional N-Bit MDACThe operation of the MDAC is as follows: In the first phase (Ф1), the inputvoltage is sampled onto all sampling capacitors (C1-Cn). Bottom plate sampling isdone to reduce signal dependent charge injection on sampling capacitors [11] . Atthe same time, the Sub–ADC would have resolved the n bits for that particular stage.The charge 𝑄1 accumulated in Ф1 on the sampling capacitors (𝐶1 to 𝐶𝑛 ) in Figure 3.3is given by:2𝑛𝑄1 𝐶𝑖 . 𝑉𝑖𝑛(3.1)1where 𝑉𝑖𝑛 is the input voltage, 𝐶𝑖 is the ith sampling capacitor, 𝑛 is the number ofbits. In the second phase (Ф2) the comparator output (thermometer code) isconverted into analog voltage (0 or Vref) and is subtracted from the initial inputvoltage sampled on each of the sampling capacitors and the resulting voltage isamplified at the output. The 2𝑛 𝑡ℎ (Cn) capacitor is however always grounded in the13

second phase. The charge 𝑄2 accumulated in Ф2 on the sampling capacitors (𝐶1to 𝐶𝑛 ) in Figure 3.3 is given by:2n 1Q2 1(Ci b. Vfull scale ) VOut Cf(3.2)where b is the thermometer code, 𝑉𝑓𝑢𝑙𝑙 𝑠𝑐𝑎𝑙𝑒 is the full-scale input voltage, 𝑉𝑜𝑢𝑡 is theresidue voltage. Applying the law of conservation of charges, 𝑉𝑂𝑢𝑡 could be expressedas:𝑛𝑛 1 21 21 𝐶𝑖 . 𝑉𝑖𝑛 𝐶𝑓𝐶𝑖 . 𝑏. .3)Figure 3.4: Ideal residue curve of a 1.5 bit MDAC with 1V input full scale voltage.Figure 3.4 shows the ideal residue curve of a 1.5 bit MDAC with an input full-scalevoltage of 1V.14

Operational Amplifier (Op-amp) DC Gain RequirementEquation (3.3) was derived based on the assumption that the operationalamplifier used in the MDAC has infinite gain and bandwidth. With finite gain, theequation becomes:Voutnn 1 21 Ci 21 [().Vin ] [1Cf1 Aβ1Ci . b. Vfull scale]Cf(3.4)where 𝐴 is the open loop gain, 𝛽 is the feedback factor. The direct transfer functionfrom the input to the output is:VoutA finite gain error of1𝐴𝛽n 21 Ci ().Vin1Cf1 Aβ1(3.5)is introduced. This error alters the residue transfer curvefrom the ideal curve as shown in Figure 3.5 resulting in missing codes in the entirepipeline structure and subsequently leading to harmonic distortion. Consequently,the accuracy and linearity of the Pipeline ADC is limited. To avoid this, the op-ampneeds to be designed with a gain high enough to reduce the gain error.15

Figure 3.5: Effect of gain error on 1.5 bit residue curve.To avoid any missing codes, the maximum gain error ( 𝑚𝑎𝑥 ) should be less than theleast significant bit (LSB) of the data converter. The maximum gain error occurswhen the input voltage is maximum [12] (i.e. 𝑉𝑖𝑛 𝑉𝑓𝑢𝑙𝑙 𝑠𝑐𝑎𝑙𝑒 ). Hence for 𝑚𝑎𝑥 ,(3.5) can be re-written as:Voutn 21 Ci ().Vfull scale1Cf1 Aβ1(3.6)The maximum gain error is given by;Vfull scaleAβThe LSB of any data converter is given by: 𝑚𝑎𝑥 LSB Vfull scale2N(3.7)(3.8)Since max should be kept below an LSB of the data converter, the minimum openloop gain (𝐴𝑚𝑖𝑛 ) required is given by:𝐴𝑚𝑖𝑛2N β16(3.9)

Clearly, a large DC gain is required in the MDAC circuit. As technology scales,achieving large DC gain from op-amps becomes very challenging. Several analogtechniques such as gain boosting [13], multi-stage op-amps [14] or longer channeldevices have been used to help increase op-amp gain. These techniques howeverresult in either increased power consumption (gain boosting), reduction in speed ofthe ADC (multi-stage) or

An ADC refers to a system that converts an analog signal into a digital signal. ADC architectures, notably the Flash ADC, Successive Approximation Register (SAR) ADC and the Pipeline ADC have evolved over the years, each offering one advantage over the other. High speed of operation while resolving a high number of bits with

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