12 Advanced-control Timer (TIM1)

1y ago
4 Views
1 Downloads
1.70 MB
174 Pages
Last View : 22d ago
Last Download : 2m ago
Upload by : Dahlia Ryals
Transcription

RM036812Advanced-control timer (TIM1)Advanced-control timer (TIM1)TIM8 is not available in STM32F401xB/C and STM32F401xD/E.12.1TIM1 introductionThe advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by aprogrammable prescaler.It may be used for a variety of purposes, including measuring the pulse lengths of inputsignals (input capture) or generating output waveforms (output compare, PWM,complementary PWM with dead-time insertion).Pulse lengths and waveform periods can be modulated from a few microseconds to severalmilliseconds using the timer prescaler and the RCC clock controller prescalers.The advanced-control (TIM1) and general-purpose (TIMx) timers are completelyindependent, and do not share any resources. They can be synchronized together asdescribed in Section 12.3.20.DocID025350 Rev 4241/841310

Advanced-control timer (TIM1)12.2RM0368TIM1 main featuresTIM1 timer features include:242/841 16-bit up, down, up/down auto-reload counter. 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clockfrequency either by any factor between 1 and 65536. Up to 4 independent channels for:–Input Capture–Output Compare–PWM generation (Edge and Center-aligned Mode)–One-pulse mode output Complementary outputs with programmable dead-time Synchronization circuit to control the timer with external signals and to interconnectseveral timers together. Repetition counter to update the timer registers only after a given number of cycles ofthe counter. Break input to put the timer’s output signals in reset state or in a known state. Interrupt/DMA generation on the following events:–Update: counter overflow/underflow, counter initialization (by software orinternal/external trigger)–Trigger event (counter start, stop, initialization or count by internal/external trigger)–Input capture–Output compare–Break input Supports incremental (quadrature) encoder and hall-sensor circuitry for positioningpurposes Trigger input for external clock or cycle-by-cycle current managementDocID025350 Rev 4

RM0368Advanced-control timer (TIM1)Figure 39. Advanced-control timer block diagram,QWHUQDO &ORFN &.B,17# ?4)- FROM 2##(75)7ULJJHU&RQWUROOHU(753(754)-X?%423RODULW\ 6HOHFWLRQ (GJH'HWHFWRU 3UHVFDOHU42'/,QSXW )LOWHU,75 ,75 TO OTHER TIMERSTO ! #7*,,75,75 75&75*,,75 6ODYH0RGH&RQWUROOHU5HVHW (QDEOH 8S 'RZQ &RXQW7, )B('7, )3 (QFRGHU,QWHUIDFH7, )3 5(3 5HJLVWHU8,8 XWR5HORDG 5HJLVWHU5HSHWLWLRQFRXQWHU6WRS &OHDU RU 8S 'RZQ# ?03#36&# ?#.43UHVFDOHU&17 &2817(5&& ,&& ,8/24) ,QSXW )LOWHU (GJH GHWHFWRU,& 3UHVFDOHU4) ,QSXW )LOWHU (GJH GHWHFWRU7, )3 7, )3 ,& 36 8&DSWXUH &RPSDUH 5HJLVWHU'7* @ UHJLVWHUV4)-X?#( 2& 5()'7*,& 3UHVFDOHU&& ,,& 36 8&DSWXUH &RPSDUH 5HJLVWHU2& 5()4)-X?#( '7*,QSXW )LOWHU (GJH GHWHFWRU7, )3 7, )3 7, ,QSXW )LOWHU (GJH GHWHFWRU7, )3 7, )3 4)-X?#( ./# .,& 3UHVFDOHU,& 364)-X?#( && ,8&DSWXUH &RPSDUH 5HJLVWHU2& 5()'7*RXWSXW /# 4)-X?#( .FRQWURO/# .75&4)-X?#( RXWSXW /# FRQWURO&& ,4) 4)-X?#( ./# .&& ,75&4)-X?#( RXWSXW /# FRQWURO75&4)-X?#( 4)-X?#( 7, )3 7, )3 8&& ,,& 3UHVFDOHU,& 36&& ,4)-X?#( 8&DSWXUH &RPSDUH 5HJLVWHU2& 5()RXWSXWFRQWURO /# 75&(75)4)-X?" ).%5.3RODULW\ 6HOHFWLRQ%,&ORFN IDLOXUH HYHQW IURP FORFN FRQWUROOHU&66 &ORFN 6HFXULW\ V\VWHP1RWHV 5HJ3UHORDG UHJLVWHUV WUDQVIHUUHGWR DFWLYH UHJLVWHUV RQ 8 HYHQW DFFRUGLQJ WR FRQWURO ELWHYHQWLQWHUUXSW '0 RXWSXW06 9 DocID025350 Rev 4243/841310

Advanced-control timer (TIM1)RM036812.3TIM1 functional description12.3.1Time-base unitThe main block of the programmable advanced-control timer is a 16-bit counter with itsrelated auto-reload register. The counter can count up, down or both up and down. Thecounter clock can be divided by a prescaler.The counter, the auto-reload register and the prescaler register can be written or read bysoftware. This is true even when the counter is running.The time-base unit includes: Counter register (TIMx CNT) Prescaler register (TIMx PSC) Auto-reload register (TIMx ARR) Repetition counter register (TIMx RCR)The auto-reload register is preloaded. Writing to or reading from the auto-reload registeraccesses the preload register. The content of the preload register are transferred into theshadow register permanently or at each update event (UEV), depending on the auto-reloadpreload enable bit (ARPE) in TIMx CR1 register. The update event is sent when the counterreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in theTIMx CR1 register. It can also be generated by software. The generation of the updateevent is described in detailed for each configuration.The counter is clocked by the prescaler output CK CNT, which is enabled only when thecounter enable bit (CEN) in TIMx CR1 register is set (refer also to the slave mode controllerdescription to get more details on counter enabling).Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx CR1register.Prescaler descriptionThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. Itis based on a 16-bit counter controlled through a 16-bit register (in the TIMx PSC register).It can be changed on the fly as this control register is buffered. The new prescaler ratio istaken into account at the next update event.Figure 40 and Figure 41 give some examples of the counter behavior when the prescalerratio is changed on the fly:244/841DocID025350 Rev 4

RM0368Advanced-control timer (TIM1)Figure 40. Counter timing diagram with prescaler division change from 1 to 2CK PSCCENTimer clock CK CNTCounter registerF7F8 F9 FA FB FC00010203Update event (UEV)Prescaler control register01Write a new value in TIMx PSCPrescaler buffer0Prescaler counter0101010101Figure 41. Counter timing diagram with prescaler division change from 1 to 4CK PSCCENTimer clock CK CNTCounter registerF7F8 F9 FA FB FC0001Update event (UEV)Prescaler control register03Write a new value in TIMx PSC12.3.2Prescaler buffer0Prescaler counter0301230123Counter modesUpcounting modeIn upcounting mode, the counter counts from 0 to the auto-reload value (content of theTIMx ARR register), then restarts from 0 and generates a counter overflow event.If the repetition counter is used, the update event (UEV) is generated after upcounting isrepeated for the number of times programmed in the repetition counter register(TIMx RCR). Else the update event is generated at each counter overflow.Setting the UG bit in the TIMx EGR register (by software or by using the slave modecontroller) also generates an update event.The UEV event can be disabled by software by setting the UDIS bit in the TIMx CR1register. This is to avoid updating the shadow registers while writing new values in theDocID025350 Rev 4245/841310

Advanced-control timer (TIM1)RM0368preload registers. Then no update event occurs until the UDIS bit has been written to 0.However, the counter restarts from 0, as well as the counter of the prescaler (but theprescale rate does not change). In addition, if the URS bit (update request selection) inTIMx CR1 register is set, setting the UG bit generates an update event UEV but withoutsetting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generatingboth update and capture interrupts when clearing the counter on the capture event.When an update event occurs, all the registers are updated and the update flag (UIF bit inTIMx SR register) is set (depending on the URS bit): The repetition counter is reloaded with the content of TIMx RCR register, The auto-reload shadow register is updated with the preload value (TIMx ARR), The buffer of the prescaler is reloaded with the preload value (content of the TIMx PSCregister).The following figures show some examples of the counter behavior for different clockfrequencies when TIMx ARR 0x36.Figure 42. Counter timing diagram, internal clock divided by 1CK PSCCNT ENTimer clock CK CNTCounter register3132 33 34 35 36 00 01 02 03 04 05 06 07Counter overflowUpdate event (UEV)Update interrupt flag (UIF)Figure 43. Counter timing diagram, internal clock divided by 2CK PSCCNT ENTimer clock CK CNTCounter register0034Counter overflowUpdate event (UEV)Update interrupt flag (UIF)246/841DocID025350 Rev 40035 00360000000100020003

RM0368Advanced-control timer (TIM1)Figure 44. Counter timing diagram, internal clock divided by 4CK PSCCNT ENTimer clock CK CNTCounter register0035000000360001Counter overflowUpdate event (UEV)Update interrupt flag (UIF)Figure 45. Counter timing diagram, internal clock divided by NCK PSCTimer clock CK CNTCounter register1F0020Counter overflowUpdate event (UEV)Update interrupt flag (UIF)Figure 46. Counter timing diagram, update event when ARPE 0 (TIMx ARR notpreloaded)CK PSCCENTimer clock CK CNTCounter register3132 33 34 35 36 00 01 02 03 04 05 06 07Counter overflowUpdate event (UEV)Update interrupt flag (UIF)Auto-reload registerFF36Write a new value in TIMx ARRDocID025350 Rev 4247/841310

Advanced-control timer (TIM1)RM0368Figure 47. Counter timing diagram, update event when ARPE 1(TIMx ARR preloaded)CK PSCCENTimer clock CK CNTCounter registerF0F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07Counter overflowUpdate event (UEV)Update interrupt flag (UIF)Auto-reload preload registerF536Auto-reload shadow registerF536Write a new value in TIMx ARRDowncounting modeIn downcounting mode, the counter counts from the auto-reload value (content of theTIMx ARR register) down to 0, then restarts from the auto-reload value and generates acounter underflow event.If the repetition counter is used, the update event (UEV) is generated after downcounting isrepeated for the number of times programmed in the repetition counter register plus one(TIMx RCR 1). Else the update event is generated at each counter underflow.Setting the UG bit in the TIMx EGR register (by software or by using the slave modecontroller) also generates an update event.The UEV update event can be disabled by software by setting the UDIS bit in TIMx CR1register. This is to avoid updating the shadow registers while writing new values in thepreload registers. Then no update event occurs until UDIS bit has been written to 0.However, the counter restarts from the current auto-reload value, whereas the counter of theprescaler restarts from 0 (but the prescale rate doesn’t change).In addition, if the URS bit (update request selection) in TIMx CR1 register is set, setting theUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt orDMA request is sent). This is to avoid generating both update and capture interrupts whenclearing the counter on the capture event.When an update event occurs, all the registers are updated and the update flag (UIF bit inTIMx SR register) is set (depending on the URS bit):248/841 The repetition counter is reloaded with the content of TIMx RCR register The buffer of the prescaler is reloaded with the preload value (content of the TIMx PSCregister) The auto-reload active register is updated with the preload value (content of theTIMx ARR register). Note that the auto-reload is updated before the counter isreloaded, so that the next period is the expected oneDocID025350 Rev 4

RM0368Advanced-control timer (TIM1)The following figures show some examples of the counter behavior for different clockfrequencies when TIMx ARR 0x36.Figure 48. Counter timing diagram, internal clock divided by 1CK PSCCNT ENTimer clock CK CNTCounter register04 03 02 01 00 36 35 34 33 32 31 30 2F05Counter underflow (cnt udf)Update event (UEV)Update interrupt flag (UIF)Figure 49. Counter timing diagram, internal clock divided by 2CK PSCCNT ENTimer clock CK CNTCounter register00020001 00000036003500340033Counter underflowUpdate event (UEV)Update interrupt flag (UIF)Figure 50. Counter timing diagram, internal clock divided by 4CK PSCCNT ENTimer clock CK CNTCounter register0001000000360035Counter underflowUpdate event (UEV)Update interrupt flag (UIF)DocID025350 Rev 4249/841310

Advanced-control timer (TIM1)RM0368Figure 51. Counter timing diagram, internal clock divided by NCK PSCTimer clock CK CNTCounter register201F0036Counter underflowUpdate event (UEV)Update interrupt flag (UIF)Figure 52. Counter timing diagram, update event when repetition counteris not usedCK PSCCENTimer clock CK CNTCounter register0504 03 02 01 00 36 35 34 33 32 31 30 2FCounter underflowUpdate event (UEV)Update interrupt flag (UIF)Auto-reload registerFF36Write a new value in TIMx ARRCenter-aligned mode (up/down counting)In center-aligned mode, the counter counts from 0 to the auto-reload value (content of theTIMx ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts countingfrom 0.Center-aligned mode is active when the CMS bits in TIMx CR1 register are not equal to'00'. The Output compare interrupt flag of channels configured in output is set when: thecounter counts down (Center aligned mode 1, CMS "01"), the counter counts up (Centeraligned mode 2, CMS "10") the counter counts up and down (Center aligned mode 3,CMS "11").In this mode, the DIR direction bit in the TIMx CR1 register cannot be written. It is updatedby hardware and gives the current direction of the counter.The update event can be generated at each counter overflow and at each counter underflowor by setting the UG bit in the TIMx EGR register (by software or by using the slave modecontroller) also generates an update event. In this case, the counter restarts counting from0, as well as the counter of the prescaler.250/841DocID025350 Rev 4

RM0368Advanced-control timer (TIM1)The UEV update event can be disabled by software by setting the UDIS bit in the TIMx CR1register. This is to avoid updating the shadow registers while writing new values in thepreload registers. Then no update event occurs until UDIS bit has been written to 0.However, the counter continues counting up and down, based on the current auto-reloadvalue.In addition, if the URS bit (update request selection) in TIMx CR1 register is set, setting theUG bit generates an UEV update event but without setting the UIF flag (thus no interrupt orDMA request is sent). This is to avoid generating both update and capture interrupts whenclearing the counter on the capture event.When an update event occurs, all the registers are updated and the update flag (UIF bit inTIMx SR register) is set (depending on the URS bit): The repetition counter is reloaded with the content of TIMx RCR register The buffer of the prescaler is reloaded with the preload value (content of the TIMx PSCregister) The auto-reload active register is updated with the preload value (content of theTIMx ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expectedone (the counter is loaded with the new value).The following figures show some examples of the counter behavior for different clockfrequencies.Figure 53. Counter timing diagram, internal clock divided by 1, TIMx ARR 0x6CK PSCCNT ENTimer clock CK CNTCounter register0403 02 01 00 01 02 03 04 05 06 05 04 03Counter underflowCounter overflowUpdate event (UEV)Update interrupt flag (UIF)1. Here, center-aligned mode 1 is used (for more details refer to Section 12.4: TIM1 registers on page 283).DocID025350 Rev 4251/841310

Advanced-control timer (TIM1)RM0368Figure 54. Counter timing diagram, internal clock divided by 2CK PSCCNT ENTimer clock CK CNTCounter register00030002 00010000000100020003Counter underflowUpdate event (UEV)Update interrupt flag (UIF)Figure 55. Counter timing diagram, internal clock divided by 4, TIMx ARR 0x36CK PSCCNT ENTimer clock CK CNTCounter register0034003500360035Counter overflowUpdate event (UEV)Update interrupt flag (UIF)1. Center-aligned mode 2 or 3 is used with an UIF on overflow.Figure 56. Counter timing diagram, internal clock divided by NCK PSCTimer clock CK CNTCounter register20Counter underflowUpdate event (UEV)Update interrupt flag (UIF)252/841DocID025350 Rev 41F0100

RM0368Advanced-control timer (TIM1)Figure 57. Counter timing diagram, update event with ARPE 1 (counter underflow)CK PSCCENTimer clock CK CNTCounter register0605 04 03 02 01 00 01 02 03 04 05 06 07Counter underflowUpdate event (UEV)Update interrupt flag (UIF)Auto-reload preload registerFD36Write a new value in TIMx ARRAuto-reload active registerFD36Figure 58. Counter timing diagram, Update event with ARPE 1 (counter overflow)CK PSCCENTimer clock CK CNTCounter registerF7F8 F9 FA FB FC 36 35 34 33 32 31 30 2FCounter overflowUpdate event (UEV)Update interrupt flag (UIF)Auto-reload preload registerFD36Write a new value in TIMx ARRAuto-reload active register12.3.3FD36Repetition counterSection 12.3.1: Time-base unit describes how the update event (UEV) is generated withrespect to the counter overflows/underflows. It is actually generated only when the repetitioncounter has reached zero. This can be useful when generating PWM signals.This means that data are transferred from the preload registers to the shadow registers(TIMx ARR auto-reload register, TIMx PSC prescaler register, but also TIMx CCRxcapture/compare registers in compare mode) every N 1 counter overflows or underflows,where N is the value in the TIMx RCR repetition counter register.DocID025350 Rev 4253/841310

Advanced-control timer (TIM1)RM0368The repetition counter is decremented: At each counter overflow in upcounting mode, At each counter underflow in downcounting mode, At each counter overflow and at each counter underflow in center-aligned mode.Although this limits the maximum number of repetition to 128 PWM cycles, it makes itpossible to update the duty cycle twice per PWM period. When refreshing compareregisters only once per PWM period in center-aligned mode, maximum resolution is2xTck, due to the symmetry of the pattern.The repetition counter is an auto-reload type; the repetition rate is maintained as defined bythe TIMx RCR register value (refer to Figure 59). When the update event is generated bysoftware (by setting the UG bit in TIMx EGR register) or by hardware through the slavemode controller, it occurs immediately whatever the value of the repetition counter is and therepetition counter is reloaded with the content of the TIMx RCR register.In center-aligned mode, for odd values of RCR, the update event occurs either on theoverflow or on the underflow depending on when the RCR register was written and whenthe counter was started. If the RCR was written before starting the counter, the UEV occurson the overflow. If the RCR was written after starting the counter, the UEV occurs on theunderflow. For example for RCR 3, the UEV is generated on each 4th overflow orunderflow event depending on when RCR was written.Figure 59. Update rate examples depending on mode and TIMx RCR register settingsCenter-aligned modeEdge-aligned modeUpcountingDowncountingCounterTIMx CNTTIMx RCR 0 UEVTIMx RCR 1 UEVTIMx RCR 2 UEVTIMx RCR 3 UEVTIMx RCR 3andre-synchronizationUEV(by SW)UEV254/841(by SW)(by SW)Update Event: Preload registers transferred to active registers and update interrupt generatedDocID025350 Rev 4

RM036812.3.4Advanced-control timer (TIM1)Clock selectionThe counter clock can be provided by the following clock sources: Internal clock (CK INT) External clock mode1: external input pin External clock mode2: external trigger input ETR Internal trigger inputs (ITRx): using one timer as prescaler for another timer, forexample, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Usingone timer as prescaler for another timer for more details.Internal clock source (CK INT)If the slave mode controller is disabled (SMS 000), then the CEN, DIR (in the TIMx CR1register) and UG bits (in the TIMx EGR register) are actual control bits and can be changedonly by software (except UG which remains cleared automatically). As soon as the CEN bitis written to 1, the prescaler is clocked by the internal clock CK INT.Figure 60 shows the behavior of the control circuit and the upcounter in normal mode,without prescaler.Figure 60. Control circuit in normal mode, internal clock divided by 1Internal clockCEN CNT ENUGCNT INITCounter clock CK CNT CK PSCCounter register3132 33 34 35 36 00 01 02 03 04 05 06 07External clock source mode 1This mode is selected when SMS 111 in the TIMx SMCR register. The counter can count ateach rising or falling edge on a selected input.Figure 61. TI2 external clock connection exampleTIMx SMCRTS[2:0]orITRxTI2TI2F RisingFilterICF[3:0]TIMx CCMR1EdgeDetector TI2F Falling010xxTI2FTI1FororencodermodeTI1 ED 100TI1FP1 101TRGIexternal clockmode 1CK PSCTI2FP2 110ETRF111ETRFexternal clockmode 2CC2PTIMx CCERCK INTinternal clockmode(internal clock)ECE SMS[2:0]TIMx SMCRDocID025350 Rev 4255/841310

Advanced-control timer (TIM1)RM0368For example, to configure the upcounter to count in response to a rising edge on the TI2input, use the following procedure:Note:1.Configure channel 2 to detect rising edges on the TI2 input by writing CC2S ‘01’ inthe TIMx CCMR1 register.2.Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx CCMR1register (if no filter is needed, keep IC2F 0000).3.Select rising edge polarity by writing CC2P 0 and CC2NP 0 in the TIMx CCERregister.4.Configure the timer in external clock mode 1 by writing SMS 111 in the TIMx SMCRregister.5.Select TI2 as the trigger input source by writing TS 110 in the TIMx SMCR register.6.Enable the counter by writing CEN 1 in the TIMx CR1 register.The capture prescaler is not used for triggering, so you don’t need to configure it.When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.The delay between the rising edge on TI2 and the actual clock of the counter is due to theresynchronization circuit on TI2 input.Figure 62. Control circuit in external clock mode 1TI2CNT ENCounter clock CK CNT CK PSCCounter register343536TIFWrite TIF 0External clock source mode 2This mode is selected by writing ECE 1 in the TIMx SMCR register.The counter can count at each rising or falling edge on the external trigger input ETR.Figure 63 gives an overview of the external trigger input block.256/841DocID025350 Rev 4

RM0368Advanced-control timer (TIM1)Figure 63. External trigger input blockorETR pinETR01ETPTIMx SMCRdivider/1, /2, /4, /8ETRPfilterdowncounterfDTSETPS[1:0]ETF[3:0]TIMx SMCRTI2FTI1FororencodermodeTRGIexternal clockmode 1CK PSCETRFexternal clockmode 2CK INTinternal clockmode(internal clock)TIMx SMCRECE SMS[2:0]TIMx SMCRFor example, to configure the upcounter to count each 2 rising edges on ETR, use thefollowing procedure:1.As no filter is needed in this example, write ETF[3:0] 0000 in the TIMx SMCR register.2.Set the prescaler by writing ETPS[1:0] 01 in the TIMx SMCR register3.Select rising edge detection on the ETR pin by writing ETP 0 in the TIMx SMCRregister4.Enable external clock mode 2 by writing ECE 1 in the TIMx SMCR register.5.Enable the counter by writing CEN 1 in the TIMx CR1 register.The counter counts once each 2 ETR rising edges.The delay between the rising edge on ETR and the actual clock of the counter is due to theresynchronization circuit on the ETRP signal.Figure 64. Control circuit in external clock mode 2fCK INTCNT ENETRETRPETRFCounter clock CK CNT CK PSCCounter register12.3.5343536Capture/compare channelsEach Capture/Compare channel is built around a capture/compare register (including ashadow register), a input stage for capture (with digital filter, multiplexing and prescaler) andan output stage (with comparator and output control).Figure 65 to Figure 68 give an overview of one Capture/Compare channel.The input stage samples the corresponding TIx input to generate a filtered signal TIxF.Then, an edge detector with polarity selection generates a signal (TIxFPx) which can beDocID025350 Rev 4257/841310

Advanced-control timer (TIM1)RM0368used as trigger input by the slave mode controller or as the capture command. It isprescaled before the capture register (ICxPS).Figure 65. Capture/compare channel (example: channel 1 input stage)TI1F EDto the slave mode controllerTI1fDTSfilterdowncounterTI1FTI1F RisingEdgeDetectorTI1F FallingICF[3:0]CC1P/CC1NPTIMx CCMR1TIMx CCERTI2F rising(from channel 2)TI2F falling(from channel 2)0TI1FP1101TI2FP110IC1divider/1, /2, /4, /8IC1PSTRC11(from slave modecontroller)0CC1S[1:0] ICPS[1:0]1TIMx CCMR1CC1ETIMx CCERThe output stage generates an intermediate waveform which is then used for reference:OCxRef (active high). The polarity acts at the end of the chain.Figure 66. Capture/compare channel 1 main circuitAPB Busread CCR1Lread in progressCC1S[0]IC1PSCapture/compare preload registerinputmodeoutputmodecomparatorCNT CCR1CounterCC1GTIM1 EGRDocID025350 Rev 4write CCR1LCC1S[1]CC1S[0]OC1PECapture/compare shadow registercaptureS write CCR1HRcompare transferCC1E258/841write in progressRcapture transferCC1S[1]8lowread CCR1H Shigh8(if 16-bit)MCU-peripheral interfaceCNT CCR1OC1PEUEVTIM1 CCMR1(from timebase unit)

RM0368Advanced-control timer (TIM1)Figure 67. Output stage of capture/compare channel (channel 1 to 3)ETRTo the master modecontroller‘0’OC1 DTCNT CCR1Output mode OC1REFCNT enablecircuitOC1OutputenablecircuitOC1NTIM1 CCEROC1N DT11010‘0’0x1CC1NE CC1E TIM1 CCEROC1CE OC1M[2:0]TIM1 CCMR1DTG[7:0]CC1NE CC1ETIM1 BDTRTIM1 CCERCC1NP MOE OSSI OSSR TIM1 BDTRTIM1 CCERFigure 68. Output stage of capture/compare channel (channel 4)ETRTo the master modecontroller01OutputenablecircuitOC4CC4PCNT CCR4Output mode OC4 REFCNT CCR4 controllerTIM1 CCERCC4E TIM1 CCEROC2M[2:0]MOE OSSI TIM1 BDTRTIM1 CCMR2OIS4 TIM1 CR2The capture/compare block is made of one preload register and one shadow register. Writeand read always access the preload register.In capture mode, captures are actually done in the shadow register, which is copied into thepreload register.In compare mode, the content of the preload register is copied into the shadow registerwhich is compared to the counter.12.3.6Input capture modeIn Input capture mode, the Capture/Compare Registers (TIMx CCRx) are used to latch thevalue of the counter after a transition detected by the corresponding ICx signal. When acapture occurs, the corresponding CCXIF flag (TIMx SR register) is set and an interrupt ora DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag wasalready high, then the over-capture flag CCxOF (TIMx SR register) is set. CCxIF can becleared by software by writing it to ‘0’ or by reading the captured data stored in theTIMx CCRx register. CCxOF is cleared when you write it to ‘0’.DocID025350 Rev 4259/841310

Advanced-control timer (TIM1)RM0368The following example shows how to capture the counter value in TIMx CCR1 when TI1input rises. To do this, use the following procedure: Select the active input: TIMx CCR1 must be linked to the TI1 input, so write the CC1Sbits to 01 in the TIMx CCMR1 register. As soon as CC1S becomes different from 00,the channel is configured in input and the TIMx CCR1 register becomes read-only. Program the input filter duration you need with respect to the signal you connect to thetimer (by programming ICxF bits in the TIMx CCMRx register if the input is a TIx input).Let’s imagine that, when toggling, the input signal is not stable during at must 5 internalclock cycles. We must program a filter duration longer than these 5 clock cycles. Wecan validate a transition on TI1 when 8 consecutive samples with the new level havebeen detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in theTIMx CCMR1 register. Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NPbits to 0 in the TIMx CCER register (rising edge in this case). Program the input prescaler. In our example, we wish the capture to be performed ateach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in theTIMx CCMR1 register). Enable capture from the counter into the capture register by setting the CC1E bit in theTIMx CCER register. If needed, enable the related interrupt request by setting the CC1IE bit in theTIMx DIER register, and/or the DMA request by setting the CC1DE bit in theTIMx DIER register.When an input capture occurs: The TIMx CCR1 register gets the value of the counter on the active transition. CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive capturesoccurred whereas the flag was not cleared. An interrupt is generated depending on the CC1IE bit. A DMA request is generated depending on the CC1DE bit.In order to handle the overcapture, it is recommended to read the data before theovercapture flag. This is to avoid missing an overcapture which could happen after readingthe flag and before reading the data.Note:260/841IC interrupt and/or DMA requests can be generated by software by setting thecorresponding CCxG bit in the TIMx EGR register.DocID025350 Rev 4

RM036812.3.7Advanced-control timer (TIM1)PWM input modeThis mode is a particular case of input capture mode. The procedure is the same except: Two ICx signals are mapped on the same TIx input. These 2 ICx signals are active on edges with opposite polarity. One of the two TIxFP signals is selected as trigger input and the slave mode controlleris configured in reset mode.For example, you can measure the period (in TIMx CCR1 register) and the duty cycle (inTIMx CCR2 register) of the PWM applied on TI1 using the following procedure (dependingon CK INT frequency and prescaler value): Select the active input for TIMx CCR1: write the CC1S bits to 01 in the TIMx CCMR1register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx CCR1 and counterclear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). Select the active input for TIMx CCR2: write the CC2S bits to 10 in the TIMx

setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):

Related Documents:

Da Vinci-History Design Jot Design Museum Collection of iPad DrawCast Drawing Lessons IBM Think . Best Kitchen Timer Best Sand Timer Egg Timer Giant Timer Hourglass Sand Timer Just Timer Wave Timer . Pixlr Express Retromatic HD Split Pic Photo Edito

that is visualized. If the Timer in use is programmed on an infinite cycle, the booked Timer will begin at the end of the first pause of the working Timer. To make a booking, press the key of the Timer-x to be booked and then the Timer-Booking key. Start and Stop of a Blind Timer It is possible to activate any one of the five

to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs. 32-bit millisecond timer driven from th e RTC clock. This timer can generate interrupts using two match registers. WatchDog timer clocked by the peripheral clock.

Timer B 0 SIP Timer B (INVITE Transaction timeout timer) 500 : 65535 Timer F 0 SIP Timer F (non-INVITE Transaction timerout timer) 500 : 65535 Use_User_Agent 0 Add User-Agent Header in SIP Message or not 0 : not use, 1 : use User_Agent_Name "WPU-7800" String in User-Agent Header 1 60 string Use_Version_On_User_Agent 0 Add version in User-Agent .

Timer Operation During Programming The timer enters the Program Mode in Standby or Service Mode the timer continues to operate normally monitoring water usage. Timer programming is stored in memory permanently. Timer Operation During A Power Failure All

The timer module is a 555 timer IC operating in the monostable mode and uses the -15V trigger from the touchless switch to start its cycle aka timer. In the monostable mode the 555 timer generates a one time pulse that has the pulse width equal to 1.1*R*C where R is the resistor used in the charge path of the capacitor. During this

8051 Timer Programming in Assembly and C Microcontroller Page2 Timers of 8051 do starting and stopping by either software or hardware control. In using software to start and stop the timer where GATE 0. The start and stop of the timer are controlled by way of software by the TR (timer start) bits TR0 and TR1. The SETB

us88685734 agma 1003-g 1993 us88685738 agma 2008-b 1990 us88685800 agma 6004-f 1988 us88685801 agma 6017-e 1986 us88685804 agma 6033-b 1998 us88685818 agma 9001-a 1986 de88686927 tgl 18790/03 1972-09 us88687103 a-a-20079 1984-04-16 us88687140 a-a-1953 1982-08-31 us88687157 a-a-1669 1982-10-18 us88687212 a-a-55063 1992-08-13 us88687305 a-a-59606 2002-08-23 us88687309 a-a-59606/2 2002-08-23 .