CAL2: Computer Aided Learning In Computer Architecture Laboratory

4DJORDJEVIC ET AL.Table 1 Assessment of the Existing Educational Computer Systems for Their Pedagogical wLowLowLowLowLowLowLowLowLowoften are not suitable for introductory courses due totheir complexity.In this paper we describe an educational computer system (ECS), graphical software simulator forit (SimECS), and a Web-based system for learning andknowledge assessment (CALKAS). The educationalcomputer system is designed to closely followcommon topics in introductory computer architecturecourses and includes a whole computer system—processor, memory, I/O subsystem, and bus arbitrator.For each component, a detailed register transfer level(RTL) description is provided. Figure 3 illustrates thecomputer system hierarchy, starting from the systemcomponents, via the register transfer level description,down to the gate-level description.A Chinese proverb says ‘‘I hear, I forget; I see, Iremember; I do, I understand.’’ In this spirit, theSimECS simulator supports animation of instructionexecution and allows students to write their ownassembly programs, translate them, interactivelyFigure 3 Computer system hierarchy. [Color figure can beviewed in the online issue, which is available at www.interscience.wiley.com.]initialize processor’s registers, run the simulation,and examine timing diagrams of selected signals,values of registers, and memory locations. Thesimulator gives graphical presentation of all parts ofthe computer system, both at the level of computersystem modules (Fig. 3, left top) and at the registertransfer level (Fig. 3, top right). A simulation runcan be done at the level of a clock, an instruction, or acomplete program.The web-based system for learning and knowledge assessment—CALKAS [13] is developed due tothe following reasons. A large number of studentstaking the laboratory exercises imposed the need for asoftware package, which would automate the assessment of students’ knowledge and keep evidence abouteach laboratory exercise for each student. In additionto that, this software package had to offer the possibility of self-learning of various topics in computerarchitecture and organization as a help in the processof preparation for the laboratory exercises and theexam itself. Finally, the software package had to beopen for its integration with the visual simulator andthe student database maintained for the whole college.The practical work with the educational systemtakes place in the laboratory where the students carryout a set of laboratory exercises. The students preparefor each laboratory exercise at home by studying thedesign of a particular part of the computer systemfrom the reference manual and online materials(Fig. 4); using a self-testing feature of the CALKASsystem, they can test their knowledge before takinga laboratory exercise. A typical laboratory sessionstarts with a laboratory test; this test is designedto determine whether students are prepared forthe laboratory or not. In each laboratory exercisethe students are asked to solve practical problemsby following the functioning of the computersystem using the simulator and the accompanyingtools. Concurrently using CALKAS they answer the

COMPUTER AIDED LEARNING5Figure 4 Active learning in computer architecture laboratory. [Color figure can be viewed in theonline issue, which is available at www.interscience.wiley.com.]questions related to their problem or submit theirsolutions.ECS: EDUCATIONAL COMPUTER SYSTEMThe educational computer system is similar to theEDCOM described in Ref. [12], and encompassesthe following components: a processor (CPU), amemory (MEM), an input/output subsystem (I/O) andan asynchronous bus with an arbiter (ARB). Theprocessor features a CISC-like instruction set; a richset of programmable registers including data registers,base, index, and address registers; and special purposeregisters, such as the program counter, the stackpointer, the program status word, the accumulator, andthe interrupt mask register. The data types supportedare 8-bit signed and unsigned integers. The instructionformat is the one-address one with the instructionlength of 1, 2, 3, and 4 bytes. The addressing modesare the register direct, register indirect, memorydirect, memory indirect, base, index, base index,relative, register indirect with auto increment and autodecrement and immediate. The instruction typesare the transfer, arithmetic, logic, shift, rotate, andcontrol instructions. The interrupt mechanism is thevectored one with internal and external interrupts. Theprocessor organization features separate units foreach of the instruction execution phases. Thus, theprocessor is made up of the instruction and operandfetch unit (IF); two execution units for the integeroperations execution (IE) and the control operationsexecution (IC); and the interrupt servicing unit (IS).These units use the memory interface unit (MI) for thebus arbitration and the read, write and interrupt vectornumber acquisition cycles. Each of the units is madeup of the processing and control units. The controlunits are realized by using the hardwired technique.The memory capacity is 64 Kb. The input/outputsubsystem contains 4 input/output units, eachconsisting of a peripheral device and a controller. Aperipheral device is simulated as an array of 16bytes that can be read from or written to with thedefinable access time. The controllers are one nondirect memory access (non-DMA), one direct memoryaccess (DMA) and two dummy (IO1 and IO2) ones.The non-DMA controller is a slave interface for theprocessor controlled device/memory and memory/device data transfers. The DMA controller is a masterinterface, which takes part in the bus arbitration andorganizes the device/memory, memory/device andmemory/memory single-byte or burst data transfers.The dummy controllers take part only in the busarbitration and keep the bus busy for a definableperiod of time, but do not perform any data transfer.The registers of the input/output subsystem arememory mapped. The asynchronous bus interconnects the computer system modules with the addresslines (ABUS), the data lines (DBUS) and the controllines (RDBUS, WRBUS, and FCBUS). A mastermodule initiates a read cycle or a write cycle withthe active signal on the RDBUS line or the WRBUSline, respectively. The processor can, also, initiate aninterrupt vector number acquisition cycle from eitherthe non-DMA controller or the DMA controller withan active signal on either the inta1 line or the inta2line, respectively. The slave module indicates thecompletion of a bus cycle with an active signalon the FCBUS line. A bus cycle is preceded bythe arbitration between the bus masters, which areconnected with the bus arbiter (ARB) with pairs of thebus request (brq) and the bus grant (grant) lines.

6DJORDJEVIC ET AL.SimECS VISUAL SIMULATORThe visual simulator features tools for simulatorinitialization and simulation run. The introductorySimECS screen allows initialization, resumption ofan earlier stopped simulation, or a new simulationstart (Fig. 5a). The initialization allows the user todefine the clock rates for the system modules andthe access times of the peripheral devices and thememory, examine and set the values of memorylocations and registers of the processor and input/output units, and select signals for which the timingdiagrams will be drawn. In order to allow instructorsflexibility in preparing examples, the initializationstep can be carried out in several ways: as a completeinitialization from a predefined file—for example,by selecting one of seven exercises (Fig. 5b), as apartial initialization from a file—separately for eachcomponent of the ECS (Fig. 5c), or as an interactiveinitialisation—by direct change of values of registersand memory locations (Fig. 6a). There is also apossibility to write a program in the assemblylanguage, translate it and load into the memory. Oncethe values of either the registers in the processor or inthe input/output units or the memory locations havebeen manually changed, the new simulation statecan be saved in a file and later used for the partialinitialization from files. There are also separatescreens for a manual specification of the clock ratesof the computer system modules and a selection ofsignals for which the timing diagrams should bedrawn (Fig. 6b).The simulator supports the simulation of instruction execution at the level of a clock, an instruction, ora complete program with the visual presentation of allcomponents of the computer system. The simulationscreen consists of four windows (Fig. 7): The clocksignals window (left top part of the screen), the globalpresentation window (left middle), the detailedpresentation window (right top and middle), and theinfo and command window (bottom).The clock signals window shows a few cycles ofthe computer system modules’ clock signals, following the last clock signal that has occurred. The redvertical line points out to the first next clock signalthat will occur in one of the computer systemmodules. On the right hand side of the red line areshown a few clock signals of the computer systemmodules in the order of their occurrence. This allowsone to locate where the next clock signals are goingto occur and examine the values of the appropriatesignals before the clock signals occur and produce thechange of their values.The global presentation window gives either theblock structure of the computer system, if in thedetailed presentation window is shown any othermodule except the processor (Fig. 7), or the blockstructure of the processor, if in the detailed presentation window is shown the processor (Fig. 8). Theblocks are in both cases realized as buttons, offeringthe users possibility to navigate through the modulesof the computer system. The switchover from theblock structure at the level of the computer system’smodules (Fig. 7) to the block structure at the levelof the processors’s units (Fig. 8) can be realized bymouse click on the CPU button. The oppositeswitchover can be realized by clicking button X inthe upper left hand corner.The detailed presentation window gives thedetailed structure of the currently active computersystem’s module: MEM, ARB, DMA, non-DMA,IO1, and IO2 (Fig. 7); or the processors’s units, IF, MI,IE, IC, and IS (Fig. 8). The computer system’smodules and the processor’s units that are not activeare closed and shown as buttons with the names of themodules or the units, respectively. If a user clicks atFigure 5 Simulator start and initialization. (a) Main Window; (b) complete initialization; (c)partial initialization. [Color figure can be viewed in the online issue, which is available atwww.interscience.wiley.com.]

COMPUTER AIDED LEARNINGFigure 6 (a) Interactive examination and change of values of the processor’s registers and savingin a file; (b) specification of the clock rates of the computer system’s modules. [Color figure can beviewed in the online issue, which is available at www.interscience.wiley.com.]Figure 7 A SimECS simulation screen. The global simulation window shows the block structure atthe level of the computer system’s modules. [Color figure can be viewed in the online issue, which isavailable at www.interscience.wiley.com.]7

8DJORDJEVIC ET AL.Figure 8 Block structure at the level of the processor’s units. [Color figure can be viewed in theonline issue, which is available at www.interscience.wiley.com.]one of these buttons, the detailed presentation ofthe corresponding computer system’s module or theprocessor’s unit opens. The detailed presentationof any of the computer system’s module or theprocessor’s unit can be closed and shown as a buttonby clicking button X in the upper right hand corner.This offers another possibility to navigate throughparts of the computer system. In addition to that, thedetailed presentations of the computer system’smodules or the processor’s units are opened andclosed during the simulation in the same order as aninstruction goes through them for various phases of itsexecution. The levels of details are sequential andcombinational modules presented as blocks with inputand output signals. A single signal is presented with athin line in blue, red, or green depending on whetherthe signal on the line is inactive, active, or in the stateof high impedance. Groups of signals are presentedwith thick lines in green, if they are in the state of highimpedance and in gray and hexadecimal valuesotherwise. When the scheme of the computer system’smodule or processor’s unit presented in the detailedpresentation window contains too many elementsthat can not be shown on the screen, the detailedpresentation window has the vertical and horizontalscrollbars that allow users to move around the scheme.The info and command window gives informationabout the state of simulation (on the left hand side)and makes it possible to examine the result of thesimulation and control the simulation (the right handside). The info window contains the sequence windowand the status buttons. The sequence window gives thevalues of the control unit step counter, the controlsignals generated in that step and a brief explanationof the microoperations that are going to be executed inthat step. The status buttons PC, T and Tclk show thecurrent values of the program counter, the controlunit step counter and the number of processor’s clockselapsed, respectively. The command window containsthe simulation, miscellaneous, and start/exit command buttons. The simulation buttons Clkþ, Insþ,and Prgþ facilitate the continuation of the simulationfor one clock or as many clocks as is needed toexecute the current instruction or the completeprogram, respectively. The miscellaneous buttonsare Show, Clear and Help. The Show button opensthe window from where one can further select of oneof the windows that facilitate the interactive examination and change of values of the processor’sregisters, the input/output units’ registers (Fig. 6a)and the memory locations and the drawing of timingdiagrams of selected signals (Fig. 9a). The Clearbutton returns the simulation to the beginning. TheHelp button activates the help system which gives allinformation about the computer system and the visualsimulator (Fig. 9b). The Start/Exit buttons are Startand Exit. The Start button simulates the start of thecomputer system when either the power is turned onor the system reset button pressed. The Exit buttoncompletes the simulation with the possibility to save

COMPUTER AIDED LEARNING9Figure 9 (a) Timing diagram of signals; (b) HELP system. [Color figure can be viewed in theonline issue, which is available at www.interscience.wiley.com.]the current state of the simulation in a file and use thefile later to carry out the complete initialization fromthat file and resume the simulation.The practical work with the visual simulator of thecomputer system is organized through laboratoryexercises. They are made up of simple programscarefully prepared to demonstrate the characteristicsof interest. The students execute the programs andanswer questions related to some typical situations ofthe topic covered by the particular laboratory exercise.In addition to that in some cases the students are givenproblems, which they solve independently, write aprogram using the software tools and test it usingthe simulator. All laboratory exercises cover fourmajor areas in the field of computer architectureand organization: the processor architecture andorganization, the interrupt, the bus and the input/output. Their brief description is given in thefollowing.by the combinational and sequential circuits of theprocessing units. There are two groups of exercisesaimed at demonstrating all addressing modes andalgorithms of operations of all instruction types. Theexercises in the first group include the instructionswith simple algorithms of operations and all addressing modes available. They are the transfer instructions, the arithmetic addition, subtraction, increment,decrement and compare instructions, the logic AND,OR, XOR, and NOT instructions, the shift and rotateinstructions and the unconditional and conditionaljump instructions. The addressing modes included arethe short literal, register direct, register indirect,memory direct and memory indirect, then the base,index, base index and relative with 8- and 16-bitdisplacements and the register indirect with autoincrement and auto decrement and immediate. Theexercises in the second group include the instructionswith complicated algorithms of operations and simpleaddressing modes. They include the multiplicationand division with unsigned and signed integers, thepush on and the pop from the stack, and the jump toand the return from the subroutine.Processor Architecture and OrganizationInterruptThe processor architecture is demonstrated with anumber of exercises that illustrate programmableregisters, data types, instructions formats, addressingmodes, and instruction types. The interrupts do notappear in these exercises, since they are treated in aseparate group of exercises. The instructions areexecuted at the clock level and all processor unitsare involved. This allows one to follow the details ofthe processor organization by going through thesequence of control signals generated by the controlunits and examining the values of all signals generatedThe interrupt is demonstrated with a number ofexercises, where simple programs are executed both atthe clock and the instruction levels. The clock level isused to demonstrate the sequences of control signalsfor the interrupt handling phase of an instruction andthe execution phase of the return from interruptinstruction. Within the interrupt handling phase of anyinstruction, the program counter and the programstatus word registers are saved on the stack and thestarting address of the interrupt routine found andloaded into the program counter. The effect is a jumpLABORATORY EXERCISES

10DJORDJEVIC ET AL.to the interrupt routine. The return from interruptinstruction restores the values of the program statusword register and the program counter with the valuesfrom the stack. The effect is the return to the mainprogram. The instruction level is used to demonstratetopics such as the selective and complete masking ofinterrupt requests coming from the input/output units,the servicing of multiple interrupt requests, thenesting of interrupt requests, the mode of operationwhen a jump to the interrupt routine is being madeafter every instruction executed, the execution of theinterrupt instruction, etc. It is also demonstrated howthe starting address of an interrupt routine can befound by using the approaches with the interruptvector table, the polling of the input/output units andthe combination of both.BusThe exercises in this grou

developed an integrated computer architecture labo-ratory called CAL2 that features a flexible, hierarch-ical, graphical simulator of an educational computer system (SimECS) and a web-based software system for Computer Architecture Learning and Self-Testing (CALKAS). The educational computer system (ECS) is designed to demonstrate a broad .