A Project Report On DESIGN OF HIGH SPEED MULTIPLIER USING REVERSI BLE LOGIC
AProject reportOnDESIGN OF HIGH SPEED MULTIPLIER USINGREVERSIBLE LOGICSubmitted in partial fulfilmentS of the requirement for the award of degree ofBACHELOR OF TECHNOLOGYInELECTRONICS AND COMMUNICATION ENGINEERINGSubmittedByS.SAI Q1A0490Y.AJAY KUMAR13KQ1A04B8Under The Esteemed Guidance OfMrs.D.MANOGNA,M.TechASSISTANT PROFESSORDEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERINGPACE INSTITUTE OF TECHNOLOGY AND SCIENCESACCREDITED WITH NAAC ‘A’ GRADEVALLUR, NH-5, ONGOLE, PRAKASAM DISTRICT, PIN: 523272.(Affiliated to Jawaharlal Nehru Technological University, Kakinada)2013-2017
PACE INSTITUTE OF TECHNOLOGY & SCIENCEACCREDITED WITH NAAC ‘A’ GRADEVALLUR, NH-5, ONGOLE, PRAKASAM DISTRICT, PIN: 523272(Affiliated to Jawaharlal Nehru Technological University, Kakinada)DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERINGBONAFIDE CERTIFICATEThis is certify that the project entitled “DESIGN OF HIGH SPEEDMULTIPLIER USING REVERSIBLE LOGIC” is the bonafide work earing13KQ1A04B8,BachelorofTechnology in “ELECTRONICS AND COMMUNICATION ENGINEERING”Forthe academic year 2016-2017. This work is done under my supervision and guidance.Signature of Internal GuideSignature of Head of the DepartmentMrs.D.MANOGNA M.TechMr. M.APPARAOM. Tech, M.B.A, (Ph.D)ASSISTANT PROFESSOROf Dept Of ECEPROFESSOR AND HOD OF ECESignature of the External Examiner
ACKNOWLEDGEMENTWe thank the almighty for giving us the courage and perseverance in completingthe main project.We would like to place on record the deep sense of gratitude to the honourablechairman Sri Mr.M.VENU GOPALB.E, M.B.A., D.M.M., PACE Institute of Technology &Sciences for providing necessary facilities to carry the concluded main project work.We express my gratitude to Er.M.SRIDHARB.E, Secretary and correspondent ofPACE Institute of technology & sciences for providing me with adequate facilities, waysand means by which I was able to complete this is main project work.We are thankful to our principal Dr.C.V.SUBBARAOM.E, M.Tech, PhD, MISTE forproviding us the necessary infrastructure and labs and also permitting to carry out thisproject.With extreme jubilance and deepest gratitude, we would like to thank to head ofthe E.C.E. Department Mr. M. APPARAOM.Tech, (Ph.D.) for his constant encouragement,valuable suggestions.We are greatly indebted to project guide, Mr. M.APPARAOM.Tech, MBA, (Ph.D)Electronics and Communication engineering, for providing valuableguidance at every stage of this project work. We are profoundly grateful towards theunmatched services rendered by him.Our Special thanks to our project coordinator Mr.B.SIVA PRASADM.TechElectronicsand Communication engineering, for his support and valuable suggestions regardingproject work.Our special thanks to all faculties of Electronics and Communication Engineeringfor their valuable advises at every stage of this work.Last but not least, we would like to express our deep sense of gratitude andearnest thanks giving to our dear parents for their moral support and heartfelt cooperationin doing the main project.In the end we would also like to thank all our peers for all the support and helpthey have provided throughout our project work.
ABSTRACTMultipliers are vital components of any processor or computing machine. Moreoften than not, performance of microcontrollers and Digital signal processors are evaluatedon the basis of number of multiplications performed in unit time. Hence better multiplierarchitectures are bound to increase the efficiency of the system. Vedic multiplier is one suchpromising solution. Its simple architecture coupled with increased speed forms anunparalleled combination for serving any complex multiplication computations. Tagged withthese highlights, implementing this with reversible logic further reduces power dissipationPower dissipation is another important constraint in an embedded system which cannot beneglected.In this paper we bring out a Vedic multiplier known as "Urdhva Tiryakbhayam"meaning vertical and crosswise, implemented using reversible logic, which is the first of itskind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and otherapplications of DSP like imaging, software defined radios, wireless communications.Forarithmetic multiplication, various Vedic multiplication techniques like Urdhva tiryakbhyam,Nikhilam and Anurupye has been thoroughly discussed. It has been found that Urdhvatiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay formultiplication of all types of numbers, either small or large.Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 8x8 bits multiplicationand their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done.i
LIST OF FIGURESFigure 2.1:Multiplication of two decimal numbers by Urdhva TiryakbhyamFigure 2.2:Line diagram for multiplication of two 4 - bit numbers.Figure 2.3:Hardware architecture of the Urdhva tiryakbhyam multiplierFigure 2.4:Multiplication Using Nikhilam SutraFigure 2.5:Reversible Logic GatesFigure 2.6:Reversible Implementation of 2x2 UT MultiplierFigure 2.7:5 bit ripple carry adderFigure 2.8:4 bit Ripple carry adderFigure 2.9:6 bit Ripple carry adder using Reversible gatesFigure 2.10:9 bit Ripple carry adder using Reversible gatesFigure 3.1:Block diagram of 2x2 MultiplieFigure 3.2:RTL View of 2x2 Bits Multiplier by ModelSimFigure 3.3:Block diagram of 4x4 Bit Vedic MultiplierFigure 3.4Algorithm of 4x4 bit UT MultiplierFigure 3.5:RTL View of 4x4 Bit UT Multiplier by ModelSimFigure 3.6:8X8 Bits decomposed Vedic Multiplier.Figure 4.2:FPGA Design FlowFigure 4.3:(a) Design Flow during FPGA Implementation (b) ProcedureFollowed for ImplementationFigure 5.1Figure 5.WaveformVLSI Design FlowSimulation Output View of 4:1 MUX Using ModelSimViewerFigure 5.3Synthesis of 4:1 MUX Using Leonardo SpectrumFigure 5.4Layout view of a systemFigure 5.5Module DesignFigure 5.6Port connection RulesFigure 6.1Xilinx Project Navigator windowFig 6.2New Project Initiation window (snapshot from Xilinx ISEsoftware)Figure 6.3Device and Design Flow of Project (snapshot from Xilinx ISEsoftware)ii
Figure 6.4Create New source window (snapshot from Xilinx ISEsoftware)Figure 6.5Creating Verilog-HDL source file (snapshot from Xilinx ISEsoftware)Figure 6.6Define Verilog Source window (snapshot from Xilinx ISEsoftware)Figure 6.7New Project Information window (snapshot from Xilinx ISEsoftware)Figure 6.8Verilog Source code editor window in the Project Navigator(from Xilinx ISE software)Figure 6.9OR gate description using assign statement (snapshot fromXilinx ISE software)Figure 6.10Implementing the Design (snapshot from Xilinx ISE software)Figure 6.11Top Level Hierarchy of the designFigure 6.12Realized logic by the XilinxISE for the Verilog codeFigure 6.13Simulating the design (snapshot from Xilinx ISE software)Figure 6.14 Behavioral Simulation output Waveform (Snapshot fromModelSim)Figure 7.1:Synthesis reportFigure 7.2:Program CodeFigure 7.3:Top view of systemFigure 7.4:RTL view of systemFigure 7.5:Test bench codeFigure 7.6:Simulated outputFigure 7.7:Time Delay of systemiii
LIST OF TABLESTable 4.1:Summary of FPGA featuresTable 7.1:Time delay comparison tableiv
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CONTENTSPAGE NOLIST OF FIGURESi-iiLIST OF TABLESiiiABSTRACTiv1. INTRODUCTION11.1 OBJECTIVE41.2 THESIS ORGANISATION41.3 TOOLS USED42. VEDIC MULTIPLICATION ALGORITHMS52.1HISTORY OF VEDIC MATHEMATICS52.2 ALGORITHMS OF VEDIC MATHEMATICS72.2.1 VEDIC MULTIPLICATION72.2.2 SQUARE ALGORITHM132.2.3 CUBE ALGORITHM142.3 PERFORMANCE152.3.1 SPEED152.3.2POWER152.3.3AREA162.4 DESIGN SYNOPSIS3. DESIGN AND SOFTWARE SIMULATION16203.1IMPLEMENTATION OF 2X2 BITS VEDIC MULTIPLIER203.2 IMPLEMENTATION OF 4X4 BITS MULTIPLIER213.3 IMPLEMENTATION OF 8X8 BIT MULTIPLIER234. IMPLEMENTATION AND TESTING OF MULTIPLIER254.1FPGA IMPLIMENTATION254.1.1 OVERVIEW OF FPGA254.1.2 DESIGN ENTITY264.1.3 BEHAVIOURAL SIMULATION274.1.4 DESIGN SYNTHASIS274.1.5 DESIGN IMPLEMENTATION274.2 IMPLEMENT DESIGN IN FPGA29
4.3 DOWNLOAD DESIGN TO THE SPARTAN -3E KIT294.4 PROGRAMMING THE FPGA295. VERILOG305.1 HISTORY OF VERILOG305.2 BASIC CONCEPTS305.2.1 HARDWARE DESCRIPTION LANGUGAE305.2.2 VERILOG INTRODUCTION315.3 DESIGN FLOW315.3.1 DESIGN SPECIFICATIONS315.3.2 RTL DESCRIPTION315.3.3 FUNCTIONAL VERIICATION & TESTING335.3.4 LOGIC SYNTHASIS335.3.5 LOGICAL VERIFICATION & TESTING345.3.6 FLOOR PLANNING345.3.7 PHYSICAL LAYOUT345.3.8 LAYOUT VERIFICATION345.3.9 IMPLEMENTATION355.5 MODULES355.6 PORTS365.6.1 PORT DECLERSTION365.6.2 VERILOG KEYWORD TYPE OF PORT375.6.3 PORT CONNECTION RULES376. DIGITAL CIRCUIT DESIGN USING XILINX ISE TOOLS396.1 INTRODUCTION396.1.1 FPGA406.2 SIMULATING AND VIEWING OUTPUT WAVEFORMS517. XILINX SYNTHESIS AND OUTPUT SCREENS7.1 PROPOSED METHOD OUTPUT SCREENS5353CONCLUSION & FUTURE SCOPE58REFERENCES59
CHAPTER 11. INTRODUCTIONThe most important fundamental function in arithmetic operations ismultiplication. Some of the frequently used Computation- Intensive erationssuchasMultiplyandAccumulate(MAC) and inner product. These are presently used in many Digital SignalProcessing (DSP) applications such as Fast Fourier Transform(FFT), convolution,filtering and in microprocessors in its arithmetic and logic unit. There is a need of highspeed multiplier since multiplication dominates the execution time of most DSPalgorithms. At present the instruction cycle time of a DSP chip determination depends onmultiplication time and this time is still a dominant factor.The demand for high speed processing has been increasing as a result ofexpanding computer and signal processing applications. Higher throughput arithmeticoperations are important to achieve the desired performance in many real-time signal andimage processing applications. One of the key arithmetic operations in such applicationsis multiplication and the development of fast multiplier circuit has been a subject ofinterest over decades. Reducing the time delay and power consumption are very essentialrequirements for many applications. This work presents different multiplierarchitectures. Multiplier based on Vedic Mathematics is one of the fast and low powermultiplier.Minimizing power consumption for digital systems involves optimization at alllevels of the design. This optimization includes the technology used to implement thedigital circuits, the circuit style and topology, the architecture for implementing thecircuits and at the highest level the algorithms that are being implemented. Digitalmultipliers are the most commonly used components in any digital circuit design. Theyare fast, reliable and efficient components that are utilized to implement any operation.Depending upon the arrangement of the components, there are different types ofmultipliers available. Particular multiplier architecture is chosen based on theapplication.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE1
In many DSP algorithms, the multiplier lies in the critical delay path andultimately determines the performance of algorithm. The speed of multiplicationoperation is of great importance in DSP as well as in general processor. In the pastmultiplication was implemented generally with a sequence of addition, subtraction andshift operations. There have been many algorithms proposals in literature to performmultiplication, each offering different advantages and having tradeoff in terms of speed,circuit complexity, area and power consumption.The multiplier is a fairly large block of a computing system. The amount ofcircuitry involved is directly proportional to the square of its resolution i.e. A multiplierof size n bits has n2 gates. For multiplication algorithms performed in DSP applicationslatency and throughput are the two major concerns from delay perspective. Latency isthe real delay of computing a function, a measure of how long the inputs to a device arestable is the final result available on outputs. Throughput is the measure of how manymultiplications can be performed in a given period of time; multiplier is not only a highdelay block but also a major source of power dissipate minimizes power consumption, itis of great interest to reduce the delay by using various delay optimizations.Digital multipliers are the core components of all the digital signal processors(DSPs) and the speed of the DSP is largely determined by the speed of its multipliers.Two most common multiplication algorithms followed in the digital hardware are arraymultiplication algorithm and Booth multiplication algorithm. The computation timetaken by the array multiplier is comparatively less because the partial products arecalculated independently in parallel. The delay associated with the array multiplier is thetime taken by the signals to propagate through the gates that form the multiplicationarray. Booth multiplication is another important multiplication algorithm. Large bootharrays are required for high speed multiplication and exponential operations which inturn require large partial sum and partial carry registers. Multiplication of two n-bitoperands using a radix-4 booth recording multiplier requires approximately n / (2m)clock cycles to generate the least significant half of the final product, where m is thenumber of Booth recorder adder stages. Thus, a large propagation delay is associatedwith this case.Due to the importance of digital multipliers in DSP, it has always been an activearea of research and a number of interesting multiplication algorithms have beenPACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE2
reported in the literature. In this thesis work, Urdhva tiryakbhyam Sutra is first applied tothe binary number system and is used to develop digital multiplier architecture. This isshown to be very similar to the popular array multiplier architecture. This Sutra alsoshows the effectiveness of to reduce the NXN multiplier structure into an efficient 4X4multiplier structures. Nikhilam Sutra is then discussed and is shown to be much moreefficient in the multiplication of large numbers as it reduces the multiplication of twolarge numbers to that of two smaller ones. The proposed multiplication algorithm is thenillustrated to show its computational efficiency by taking an example of reducing a 4X4bit multiplication to a single 2X2-bit multiplication operation. This work presents asystematic design methodology for fast and area efficient digit multiplier based on Vedicmathematics .The Multiplier Architecture is based on the Vertical and Crosswisealgorithm of ancient Indian Vedic Mathematics.This work presents methodology to detect and locate faults using Built in SelfTest (BIST) and other various Designs for Testability (DFT) methods. It also introducesAutomatic Test Pattern Generation for maximum fault coverage. The task of determiningwhether the chip is working properly or not is very tedious. However, if chip is notproperly fabricated, they can cause system failure and result in heavy loss in economy.System failure results difficulty in debugging. The debugging cost grows exponentiallyas we move from chip to board level and then toward the system level. As the number oftransistor integrated in the chip increases, task to test the functionality of chip becomemore and more difficult. To overcome these design issues, Design for Testability hasbecome more important.Automatic Test Pattern Generation is a process of generating patterns to test acircuit which is described strictly with a logic level net list. They can generate circuit testvectors to detect faults in the circuit. They can find redundant or unnecessary circuitlogic and they can prove whether one circuit implementation matches the circuitimplementation.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE3
1.1 OBJECTIVEThe main objective of this thesis work is to design and implement a fast vedicUT multiplier using reversible logic gates with self testing, which can be used in theapplication of any processor. The study, design and implementation of Vedic multiplierwith Built In Self Test technique deals in this thesis work. Vedic multiplication usingreversible logic gates, square and cube algorithms has been explored in this thesis work.Here the architecture of Vedic multiplier depending on speed specification is developedhere. Spartan 3E Board is used for the Hardware Implementation of this multiplier. Thetesting of this multiplier is finally done using BIST technique.1.2 THESIS ORGANIZATIONThe functionality of Vedic multiplier using reversible logic gates andfundamental concepts of multiplications, architectures are going to be discussed inchapter2 The design and software implementation of different modules of the Vedicmultiplier using reversible gates are discussed in Chapter 3 & chapter 4. Simulationsoftware ISE (Integrated Software Environment) of Xilinx and ModelSim are used forthe coding of modules.The hardware implementation of Vedic multiplier using reversible logic gates on FPGAusing Xilinx tool is going to be discussed and the design flow of BIST is also explainedin chapter 6.In chapter 7 results obtained from realization of Vedic multiplier usingreversible logic gates on FPGA kit, in terms of speed, area and number of gates areshown. The observation of Built In Self Test results of has done. By observing theresults of proposed work, a conclusion and future scope of the thesis work are discussed.1.3 TOOLS USEDSimulation Software: Modelsim6.1e has been used for simulation. For synthesis andverification ISE14.3i (Integrated system environment) has been used.Hardware used: Xilinx Spartan3E (Family), XC3S100(Device),VQ100(Package), -5(Speed Grade) FPGA devices.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE4
CHAPTER 22. VEDIC MULTIPLICATION ALGORITHMS2.1 HISTORY OF VEDIC MATHEMATICSVedic mathematics is part of four Vedas (books of wisdom). It is part ofSthapatya-Veda (book on civil engineering and architecture), this is an upa-veda(supplement) of Atharvana Veda. It covers explanation of several modern mathematicalterms including quadratic equations, factorization ,arithmetic, geometry (plane, coordinate), trigonometry, and even calculus.His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja(1884-1960) comprised all this work together and gave its mathematical explanationwhile discussing it for various applications.16 sutras (formulae) and 16 Upa sutras (subformulae) was constructed by Swamiji after extensive research in Atharvana Veda. theseformulae were constructed by Swamiji himself obviously these formulae are not to befound in present text of Atharvana Veda since Vedic mathematics which couldn‟t bedisapproved because it is not only a mathematical wonder. Vedic Mathematics hasalready crossed the boundaries of India and has become a leading topic of researchabroad due these phenomenal characteristic. Several basic as well as complexmathematical operations are deal with vedic mathematics. The various branches ofmathematics like geometry, algebra, arithmetic are mainly included in Vedicmathematics based on 16 Sutras (or aphorisms) dealing with etc. These Sutras areenlisted below alphabetically along with their brief meanings1.(Anurupye) Shunyamanyat –If one is in ratio, the other is zero.2.Chalana-Kalanabyham –Differences and Similarities.3.Ekadhikina Purvena –By one more than the previous One.4.Ekanyunena Purvena –By one less than the previous one.5.Gunakasamuchyah –The factors of the sum is equal to the sum of the factors.6.Gunitasamuchyah –The product of the sum is equal to the sum of the product.7.Nikhilam Navatashcaramam Dashatah –All from 9 and last from 10.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE5
8.Paraavartya Yojayet –Transpose and adjust.9.Puranapuranabyham –By the completion or no completion.10.Sankalana- vyavakalanabhyam –By addition and by subtraction.11.Shesanyankena Charamena –The remainders by the last digit.12.Shunyam Saamyasamuccaye –When the sum is the same that sum is zero.13.Sopaantyadvayamantyam –The ultimate and twice the penultimate.14.Urdhva-tiryakbhyam –Vertically and crosswise.15.Vyashtisamanstih –Part and Whole.16.Yaavadunam –Whatever the extent of its deficiency.These methods of architectures and ideas may be applied to applied mathematicsof various kinds and spherical geometry, plain and conics, trigonometry, calculus (bothdifferential and integral) directly. All these Sutras were reconstructed from ancient Vedictexts early in the last century s mentioned earlier. There are so many Sub-sutras werealso discovered at the same time but are not discussed here.The reduction of cumbersome-looking calculations in conventional mathematicsto a very simple one is the beauty of Vedic mathematics lies in that. The naturalprinciples on which the human mind works are the basic building blocks of the Vedicformulae . Various branches of engineering such as computing and digital signalprocessing.The multiplier architecture can be generally classified into three categories. Firstis the serial multiplier which emphasizes on hardware and minimum amount of chiparea. Second is parallel multiplier (array and tree) which carries out high speedmathematical operations. But the drawback is the relatively larger chip areaPACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE6
consumption. Third is serial- parallel multiplier which serves as a good trade-offbetween the times consuming serial multiplier and the area consuming parallelmultipliers.2.2 ALGORITHMS OF VEDIC MATHEMATICS2.2.1 VEDIC MULTIPLICATIONThe proposed Vedic multiplier is based on the Vedic multiplication formulae(Sutras). For the multiplication of two numbers in the decimal number system theproposed Sutras have been traditionally used. To make the proposed algorithmcompatible with the digital hardware in this work, the same ideas are applied to thebinary number system. The algorithms that took part in Vedic multiplication based areexplained in further discussion.2.2.1.1 Urdhva Tiryakbhyam sutraUrdhva Tiryakbhyam Sutra is applicable to all cases of multiplication. This sutraperforms the multiplication using the principle Vertically and crosswise multiplication.The generation of all partial products can be done with the concurrent addition of thesepartial products. The fig 2.1 explains parallelism in generation of partial products andtheir summation. The algorithm can be generalized for n x n bit number. This multiplieris independent of the clock frequency of the processor as the partial products and theirsums are calculated in parallel. The same amount of time will require by this multiplierto calculate the product and thus it is independent of the clock frequency.The need of microprocessors to operate at increasingly high clock frequencies isreduces using which is main advantage. There is an increase in processing power as aresult of high clock frequency. The power dissipation is also increases which is a disadvantage results in higher device operating temperatures. Through the implementationof Vedic multiplier in processor design the problems are easily over come and hence thedevice failure may avoided. The great advantage of this multiplier is gate delay and areaincreases very slowly with the number of bits increases as compared to conventionalmultipliers. Hence it is more efficient than conventional multipliers. This architecture isquite efficient in terms of silicon area/speed.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE7
1) Multiplication of two decimal numbers- 325*738To illustrate this multiplication scheme, the multiplication of two decimalnumbers (325 * 738) is going to explain here. This multiplication process is explained interms of line diagram for as shown below. Multiplication proceeds from right to left, firstdigits are multiplied and to the carry which is obtained from the previous step. Thisresult in the generation of a part of the bits in the result. This process continuous byadding the previous carry to the next step. When one or more lines are in one step thenall the results are added. All the bits act as carry for the next step except, least significantbit which acts as the result bit. For the first time carry bit is zero.Figure 2.1: Showing Multiplication of two decimal numbers by UrdhvaTiryakbhyam2) Algorithm for 4 x 4 bit Vedic multiplier Using Urdhva Tiryakbhyam(Vertically and crosswise) for two Binary numbersCP Cross Product (Vertically and Crosswise)X3X2X1 X0MultiplicandY3Y2Y1 ------P7P6P5P4 P3P2P1 ---------------------------PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE8
PARALLEL COMPUTATION METHODOLOGY1. CP X0 X0 * Y0 AY02. CP X1 X0 X1 * Y0 X0 * Y1 BY1 Y03. CP X2Y24. CP X3Y35. CP X3Y36. CP X3Y37 CP X3X1 X0 X2 * Y0 X0 * Y2 X1 * Y1 CY1 Y0X2 X1 X0 X3 * Y0 X0 * Y3 X2 * Y1 X1 * Y2 DY2 Y1 Y0X2 X1 X3 * Y1 X1 * Y3 X2 * Y2 EY2 Y1X2 X3 * Y2 X2 * Y3 FY2 X3 * Y3 GY33) Algorithm for 8 X 8 Bit Multiplication Using Urdhva Triyakbhyam for twoBinary numbersA B A7A6A5A4A3A2A1A0X1X0B7B6B5B4B3B2B1B0Y1Y0X1X0* ----------FEDCCP X0 * Y0 CCP X1 * Y0 X0 * Y1 D CP X1 * Y1 EWhere CP Cross Product.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE9
For the illustration of the multiplication algorithm, the multiplication of twobinary numbers a3a2a1a0 and b3b2b1b0 are explained. The result of this multiplicationis expressed as. r3r2r1r0 since it should be more than 4 bits. Fig 2.2 shows the linediagram for multiplication of two 4-bit numbers which is nothing but the mapping of thebinary system in Fig 2.1. Each bit is represented by a circle for the simplicity. the leastsignificant bits of the multiplicand and the multiplier are multiplied to obtain leastsignificant bit r0.Figure 2.2: Showing Line diagram for multiplication of two 4 - bit numbers.The least significant bit of the product is first obtained by multiplying leastsignificant bits. Then, the product of LSB of multiplier and next higher bit of themultiplicand are added with the multiplication of LSB of the multiplicand and the nexthigher bit of the multiplier . This sum results in second bit of the product and the carry isadded in the output of next stage sum obtained by the crosswise and verticalmultiplication and addition of three bits of the two numbers from least significantposition. Next, all the four bits are processed with crosswise multiplication and additionto give the sum and carry. The sum is the corresponding bit of the product and the carryis again added to the next stage multiplication and addition of three bits except the LSB.The same operation continues until the multiplication of the two MSBs to give the MSBof the product. For example, if in some intermediate step, we get 110, then 0 will act asresult bit (referred as rn) and 11 as the carry (referred as cn).PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE10
r0rr0 a0b0;(1)c1rr1 a1b0 a0b1;(2)c2rr2 c1 a2b0 a1b1 a0b2;(3)c3rr3 c2 a3b0 a2b1 a1b2 a0b3;(4)c4rr4 c3 a3b1 a2b2 a1b3;(5)c5rr5 c4 a3b2 a2b3;(6)c6rr6 c5 a3b3(7)The final product is c6r6r5r4r3r2r1r0 being. Thus all cases of multiplicationsemploy this general mathematical formula.Figure 2.3: Showing Hardware architecture of the Urdhva tiryakbhyam multiplierThe proposed hardware architecture design resembles that of the popular arraymultiplier where the final product is achieved through an array of adders. All the partialproducts are calculated in parallel in general array multiplier so that the delay associatedis clearly the time taken by the carry to propagate through the adders which form thePACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE11
multiplication array. Thus array multiplier is not suitable for the multiplication of largenumbers because of large propagation delay involved. An efficient multiplier algorithmfor multiplication of two large numbers is the Nikhilam Sutra algorithm.2.2.1.2 Nikhilam SutraThe meaning of Nikhilam Sutra is all from nine and last from ten. All cases ofmultiplication can employ Nikhilam Sutra, when the numbers involved are large it ismore effective. To perform the multiplication operation it finds out the compliment ofthe large number from its nearest base. This multiplication algorithm is less complex forlarge numbers. Let us consider the multiplication of two decimal numbers (96 * 93) herethe base is chosen 100 since it is nearest to and greater than both these two numbers.Figure 2.4: Showing Multiplication Using Nikhilam SutraWith simple multiplication of the numbers of the Column 2 (7*4 28) the righthand side (RHS) of the product resulted. By cross subtracting the second number ofColumn 2 from the first number of Column 1 or vice versa, i.e., 96 - 7 89 or 93 - 4 89 the left hand side (LHS) of the product can be obtained. By concatenating RHS andLHS (Answer 8928) the final result is obtained.PACE INSTITUTE OF TECHNOLOGY AND SCIENCES, ECE12
2.2.2 SQUARE ALGORITHMUrdhva Triyakbhyam‟s square of a property is calculated using the Duplex. Theduplex can be achieved by taking twice the product of the outermost pair and then addtwice the product of the next outermost pair and so on till no pairs are left. When thereare odd numbers of bits in the original sequence, there is no possibility of leaving at leastone bit by itself in the middle so that this enters as its square. Thus for 987654321,D 2 * ( 9 * 1) 2 * ( 8 * 2 ) 2 * ( 7 * 3 ) 2 * ( 6 * 4) 5 * 5 165.The Duplex can be explained further as followsFor a 1 bit number D is its square.For a 2 bit number D is twice their productFor a 3 bit number D is twice the product of the outer pair square of the middle bit.F
2.4 design synopsis 16 3. design and software simulation 20 3.1implementation of 2x2 bits vedic multipl ier 20 3.2 implementation of 4x4 bits multiplier 21 3.3 implementation of 8x8 bit multiplier 23 4. implementation and testing of multiplier 25 4.1fpga implimentation 25
akuntansi musyarakah (sak no 106) Ayat tentang Musyarakah (Q.S. 39; 29) لًََّز ãَ åِاَ óِ îَخظَْ ó Þَْ ë Þٍجُزَِ ß ا äًَّ àَط لًَّجُرَ íَ åَ îظُِ Ûاَش
Collectively make tawbah to Allāh S so that you may acquire falāḥ [of this world and the Hereafter]. (24:31) The one who repents also becomes the beloved of Allāh S, Âَْ Èِﺑاﻮَّﺘﻟاَّﺐُّ ßُِ çﻪَّٰﻠﻟانَّاِ Verily, Allāh S loves those who are most repenting. (2:22
3.1 An Overview of Linking Project Design, Annual Planning and M&E When you “manage for impact”, project design, annual planning and M&E become linked processes. Your starting point for implementation is the initial project design as outlined in the project appraisal report. But design is an ongoing process for the life of the project.
Project Design Guidance provides a comprehensive approach to project design that is relevant to all ChildFund supported projects. The processes and steps in this Guidance represent minimum standards for project design. The Project Design Guidance will help ensure consistent quality of project design across all ChildFund supported projects.
DIDET Project – Final Report – 1.0 – 1st August 2008 Page 1 of 26 JISC DEVELOPMENT PROGRAMMES Project Document Cover Sheet DIDET Project Final Report Project Project Acronym DIDET Project ID Project Title Digital Libraries for Distributed, Innovative Design Education and Teamwork Start Date 1 March 2003 End Date 29 February 2008
6. phase one: planning a project-design process 8 7. phase two: undertaking a project-design process 11 8. the project development document (pdd) 11 9. project-level monitoring, evaluation and cla 13 10. library of project designs on programnet 13 11. project implementation 14 12. life of a project 16 13. u
IV. PMO Project Management Lifecycle (Refer to attachment 2 - OIT PMO Project Management Lifecycle) The Project Management Process governs the project life-cycle which is comprised of the following five phases: 1. Project Initiating phase 2. Project Planning phase 3. Project Funding phase 4. Project Executing phase 5. Project Closing phase
Project success is one of the most important topic in project management (Prabhakar, 2009). Importance of the project success varies by the contract of the project, type of project and individual role of personality in project also (Muller & Jugdev, 2012). Project success comprises of two parts. First is success of project management and
