DM3730, DM3725 Digital Media Processors Datasheet (Rev. D)
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comDM3730, DM3725Digital Media ProcessorsCheck for Samples: DM3730, DM37251 DM3730, DM3725 Digital Media Processors1.1Features123456 DM3730/25 Digital Media Processors:– Compatible with OMAP 3 Architecture– ARM Microprocessor (MPU) Subsystem Up to 1-GHz ARM Cortex -A8 CoreAlso supports 300, 600, and 800-MHzoperation NEON SIMD Coprocessor– High Performance Image, Video, Audio(IVA2.2TM) Accelerator Subsystem Up to 800-MHz TMS320C64x TM DSP CoreAlso supports 260, 520, and 660-MHzoperation Enhanced Direct Memory Access (EDMA)Controller (128 Independent Channels) Video Hardware Accelerators– POWERVR SGX Graphics Accelerator(DM3730 only) Tile Based Architecture Delivering up to20 MPoly/sec Universal Scalable Shader Engine:Multi-threaded Engine Incorporating Pixeland Vertex Shader Functionality Industry Standard API Support:OpenGLES 1.1 and 2.0, OpenVG1.0 Fine Grained Task Switching, LoadBalancing, and Power Management Programmable High Quality ImageAnti-Aliasing– Advanced Very-Long-Instruction-Word(VLIW) TMS320C64x TM DSP Core Eight Highly Independent FunctionalUnits Six ALUs (32-/40-Bit); Each SupportsSingle 32- bit, Dual 16-bit, or Quad 8-bit,Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16-BitMultiplies (32-Bit Results) per ClockCycle or Eight 8 x 8-Bit Multiplies (16-BitResults) per Clock Cycle Load-Store Architecture WithNon-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x TM Enhancements– Protected Mode Operation– Expectations Support for ErrorDetection and Program Redirection– Hardware Support for Modulo LoopOperationTM– C64x L1/L2 Memory Architecture 32K-Byte L1P Program RAM/Cache(Direct Mapped) 80K-Byte L1D Data RAM/Cache (2-WaySet- Associative) 64K-Byte L2 Unified Mapped RAM/Cache(4- Way Set-Associative) 32K-Byte L2 Shared SRAM and 16K-ByteL2 ROM– C64x TM Instruction Set Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting Compact 16-Bit Instructions Additional Instructions to SupportComplex Multiplies– External Memory Interfaces: SDRAM Controller (SDRC)– 16, 32-bit Memory Controller With1G-Byte Total Address Space– Interfaces to Low-Power SDRAM– SDRAM Memory Scheduler (SMS) andRotation Engine General Purpose Memory Controller(GPMC)– 16-bit Wide Multiplexed Address/Data123456Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.POWERVR SGX is a trademark of Imagination Technologies Ltd.OMAP is a trademark of Texas Instruments.Cortex, NEON are trademarks of ARM Limited.ARM is a registered trademark of ARM Ltd.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.Copyright 2010–2011, Texas Instruments Incorporated
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011––––2www.ti.comBus– Up to 8 Chip Select Pins With128M-Byte Address Space per ChipSelect Pin– Glueless Interface to NOR Flash,NAND Flash (With ECC HammingCode Calculation), SRAM andPseudo-SRAM– Flexible Asynchronous ProtocolControl for Interface to Custom Logic(FPGA, CPLD, ASICs, etc.)– Nonmultiplexed Address/Data Mode(Limited 2K-Byte Address Space)1.8-V I/O and 3.0-V (MMC1 only),0.9-V to 1.2-V Adaptive Processor CoreVoltage0.9-V to 1.1-V Adaptive Core Logic VoltageNote: These are default OperatingPerformance Point (OPP) voltages and couldbe optimized to lower values usingSmartReflex AVS.Commercial, Industrial, and ExtendedTemperature GradesSerial Communication 5 Multichannel Buffered Serial Ports(McBSPs)– 512 Byte Transmit/Receive Buffer(McBSP1/3/4/5)– 5K-Byte Transmit/Receive Buffer(McBSP2)– SIDETONE Core Support (McBSP2 and3 Only) For Filter, Gain, and MixOperations– Direct Interface to I2S and PCM Deviceand T Buses– 128 Channel Transmit/Receive Mode Four Master/Slave Multichannel SerialPort Interface (McSPI) Ports High-Speed/Full-Speed/Low-Speed USBOTG Subsystem (12-/8-Pin ULPI Interface) High-Speed/Full-Speed/Low-SpeedMultiport USB Host Subsystem– 12-/8-Pin ULPI Interface or 6-/4-/3-PinSerial Interface One HDQ/1-Wire Interface Four UARTs (One with Infrared DataAssociation [IrDA] and Consumer Infrared[CIR] Modes) Three Master/Slave High-SpeedInter-Integrated Circuit (I2C) ControllersCamera Image Signal Processing (ISP) CCD and CMOS Imager Interface Memory Data Input BT.601/BT.656 Digital YCbCr 4:2:2(8-/10-Bit) Interface Glueless Interface to Common VideoDecoders Resize Engine– Resize Images From 1/4x to 4x– Separate Horizontal/Vertical Control– System Direct Memory Access (SDMA)Controller (32 Logical Channels WithConfigurable Priority)– Comprehensive Power, Reset, and ClockManagement SmartReflexTM Technology Dynamic Voltage and Frequency Scaling(DVFS)– ARM Cortex -A8 Core ARMv7 Architecture– TrustZone – Thumb -2– MMU Enhancements In-Order, Dual-Issue, SuperscalarMicroprocessor Core NEON Multimedia Architecture Over 2x Performance of ARMv6 SIMD Supports Both Integer and Floating PointSIMD Jazelle RCT Execution EnvironmentArchitecture Dynamic Branch Prediction with BranchTarget Address Cache, Global HistoryBuffer, and 8-Entry Return Stack Embedded Trace Macrocell (ETM)Support for Non-Invasive Debug– ARM Cortex-A8 Memory Architecture: 32K-Byte Instruction Cache (4-WaySet-Associative) 32K-Byte Data Cache (4-WaySet-Associative) 256K-Byte L2 Cache– 32K-Byte ROM– 64K-Byte Shared SRAM– Endianess: ARM Instructions - Little Endian ARM Data – Configurable DSP Instructions/Data - Little EndianRemovable Media Interfaces:– Three Multimedia Card (MMC)/ Secure Digital(SD) With Secure Data I/O (SDIO)Test Interfaces– IEEE-1149.1 (JTAG) Boundary-ScanCompatible– Embedded Trace Macro Interface (ETM)– Serial Data Transport Interface (SDTI)12 32-bit General Purpose Timers2 32-bit Watchdog TimersDM3730, DM3725 Digital Media ProcessorsSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725Copyright 2010–2011, Texas Instruments Incorporated
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com 1 32-bit Secure Watchdog Timer 1 32-bit 32-kHz Sync Timer Up to 188 General-Purpose I/O (GPIO) Pins(Multiplexed With Other Device Functions) 45-nm CMOS Technology Package-On-Package (POP) Implementation forMemory Stacking (Not Available in CUSPackage)Copyright 2010–2011, Texas Instruments Incorporated Packages:– 515-pin s-PBGA package (CBP Suffix), .5mmBall Pitch (Top), .4mm Ball Pitch (Bottom)– 515-pin s-PBGA package (CBCSuffix), .65mm Ball Pitch (Top), .5mm BallPitch (Bottom)– 423-pin s-PBGA package (CUSSuffix), .65mm Ball PitchDM3730, DM3725 Digital Media ProcessorsSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM37253
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 20111.2www.ti.comDescriptionThe DM37x generation of high-performance, digital media processors are based on the enhanced devicearchitecture and are integrated on TI's advanced 45-nm process technology. This architecture is designedto provide best in class ARM and Graphics performance while delivering low power consumption. Thisbalance of performance and power allow the device to support the following example applications: Portable Data Terminals Navigation Auto Infotainment Gaming Medical Imaging Home Automation Human Interface Industrial Control Test and Measurement Single board ComputersThe device can support numerous HLOS and RTOS solutions including Linux and Windows EmbeddedCE which are available directly from TI. Additionally, the device is fully backward compatible with previousCortex -A8 processors and OMAP processors.This DM3730/25 Digital Media Processor data manual presents the electrical and mechanicalspecifications for the DM3730/25 Digital Media Processor. The information contained in this data manualapplies to the commercial, industrial, and extended temperature versions of the DM3730/25 Digital MediaProcessor unless otherwise indicated. It consists of the following sections: A description of the DM3730/25 terminals: assignment, electrical characteristics, multiplexing, andfunctional description A presentation of the electrical characteristics requirements: power domains, operating conditions,power consumption, and dc characteristics The clock specifications: input and output clocks, DPLL and DLL A description of thermal characteristics, device nomenclature, and mechanical data about the availablepackaging4DM3730, DM3725 Digital Media ProcessorsSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725Copyright 2010–2011, Texas Instruments Incorporated
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com1.3Functional Block DiagramThe functional block diagram of the DM3730/25 Digital Media Processor is shown below.LCD PanelIVA 2.2 SubsystemTMS320DM64x DSPImaging Video andAudio Processor32K/32K L1 48K L1D RAM64K L2 32K L2 RAM16K L2 ROMVideo (Parallel)Amp ARMCortex - A8 CoreTrustZone32K/32K L1 ParallelTMPOWERVRSGXGraphicsAcceleratorL2 CaptureHardwareImagePipelineDual Output 3-LayerDisplay Processor(1xGraphics, 2xVideo)Temporal DitheringSDTV QCIF Support3264HS USBHostHSUSBOTG32Async326464L3 Interconnect Network-Hierarchial, Performance, and Power 23232L4 D/NORFlash,SRAMExternal andStacked MemoriesPeripherals: 4xUART,3xHigh-Speed I2C, 5xMcBSP(2x with Sidetone/Audio Buffer)4xMcSPI, 6xGPIO3xHigh-Speed MMC/SDIOHDQ/1 Wire, 6xMailboxes12xGPTimers, 2xWDT,32K Sync eExternalPeripheralsInterfacesEmulationDebug: SDTI, ETM, JTAGFigure 1-1. DM3730/25 Functional Block DiagramCopyright 2010–2011, Texas Instruments IncorporatedDM3730, DM3725 Digital Media ProcessorsSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM37255
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comRevision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.This data sheet revision history highlights the technical changes made from the previous to the currentrevision.Revision HistorySECTIONADDITIONS/CHANGES/DELETIONSTerminal DescriptionChanged: Table 2-1. Ball Characteristics (CBP Pkg.). Removed restriction note from GPIO 16. Table 2-2. Ball Characteristics (CBC Pkg.). Removed restriction note from GPIO 16. Table 2-3. Ball Characteristics (CUS Pkg.). Removed restriction note from GPIO 16.Electrical CharacteristicsChanged: Table 3-1. Absolute Maximum Rating over Junction Temperature Range. Added JTAG toVESD. Table 3-5. DC Electrical Characteristics. Removed USIM ball R27.Clock SpecificationsAdded note on rise and fall times for these tables: Input Clock Requirements sys xtalin Squarer Input Clock Timing Requirements - Bypass Mode sys 32k Input Clock Timing Requirements sys altclk Input Clock Timing Requirements sys clkout1 Output Clock Switching Characteristics sys clkout2 Output Clock Switching CharacteristicsAdded: Table 4-2, Crystal Electrical Characteristics. Added entry for DL - Crystal drive level6DM3730, DM3725 Digital Media ProcessorsSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725Copyright 2010–2011, Texas Instruments Incorporated
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com2 TERMINAL DESCRIPTION2.1Terminal AssignmentFigure 2-1 through Figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array(s-PBGA) packages. Table 2-1 through Table 2-25 indicate the signal names and ball grid numbers forboth packages.Note: There are no balls present on the top of the 423-ball s-PBGA package.AHAGAFAEADACABAAYWVUTRPNMLKJHGFEDCBA1 23456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28030-001Figure 2-1. DM3730/25 Digital Media Processor CBP s-PBGA-N515 Package (Bottom View)TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM37257
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 171815161113141291057861342030-002Figure 2-2. DM3730/25 Digital Media Processor CBP s-PBGA-N515 Package (Top View)8TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comAFAEADACABAAYWVUTRPNMLKJHGFEDCBA1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26Figure 2-3. DM3730/25 Digital Media Processor CBC s-PBGA-515 Package (Bottom View)TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM37259
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comAAYWVUTRPNMLKJHGFEDCBA21 20 19 18 17 16 15 14 13 12 11 10 987654321Figure 2-4. DM3730/25 Digital Media Processor CBC s-PBGA-515 Package (Top View)10TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24Figure 2-5. DM3730/25 Digital Media Processor CUS s-PBGA-N423 Package (Bottom View)2.22.2.1Pin AssignmentsPin Map (Top View)The following pin maps show the top views of the 515-pin sPBGA package [CBP], the 515-pin sPBGApackage [CBC], and the 423-pin sPBGA package [CUS] pin assignments in four quadrants (A, B, C, andD).Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pinsmust be left unconnected.TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372511
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com1234567891011121314ANCNCvssNCvdds memNCNCvdds memNCNCNCvdds memNCNCBNCvssNCNCvdds memNCNCvdds memNCNCNCvdds NCvssvdd corevdd corevssNCNCvssNCENCNCvssvssNCNCNCNCNCNCF vdds mem vdds mem gpmc nadv gpmc nwealeGgpmc noe gpmc nbe0 gpmc ncs0cleNCH gpmc nwpgpmc d8J vdds mem vdds memgpmc ncs1vdd corevssvdd coregpmc wait3vdd mpuivavdd mpuivavdd mpuivavssvssvdd mpuivavdd mpuivavssvdd mpuivavdd mpuivaKgpmc d0gpmc d9gpmc a10gpmc a4gpmc wait2vssvssLgpmc d1gpmc d2gpmc a9gpmc a3gpmc wait1vdd mpuivavdd mpuivaMpop y23m1pop k2m2gpmc a8gpmc a2gpmc wait0vdd mpuivavdd mpuivaNpop u1n1pop l2n2gpmc a7gpmc a1gpmc ncs7vssvdd mpuivagpmc d3vssvssgpmc ncs6vssvssP gpmc d10A.Top Views are provided to assist in hardware debugging efforts.Figure 2-6. CBP Pin Map [Quadrant A - Top View]12TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com1516171819202122232425262728pop a12a15NCNCvdds memNCNCNCvdds memcam vscam hscam d5vsspop a22a27pop a23a28Apop b12b15NCNCvdds memNCNCNCvdds memcam wencam d2cam d10cam xclkbvsspop b23b28BNCvdds memNCNCvssNCNCvsscam fldcam d3cam xclkacam d11cam pclkvdds memCvdd corevdds memNCNCvssNCvssvdd corevdd corecam d4cam strobe dss hsync dss vsyncdss pclkDvdd corevddsdss data6 dss acbias dss data20 Evddsdss data16 dss data9dss data8dss data7Fvssvdds memGvddsHpop k1j28JNCNCNCuart3 ctsrctxuart3 rtssduart3 rxirrxuart3 txirtxvdd mpuivavssvssvdd corevdd corevdd corei2c1 sdahdq siodss data21pop h22j27vdda dpllsdllvssvssvdd corevssvdd corei2c1 sclvddsmmc1mcbsp1 fsxcam d8cam d6Kvssvsscap vddsram corevdd corevsscam d9cam d7Lvdd corevssmcbsp2 dxvdd corepop k22m26mmc1cmdvssMvdd corevdd coremcbsp2clkxmmc1dat2mmc1dat1mmc1dat0mmc1clkNgpio 126mmc1dat3Pvssdss data19 dss data18 dss data17vdd core mcbsp2 fsxvdds xgpio 127Figure 2-7. CBP Pin Map [Quadrant B - Top View]TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372513
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comRgpmc d11gpmc d12gpmc a6vdds memgpmc ncs5vdd mpuivavdd mpuivaTgpmc d4gpmc d13gpmc a5gpmc clkgpmc ncs4vdd mpuivavdd mpuivaUvdds memvsscap vddgpmc nbe1 bb mpuivagpmc ncs3vssvdd mpuivaVgpmc d5gpmc d6mcspi2cs1cap vddsrammpu ivagpmc ncs2vssvssW gpmc d14gpmc d7vssvddsuart1 ctsvdd mpuivavssvdd mpuivavdd mpuivavssvssY gpmc d15mcspi2simomcspi2somimcspi2cs0uart1 rxvdd mpuivavdd mpuivavdd mpuivavssvssvdd mpuivapop aa2aa2mcspi2 clkmcspi1somiuart1 txuart1 rtsjtag rtckjtag tckvdda wkupbg bbmcspi1simoetk d10vddsvdd coreetk ctletk d4vssetk d3sys boot2AApop aa1aa1ABmcspi1cs2mcspi1cs3mcspi1 clkACmcbsp4fsxmcspi1cs0mcspi1 cs1 vdd coreAD mcbsp4 dr mcbsp4 dxAEmcbsp4clkxAFpop ac8af1mmc2clkpop u2af2jtag emu1 jtag clkxmcbsp3 dxetk d11vddsetk d8etk clketk d0vssetk d6i2c3 sclpop ab8ag10pop ab9ag11etk d1pop ab11ag13i2c3 sdamcbsp3 fsx mcbsp3 drAGpop ab1ag1vssvssmmc2dat2mmc2cmdvssetk d12etk d14etk d9AHpop ac1ah1pop ac2ah2mmc2dat5mmc2dat1mmc2dat0vdds memetk d13etk d15etk d5pop ac13ah10pop ac9ah11etk d2pop ac11ah13etk d71234567891011121314Figure 2-8. CBP Pin Map [Quadrant C - Top View]14TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comRhsusb0data0hsusb0 eo2outWmcbsp1clkrvssvssa daccvideo1vfbcvideo1outYmcbsp1 fsruart2 txNCdssdata15dssdata14uart2 rtsuart2 ctsvssvssuart2 rxi2c4 sclsys 32ki2c4 sdaNCpop aa23ae28AEsys nirqpop aa22af27pop h23af28AFvddspop ab23ag28AGpop ac22ah27pop ac23ah28AH2728mcbsp2 drvdd corevssmcbsp clksvdd corevdd coremcbsp1 drhsusb0data4vssvdd coremcbsp1 dxvdda dacmcbsp1clkxvdds sramvssvdd corevssvdd corevdd mpuivavdd coresysxtalgndvdd corevdd corevdd corejtag ntrstjtag tmstmscjtag tdojtag tdivdda dpllperhsusb0 dirvssvdd mpuivacap vdduwkuplogicgpio 128vssgpio 129hsusb0 stp hsusb0 nxti2c2 sdavddssys xtalinvdd corevsssys boot5 sys clkout2i2c2 sclvddssys xtalout sys boot3 sys boot4vsssys boot6pop ab13ag15vsscam d0gpio 114gpio 112vddsvddspop l1ah15pop ac14ah16cam d1gpio 115gpio 113cap vdduarrayvssdss data1dss data3dss data515161718192021222324vdd corevsssys offmodevddsvddsdss data0 dss data2vdd coresys clkreqsysnreswarmdss data4 sys clkout1 sys boot1syssys boot0nrespwron2526dss data13 dss data12dssdata22dssdata23dss data11 dss data10AAABACADFigure 2-9. CBP Pin Map [Quadrant D - Top View]TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372515
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com12345678910111213Apop mcwait2gpmcncs4gpmcncs6gpmcncs3NCNCNCNCNCNCNCi2c2 sNCNCcapvdd bbmpu ivavssNCvddsvssNCvssvdd mpuivaC I2C2 ot5vddsNCvssvdd mpuivavssvddcorevdd mpuivaNCHgpmca2gpmca3uart1rxvssvdd CKvssgpmcnbe0clemmc2dat7NCNCNCNCNCvdd mpuivaNCvddadpllsdllLpop j1l1gpmcd14mmc2dat6uart1txvddsNCvdd mpuivavssMgpmcnwegpmcd15mmc2dat5vddsvddcoreNCvdd mpuivavdd mpuivaNgpmcclkgpmcnoemcbsp3drvssvdd mpuivavdd mpuivacap vddsrammpu ivavssA.Top Views are provided to assist in hardware debugging efforts.Figure 2-10. CBC Pin Map [Quadrant A - Top View]16TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.com14151617181920212223242526popa21 a26ANCNCNCNCvddsNCpop b16a20NCNCcam wencam d2popa20 a25NCNCNCNCNCNCNCNCNCcam fldcam d3vsspopb21 b26BNCNCNCNCNCNCNCNCNCcam hscam d5camxclkacampclkCvssvddcoreNCNCvssNCvssNCNCcam vscam d4cam d10camstrobeDvssNCvddscamxclkbcam d11Edssdata20dssacbiasFuart3ctsrctxuart3rts HNCvddsNCNCvddsNCNChdq sioi2c1 sdai2c1 scldssdata9Jcap vdduwkuplogicvssNCNCmmc1dat2NCcap vddsramcoreNCdsshsyncvsspoph21 coremmc1dat1mmc1dat0gpio t3vddsmmc1dssdata21cam d8cam d9NFigure 2-11. CBC Pin Map [Quadrant B - Top View]TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372517
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY simomcspi1clkvdd pi1cs2mmc2cmdTgpmcd10pop gpmcd12gpmcd11mcbsp3clkxmcbsp4drvdd mpuivamcspi2somimmc2dat3mmc2dat2vdd mpuivavddssramvdd mpuivaVgpmcd8etk d9mcbsp4clkxNCvdd mpuivamcspi2cs0mcspi2cs1mmc2dat4vdd mpuivasys lkmcspi2simovdd mpuivammc2clksysclkout2NCjtagrtckYgpmcd9pop t2y2etk d4vddsvssvddcorevdd mpuivavssvdd mpuivavddcorejtagtdoAAgpmcd1gpmcd0etk d3etk d8ABetk d5etk clketk ctli2c3 sclvssACgpmcd3gpmcd2etk d0i2c3 pmcncs1etk d7etk d2etk d1gpmcd6gpmcd5sysnreswarmgpmcncs0NCgpmcnadv aleNCNCNCAENCpop w2ae2etk d6etk d10gpmcd4etk d12vssNCetk d15vddsNCNCNCAFNCNCNCpop y2af4pop aa6af5etk d11etk d13pop y7af8etk d14pop y9af10NCpop aa10af12pop aa11af1312345678910111213Figure 2-12. CBC Pin Map [Quadrant C - Top View]18TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comgpio 127gpio 128gpio 129mcbsp1fsxvdds xNCcam d6cam mcbsp2drmcbspclksmcbsp1drvssvddsNCNCTjtag bvsspopp21 u26UVvddadpll perjtagntrstjtag tckjtag tmstmscsys 1rsetvssadacvddadaccvideo2outvddawkupbg bbsysclkreqi2c4 sdssdata22dssdata10ACvssi2c4 sclgpio 113gpio sdata11ADsysclkout1cam d1cam d0gpio 115gpio 114capvdduarraysys 32kdssdata0dssdata1dssdata2dssdata3pop y20ae25pop y21ae26AEpop aa12af14pop aa13af15pop aa14af16pop y14af17pop aa17af18sysxtalinsysxtaloutpop y17af21popaa19 af22sysxtalgndpop y19af24pop aa20af25pop aa21af26AF14151617182021222324252619Figure 2-13. CBC Pin Map [Quadrant D - Top View]TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372519
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 201112ANCNCBNCsdrc a4sdrc a3Cgpmcwait0gpmcwait3sdrc a545sdrc a0sdrcdqs0sdrc a1sdrc d3sdrc d1gpmcncs3DEgpmcnwpgpmcncs0sdrc w.ti.comgpmcd4mcspi2cs1gpmcncs5gpmcnbe0 clemcspi2cs0678sdrcdm2sdrcdqs2sdrcdm0sdrc d7sdrc d18sdrc d2sdrc a29101112sdrcclksdrcnclksdrc d19sdrc d21sdrc d8sdrc d6sdrc d16sdrc d20sdrc d9sdrc d0sdrc d4sdrc d5sdrc d22sdrc a10sdrc a9sdrc a8sdrc d17sdrc a7sdrc a13sdrc a14vdd mpuivavddcoresdrc a11sdrc a12vdd mpuivavdd mpuivavddcorevdds xvdd mpuivavdd mpuivavssvddcorevdd mpuivavdd mpuivavssvsssdrc svssvssvdd mpuivavdd mpuivavssvssvdd mpuivavdd mpuivavdd mpuivavdd mpuivavssTop Views are provided to assist in hardware debugging efforts.Figure 2-14. CUS Pin Map [Quadrant A - Top View]20TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY rcba1sdrcnrassdrcd23sdrcd24vddsmemcam vsvddcorevddsmemvddsmemcam wencam d3vddcorevddsmemvddsmemvddadpllsdllcam d2cam d421222324cam hsuart3ctsrctxhdq rtxcam d5Cdssdata20dssdata6Ddsshsyncdssdata7dssdata8Ecam d10dssvsyncdssdata9cam d11dsspclkdssdata17dssdata18Gdssdata19cam fldHFvddcorevssvddsmemvsscap obedssacbiasdssdata16cam d8vssvssvddcorevddcorevddcorei2c1 scli2c1 sdadssdata21cam d9cam d7Kvssvddcorevddcorevssmmc1cmdcam 1mmc1dat0mmc1clkJMFigure 2-15. CUS Pin Map [Quadrant B - Top View]TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372521
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY vdd mpuivavdd mpuivavdd gpmcd7gpmcd8gpmcd11mcspi1simomcbsp1cs3vdd mpuivavdd mpuivavdd mpuivagpmcd9gpmcd12mcspi1somimcspi1clkmcspi1cs0vdd mpuivavdd mpuivavssvssvssvsscap vddsrammpu ivavssvddsvssvdd dat6AAmmc2dat7mmc2dat5ABmmc2dat4mmc2dat0ACetk clkuart1ctsetk d10ADNCetk d5etk ctl123etk d84mcbsp3dxuart1rxvddsvddsvdd mpuivauart1rtsuart1txvddsvddsvdd mpuivasysclkout1vddssysnreswarmcap vdduwkup logicsysclkout2jtagrtckjtag jtagtdojtagtdisysboot0etk d4etk d1etk d2etk d6etk d11etk d12etk d9etk d0etk d3etk d75689mcbsp3dr710etk d14i2c3 sdaetk d13etk d151112Figure 2-16. CUS Pin Map [Quadrant C - Top View]22TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM3725
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 2011www.ti.comvddsvddsvddscap vdduarraycap vddbb mpuivagpio 126mmc1dat3vddsmmc1Nhsusb0dirgpio usb0data1hsusb0data0Tvdd dd mpuivavssvssmcbsp1clkxmcbsp2drvdd i2c4 sdai2c4 sclmcbsp1drvddawkupbg bbsysboot6sys 32kmcbspclksmcbsp1fsxvddadacvssa dacsysboot5cam d0dssdata1mcbsp1fsri2c2 sdai2c2 sclsysboot1sysboot4cam t2sysboot3dssdata2dssdata414152021i2c3 ys offmodejtagemu1AD232422Figure 2-17. CUS Pin Map [Quadrant D - Top View]TERMINAL DESCRIPTIONCopyright 2010–2011, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Link(s): DM3730 DM372523
DM3730, DM3725SPRS685D – AUGUST 2010 – REVISED JULY 20112.3www.ti.comBall CharacteristicsTable 2-1 through Table 2-3 describe the terminal characteristics and the signals multiplexed on each pinfor the CBP, CBC, and CUS packages, respectively. The following list describes the table columnheaders.1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom.2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is thesignal name in mode 0).Note: Table 2-3 does not take into account subsystem pin multiplexing options. Subsystem pinmultiplexing options are described in Section 2.5, Signal Descriptions.3. MODE: Multiplexing mode number.(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pincorresponds to the name of the pin. There is always a function mapped on the primary mode.Notice that primary mode is not necessarily the default mode.Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODEcolumn.(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectivelyused for alternate functions, while some modes are not used and do not correspond to a functionalconfiguration.4. TYPE: Signal direction– I Input– O Output– I/O Input/Output– D Open drain– DS Differential– A Analog– PWR Power– GND GroundNote: In the safe mode, the buffer is configured in high-impedance.5. BALL RESET STATE: The state of the terminal at the power-on reset.– 0: The buffer drives VOL (pulldown/pullup resistor not activated)0(PD): The buffer drives VOL with an active pulldown resistor.– 1: The buffer drives VOH (pulldown/pullup resistor not activated)1(PU): The buffer drives VOH with an active pullup resistor.– Z: High-impedance– L: High-impedance with an active pulldown resistor– H : High-impedance with an active pullup resistor6. BALL RESET REL. STA
This DM3730/25 Digital Media Processor data manual presents the electrical and mechanical specifications for the DM3730/25 Digital Media Processor. The information contained in this data manual applies to the commercial, industrial, and extended temperature versions of the DM3730/25 Digital Media Processor unless otherwise indicated.
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