Digital Circuits: CMOS
6.012 - Microelectronic Devices and CircuitsLecture 15 - Digital Circuits: CMOS - Outline Announcements One supplemental reading on StellarExam 2 - Thursday night, Nov. 5, 7:30-9:30Review - Inverter performance metricsTransfer characteristic: logic levels and noise marginsPower: Pave, static Pave, dynamic ( IONVDD/2 f CLVDD 2 )Switching speed: charge thru pull-up, discharge thru pull-downIf can model load as linear C: dvOUT/dt iCH(vOUT)/CL; iDCH(vOUT)/CLIf can say iCH, iDCH constant: τHI-LO CL(VHI-VLO)/ICH ; τHI-LO CL(VHI-VLO)/IDCHFan-out, fan-inManufacturability(often only 10 to 90% swings) CMOSTransfer characteristicGate delay expressionsPower and speed-power product Velocity SaturationGeneral commentsImpact on MOSFET and Inverter CharacteristicsClif Fonstad, 11/3/09Lecture 15 - Slide 1
V OUTV DDTransfer characteristicV HINode equation: iPD iPU0for vIN VT,PDiPD KPD(vIN-VT,PD)2/2 for vIN-VT,PD vOUTKPD(vIN-VT,PD -vOUT/2) vOUTforv -VIN T,PD vOUTGives us: VHI and VLONML and NMHClif Fonstad, 11/3/09VMvOUTV LO–V INNMLV DDGeneral approach:Bigger current faster vOUT changeiPD V LO V 1L V M V 1HSwitching transientsdvout/dt iCL/CLiPU vIN–iPU: Depends on the device usedThe load, CL, is a nonlinear charge store, butfor MOSFETs it is fairlylinear and it is useful tothink linear:PullUpPullUpV DDNMHPullUp iiPUV HIPUiDischarge HI to LO–OFF LOtoHI–Charging cycle:iCharge iPUCL ON LO to HI–iPDHItoLOCL–Discharging cycle:iDischarge iPD – iPULecture 15 - Slide 2
V DDMOSinverters:PullUp5 pull-upchoicesRLResistorpull-up v OUT v IN–GenericinverterV DD CL v IN––V DDV DDv OUT–V DDV DDV GG( V DD ) v IN–v OUT– v IN–v OUTn-channel, e-mode pull-upVDD on gateVGG on gateClif Fonstad, 11/3/09* Known as PMOS when made with p-channel.– v IN– v OUT v INv OUT––– n-channel, d-modepull-up (NMOS)Active p-channelpull-up (CMOS)**Lecture 15 - Slide 3** Notice that CMOS has a larger ( 3x) input capacitance.
Switching transients: summary of charge/discharge currentsV DDResistor and Emode pull-up(VGG on gate)iPU iChargeV DDRLV GG( V DD ) v IN–iPD iDischarge iPU v OUT v IN––IONiChargev OUTiDischargeION–v OUTv OUTV DDiPU iChargeV DDiPD iDischargeE-mode pull-up(VDD on gate)ION v IN–iDischargeIONiChargev OUT–v OUTv OUTV DDiPU iChargeV DDiPD iDischargeD-mode pull-upV DD iPUiDischarge(called "NMOS") IONIONiChargev OUT v IN––v OUTiPU iChargeCMOSv OUT––iPD iDischargeiCharge v INv OUTV DDV DDClif Fonstad, 11/3/09V DD iPUiDischargev OUT IONIONION 0V DD iPUV DD Comparisons made with same pull-down MOSFET, VHI, and ION.v OUTV DDLecture 15 - Slide 4
CMOS: transfer characteristic calculationV DDvOUTvOUTvSGp VTp vGSn V TnV DDV DDQnoffQp v INQnvDSn vGSn -V TnQn : vSGp vSDp - V Tp Qp :QpoffQn lin.v OUT– V Tp –vOUTvGSn V TnvSDp vSGp- V Tp IIIIIIVV TnvINvSGp VTp vDSn vGSn -V Tn-V Tp(V DD V Tp ) V DDV DDV DDIQp sat.vINV TnClif Fonstad, 11/3/09Qp lin.Qn sat.V(V DD V Tp ) V DDvINTransistor operating conditionin each -offLecture 15 - Slide 5
CMOS: transfer characteristic calculation, cont.Region I:#VDD " vOUT ) &(iDn 0 and iDp K p %VDD " v IN " VTp "((VDD " vOUT )2 'so iDn iDp ) vOUT VDDRegion II:!#vOUT &iDn K n %v IN " VTn "vOUT 2 ('so iDn iDp ) vOUT 0V DDand iDp 0vOUTvGSn V TnvSGp VTp V DDI!vSDp vSGp- V Tp IIQpvDSn vGSn -V TnIII v IN–Qn v OUT V Tp IV–V TnClif Fonstad, 11/3/09V(V DD - V Tp ) V DDvINLecture 15 - Slide 6
CMOS: transfer characteristic calculation, cont.Region III:iDn Kn2[ v IN " VTn ]2soiDn iDp# v IN[]2KpV DD -v IN " VTp2VDD " VTp VTn K n K p . To achieve symmetry we make1 K n K pandiDp K n K p , and VTp VTn . With this : v IN V DD!V DDQp v INQn– V DD /2 V Tp IvSDp vSGp- V Tp IIIIIvDSn vGSn -V TnIVVv OUT–V DD /2-V Tn V Tp Regions II and IV:Parabolic segments connectingthe three straight segments.Clif Fonstad, 11/3/09VDDVVand DD " VTn vOUT DD VTp222vOUTvSGp VTp vGSn V TnV TnV DD /2 (V DD - V DD V Tp )vINLecture 15 - Slide 7
CMOS: transfer characteristic calculation, cont.Complete characteristic so far:V DDV DD(V DD/2-V Tp)KpV Tp v IN–V OUT KnV Tn v OUTV DD/2(V DD/2-V Tn)-V Tp–V TnV DD/2 (V DD V DDV Tp )V INNOTE: We design CMOS inverters to have Kn Kp and VTn -VTpto obtain the optimum symmetrical characteristic.Clif Fonstad, 11/3/09Lecture 15 - Slide 8
CMOS: transfer characteristic calculation, cont.vOUTOur calculation says that thetransfer characteristic isvertical in Region III.V DDWe know it must have someslope, but what is it?To see, calculate the smallsignal gain about the biaspoint: VIN VOUT VDD/2-V TpV TnBegin with the small signal model:V DDQpK p !pV TpspV DD/2 (V DD - V DD V Tp )vINsp-v gsp v ingp gmp v gspgopdpgn V DD/2 v inQn–Clif Fonstad, 11/3/09 Kn !n V DD/2 v out v inV Tn– v gsn v insndn v outgmnv gsngonsnLecture 15 - Slide 9
CMOS: transfer characteristic calculation, cont.Redrawing the circuit we getgn ,gp v in v gsn v gsp--dn ,dpgmnv ingmp v ingongopsn ,sp v out- s ,sn pfrom which we see immediately#vAv " OUT#v INQgmn gmp ][v out v in[gon gop ]In Lecture 13 we learned how to write the conductances in termsof the bias point asgmn ! 2K n IDn ,gmp 2K p IDp gmn ,gon "n IDn ,gop " p IDp " p IDnwhich will enable us to express the gain in terms of the biaspoint, IDn ( IDp ), and MOSFET parameters!Av "Clif Fonstad, 11/3/09#vOUT#v IN Q2 2K n IDn2 2K n [%n % p ]IDn [%n % p ] IDnLecture 15 - Slide 10
CMOS: transfer characteristic calculation, cont.vOUTReturning to the transfer characteristic,we see that the slope in Region III isnot infinite, but is instead:#vAv " OUT#v INg[ [gmnQon gmp ]V DDV DD/2 gop ]-V TpvOUT!Final comment: A quick andeasy way to approximate thetransfer characteristic of aCMOS gate is to simply drawthe three straight line portionsin Regions I, III, and V:AvV TnV DDV DD/2AvV DD/2Clif Fonstad, 11/3/09V DD/2 (V DD - V DD V Tp )vINvINV DDLecture 15 - Slide 11
CMOS: switching speed; minimum cycle timeThe load capacitance: CL Assume to be linear Is proportional to MOSFET gate area In channel: µe 2µh so to have Kn Kp we must have Wp/Lp 2Wn/LnTypically Ln Lp Lmin and Wn Wmin, so we also have Wp 2Wmin***CL " n [W n Ln W p L p ]Cox n [W min Lmin 2W min Lmin ]Cox 3nW min Lmin CoxCharging cycle: vIN: HI to LO; Qn off, Qp on; vOUT: LO to HI! Assume charged by constant iD,satiCh arg e "iDp[Kp#VDD " VTp2]2 Kn2[VDD " VTn ]2QpqCh arg e CLVDD Ch arg eqCh arg e2CLVDD iCh arg e K n [VDD " VTn ] 2 Clif Fonstad, 11/3/09*6nW min Lmin CoxVDDW min2*µe CoxV"V[ DD Tn ]Lmin v IN6nL2minVDD 2µe [VDD " VTn ]V DD– QnCLv OUT–Lecture 15 - Slide 12
CMOS: switching speed; minimum cycle time, cont.Discharging cycle: vIN: LO to HI; Qn on, Qp off; vOUT: HI to LO Assume discharged by constant iD,satV DDKn2iDisch arg e iDn "[VDD # VTn ]2QpqDisch arg e CLVDD Disch arg eqDisch arg e2CLVDD iDisch arg e K n [VDD # VTn ] 2 *6nW min Lmin CoxVDDW min2*µe CoxV#V[ DD Tn ]LminMinimum cycle time: v IN6nL2minVDDµe [VDD # VTn ]vIN: LO to HI to LO;" Min.Cycle " Ch arg e " Disch arg e!Clif Fonstad, 11/3/09!– QnCLv OUT–2vOUT: HI to LO to HI12nL2minVDD 2µe [VDD # VTn ]Lecture 15 - Slide 13
CMOS: switching speed; minimum cycle time, cont.Discharging and Charging times:What do the expressions tell us? We have" Min Cycle12nL2minVDD 2µe [VDD # VTn ]This can be written as:!" Min Cycle 12nVDDLmin (VDD # VTn ) µe (VDD # VTn ) LminThe last term is the channel transit time:!LminLminL min Ch Transitµe (VDD " VTn ) Lminµe #Chse,ChThus the gate delay is a multiple of the channel transit time:!Clif Fonstad, 11/3/09!" Min Cycle 12nVDD" Channel Transit n' " Channel Transit(VDD # VTn )Lecture 15 - Slide 14
CMOS: power dissipation - total and per unit areaAverage power dissipationAll dynamic2*2Pdyn,ave E Dissipated per cycle f CLVDD 3nW min Lmin CoxVDDfPower at maximum data rateMaximum f will be 1/τGate Delay Min.!Pdyn @ f max *ox2DD3nW min Lmin C V" Min.Cycle µe [VDD VTn ]*2 3nW min Lmin CoxVDD #12nL2minVDD21 W min2*µe CoxVDD [VDD VTn ]4 LminPower density at maximum data rateAssume that the area per inverter is proportional to WminLmin!PDdyn @ f max Clif Fonstad, 11/3/09!Pdyn @ f maxInverterArea"Pdyn @ f maxW min Lmin*µe CoxVDD [VDD # VTn ] L2min2Lecture 15 - Slide 15
CMOS: design for high speedMaximum data rateProportional to 1/τMin Cycle" Min.Cycle " Ch arg e " Disch arg e 12nL2minVDDµe [VDD # VTn ]2Implies we should reduce Lmin and increase VDD.Note: As we reduce Lmin we must also reduce tox, but tox doesn'tenter directly in fmax so it doesn't impact us here!Power density at maximum data rateAssume that the area per inverter is proportional to WminLminPDdyn @ f max "!Clif Fonstad, 11/3/09Pdyn @ f maxW min Lminµe#oxVDD [VDD VTn ] t ox L2min2Shows us that PD increases very quickly as we reduce Lminunless we also reduce VDD (which will also reduce fmax).Note: Now tox does appear in the expression, so the rate of increasewith decreasing Lmin is even greater because tox must be reducedalong with L.How do we make fmax larger without melting the silicon?By following CMOS scaling rules - the topic of Lecture 16.Lecture 15 - Slide 16
CMOS: velocity saturationSanity checkCMOS gate lengths are now under 0.1 µm (100 nm). The electric fieldin the channel can be very high: Ey 104 V/cm when vDS 0.1 V.Clearly the velocity of the electrons and holes in the channel willbe saturated at even low values of vDS!What does this mean for the device and inverter characteristics?Clif Fonstad, 11/3/09Lecture 15 - Slide 17
CMOS: velocity saturation, cont.Models for velocity saturation*Two useful models are illustrated below. We'll use Model A today.Model AModel BModel Asy (E y ) µe E y if E y " E crit µe E crit # ssat if E y E critClif Fonstad, 11/3/09!µe E ysy (E y ) Ey1 E critModel B* See pp 281ff and 307ff in course text.Lecture 15 - Slide 18
CMOS: velocity saturation, cont.Drain current: iD(vGS,vDS,vBS)With Model A*, the low field iD model, s µE, holds for increasing vDSuntil the velocity of the electrons at some point in the channelreaches ssat (this will happen at the drain end). When this happensthe current saturates, and does not increase further for larger vDS.iDEcrLClif Fonstad, 11/3/09vDS* Model A: sy (E y ) µe E y µe E crit # ssatifE y " E critifE y E critLecture 15 - Slide 19
!CMOS: velocity saturation, cont.If the channel length, L, is sufficiently small we can simplify themodel even further because the carrier velocity will saturate atsuch a small vDS that for vDS EcritL the inversion layer will beuniform and all the carriers will be drifting at their saturationvelocity. In this situation (the saturation region) we will have:*iD (vGS ,v DS ,v BS ) " #W qN (vGS ,v BS ) ssat W ssat Cox[vGS # VT (v BS )]!For smaller vDS, prior to the onset of velocity saturation, the linearregion model we had earlier will hold. The entire characteristic,neglecting the vDS/2 factor in the linear region expression, is%0''*iD (vGS ,v DS ,v BS ) " & W ssat Cox[vGS # VT (v BS )]'W*'( µe Cox [vGS # VT (v BS )]v DSLfor(vGS # VT ) 0 v DSfor 0 (vGS # VT ), crit L v DSfor 0 (vGS # VT ), v DS crit LNote that the current in saturation increases linearly with (vGS - VT),rather than as its square like it did then the gate was longer.Clif Fonstad, 11/3/09Lecture 15 - Slide 20
CMOS: velocity saturation, cont.This simple model for the output characteristics of a very shortchannel MOSFET (plotted below) provides us an easy way tounderstand the impact of velocity saturation on MOSFET andCMOS inverter performance.iDvDSEcritLNote first that in the forward active region where vDS EcritL,the curves in the output family are evenly spaced, indicatinga constant gm:*gm " #iD #vGS Q W ssat CoxClif Fonstad, 11/3/09Lecture 15 - Slide 21
CMOS: velocity saturation, cont.Charge/discharge cycle and gate delay:The charge and discharge currents, charges, and times are now:*iDisch arg e iCh arg e W min ssat Cox(VDD " VTn )*qDisch arg e qCh arg e CLVDD 3W min Lmin CoxVDD# Disch arg e # Ch arg e*qDisch arg e3W min Lmin CoxVDD3nLminVDD *iDisch arg e W min ssat Cox (VDD " VTn ) ssat (VDD " VTn )CMOS minimum cycle time and power density at fmax:!" Min.Cycle " Ch arg e " Disch arg e " Min.Cycle #!!6 n LminVDDssat [VDD # VTn ]LminVDD n' " ChanTransitssat [VDD VTn ]Note: " ChanTransit PDdyn @ f max "!Lssatssat #oxVDD [VDD VTn ]t ox LminLessons: Still gain by reducing L, but not as quickly.Scaling of both dimensions and voltage is still required.Channel transit time, Lmin/ssat, still rules!Clif Fonstad, 11/3/09!Lecture 15 - Slide 22
MOSFETs: LEC w. velocity saturationSmall signal linear equivalent circuit: gm and Cgs changeCgdgdgm " Cgsv gs-gmv gsgos,bs,b#iD#vGS* W ssat CoxQ*Cgs W L CoxOne final model observation: Insight on gmWe in general want gm as large! as possible. To see another wayto think about this is to note that gm can be related to τCh-Transit:No velocitysaturationFull velocitysaturationgm*#W'W L Cox*%% µe Cox (vGS " VT ) 2%CgsLL µe (vGS " VT ) % *(*W L Cox Ch Transit*%%W ssat Cox %&%)L ssatCgs is a measure of how much channel charge we are controlling,and 1/τCh-tr is a measure of how fast it moves through the device.We'd like both to be large numbers.!Clif Fonstad, 11/3/09Lecture 15 - Slide 23
6.012 - Microelectronic Devices and CircuitsLecture 15 - Digital Circuits: CMOS - SummaryV CMOSDDTransfer characteristic: symmetricVLO 0, VHI VDD, ION 0NML NMH implies Kn Kp, VTp VTn VTLn Lp Lmin, Wp (µe/µh)WnGate delay expressions v INv OUT––τLO-HI τHI-LO 2VDDCL/Kn(VDD - VT)2Gate delay (GD) τLO-HI τHI-LO 4VDDCL/Kn(VDD - VT)2If CL n(WnLn WpLp)Cox* 3n WnLminCox*(Assumes µe 2µh)then GD 12 n Lmin2 VDD/ µn(VDD - VT)2(Motivation for reducing Lmin)Power and speed-power productPave f CLVDD 2Pdyn@ fmax CLVDD2/GD KnVDD (VDD - VT)2/4(Motivation for reducing VDD) Velocity SaturationGate delay; Power and speed-power product:Scales as 1/Lmin, rather than (1/Lmin)2Clif Fonstad, 11/3/09Lecture 15 - Slide 24
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6.012 - Microelectronic Devices and Circuits Lecture 15 - Digital Circuits: CMOS - Outline Announcements . One supplemental reading on Stellar Exam 2 - Thursday night, Nov. 5, 7:30-9:30 Review - Inverter performance metrics Transfer characteristic: logic levels and noise margins. Power: P. 2) ave, static P. ave, dynamic ( I. ON. V .
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