CPE 323 Introduction To Embedded Computer Systems: DMA Controller, LCD .

CPE 323 Introduction to EmbeddedComputer Systems:DMA Controller, LCD ControllerInstructor: Dr Aleksandar MilenkovicLecture Notes

Outline MSP430: System ArchitectureDMA ControllerLCD ControllerCPE 3232

DMA Controller Introduction Direct memory access (DMA) controllertransfers data from one address to anotherwithout CPU intervention, across the entire address range. Move data from the ADC12 conversion memory to RAMMove data from RAM to DAC12Devices that contain a DMA controller may have one, two, or threeDMA channels availableUsing the DMA controller Can increase the throughput of peripheral modulesCan reduce system power consumptionby allowing the CPU to remain in a low-power modewithout having to awaken to move data to or from a peripheralCPE 3233

MSP430 DMA Features Up to three independent transfer channelsConfigurable DMA channel prioritiesRequires only two MCLK clock cycles per transferByte or word and mixed byte/word transfer capabilityBlock sizes up to 65535 bytes or wordsConfigurable transfer trigger selectionsSelectable edge or level-triggered transferFour addressing modesSingle, block, or burst-block transfer modes Configured from software CPE 3234

DMA Block DiagramCPE 3235

DMA Addressing Modes Configured with the DMASRCINCRx and DMADSTINCRx control bits DMASRCINCRx/ DMADSTINCRx bits select if the source/destination address isincremented, decremented, or unchanged after each transferTransfers may be byte-to-byte, word-to-word, byte-to-word, or word-to-byte Word-to-byte: only the lower byte of the source-word is transferredByte-to-word: the upper byte of the destination-word is cleared when the transferoccursCPE 3236

DMA Transfer Modes Single/Repeated single modes:each byte/word transfer requiresa separate triggerBlock/Repeated block modes:a transfer of a complete block ofdata occurs after one trigger CPU is halted until the completeblock has been transferredBurst-block/Repeated burst-blockmodes: transfers are blocktransfers with CPU activityinterleaved. CPU executes 2 MCLK cyclesafter every four byte/wordtransfers of the block resulting in20% CPU execution capacityCPE 3237

DMA Trigger Operation DMAxTSELx bitsselect triggerEdge-sensitive orlevel-sensitiveCPE 3238

DMA Trigger Operation (cont’d)CPE 3239

DMA Channel Priorities Default DMA channel priorities are DMA0 DMA1 DMA2 Transfers in progress are not halted if a higher prioritychannel is triggered If two or three triggers happen simultaneously or are pending,the channel with the highest priority completes its transfer(single, block or burst-block transfer) first, then the secondpriority channel, then the third priority channel.The higher priority channel waits until the transfer in progresscompletes before startingDMA channel priorities are configurable with theROUNDROBIN bit (see below)CPE 32310

DMA Transfer Cycle Times DMA requires 1 or 2 MCLK ccto synchronize before eachsingle transfer or completeblock or burst-block transferEach byte/word transferrequires 2 MCLK aftersynchronization, and one cycleof wait time after the transferDMA cycle time is dependenton the MSP430 operatingmode and clock system setup(use MCLK) CPE 323If the MCLK source is active, but theCPU is off, the DMA controller will usethe MCLK source for each transfer,without re-enabling the CPU.If the MCLK source is off, the DMAcontroller will temporarily restartMCLK, sourced with DCOCLK, for thesingle transfer or complete block orburst-block transferThe CPU remains off, and after thetransfer completes, MCLK is turnedoff.11

DMA and Interrupts DMA transfers are not interruptible by system interrupts. System interrupt service routines are interrupted byDMA transfers System interrupts remain pending until the completion of thetransferNMI interrupts can interrupt the DMA controller if the ENNMI bitis setIf an interrupt service routine or other routine must execute withno interruptions, the DMA controller should be disabled prior toexecuting the routineEach DMA channel has its own DMAIFG flag Each DMAIFG flag is set in any mode, when the correspondingDMAxSZ register counts to zero. If the corresponding DMAIEand GIE bits are set, an interrupt request is generatedCPE 32312

DMA and Other Devices USCI B I2C ModuleADC12DAC12Writing to FlashCPE 32313

LCD Controller Liquid Crystal Display (LCD) controller Included in several devices of the MSP430 families (’3xx and ’4xx)Allows a rapid and simple way to interface with the programLCD controller commands the LCD panels generating voltagesignals to the segments. It supports static, and multiplex rates up to4 (2 mux, 3 mux and 4 mux) LCD panelsFeatures Display memoryAutomatic signal generationConfigurable frame frequencyBlinking capabilitySupport for 4 types of LCDs: Static2-mux, 1/2 bias3-mux, 1/3 bias4-mux, 1/3 biasCPE 32314

LCD Controller Block DiagramCPE 32315

LCD Memory Map Each memory bitcorresponds to one LCDsegment, or is not used,depending on the mode.To turn on an LCD segment,its corresponding memorybit is setCPE 32316

LCD Controller Operation LCD controller supports blinking The LCDSON bit is ANDed with each segment’s memory bit. When LCDSON 1, each segment is on or off according to its bitvalueWhen LCDSON 0, each LCD segment is offTiming generation Uses the fLCD signal from the Basic Timer1 to generate thetiming for common and segment lines Proper frequency fLCD depends on the LCD’s requirement forframing frequency and LCD multiplex rate.See the Basic Timer1 chapter for more information on configuringthe fLCD frequencyCPE 32317

LCD Controller Operation LCD voltage generation Voltages required for the LCD signals are supplied externally topins R33, R23, R13, and R03Using an equally weighted resistor divider ladder between thesepins establishes the analog voltages as shown in Table 24 1The resistor value R is typically 680 k Values of R from 100k to 1M can be used depending on LCDrequirements.R33 is a switched-VCC output. This allows the power to theresistor ladder to be turned off eliminating current consumptionwhen the LCD is not used.CPE 32318

Static Mode Each MSP430 segment pindrives one LCD segmentOne common line, COM0, isused.CPE 32319

Static LCDExampleCPE 32320

Static Mode Software ExampleCPE 32321

2-MUX Mode Each MSP430segment pin drivestwo LCD segmentsTwo common lines,COM0 and COM1,are used2-mux examplewaverformsa COM1-SP1b COM1-SP2c COM1-SP3d COM0-SP3e COM0-SP4f COM0-SP1g COM1-SP4h COM0-SP2CPE 32322

2-MUX LCDExampleCPE 32323

2-MUX Software ExampleCPE 32324

3-MUX Mode Waverforms Each MSP430segment pin drivesthree LCD segmentsThree common lines,COM0 and COM1, andCOM2 are used3-mux examplewaverformsCPE 32325

3-MUX LCDExampleCPE 32326

3-MUX SoftwareExampleCPE 32327

4-MUX Mode Waverforms Each MSP430segment pin drives fourLCD segmentsFour common lines,COM0, COM1, COM2,and COM3 are used4-mux examplewaverformsCPE 32328

4-MUX LCDExampleCPE 32329

4-MUX Software ExampleCPE 32330

LCD Control RegistersCPE 32331

LCD Control RegisterCPE 32332

DRFG4618 LCD InterfaceCPE 32333

Softbaugh LCD SBLCDA4:Segment DescriptionSBLCDA4 DisplayCPE 32334

CPE 323 3 DMA Controller Introduction Direct memory access (DMA) controller transfers data from one address to another without CPU intervention, across the entire address range. Move data from the ADC12 conversion memory to RAM Move data from RAM to DAC12 Devices that contain a DMA controller may have one, two, or three DMA channels available