ENGN3227: Analogue Electronics Project Voltage To Frequency Converter

ENGN3227: Analogue Electronics, By Group TA2needed to simply invert the output. The inverting circuit is simply an inverting amplifier, where the gain isgiven by,Vout RfRi3-4VinObviously the resistance ratio for the inverting amplifier,RfRi 1 . An additional design improvement would beto simply alter the inverting amplifier to be a active low pass filter by adding a capacitance across R f . Thiswould reduce any noise at the input to the AD650, considering that the input to the AD650 is very lowfrequency and can be considered to be approximately DC (refer to implementation).3.1.3AD650A voltage-to-frequency converter is (Figure 3-3) a device that converts an analog voltage on the input to a pulsesignal with a frequency that is directly proportional to the amplitude of the input voltage. There are severalways to implement a V/F converter (Floyd, Buchla, pp 740-748). The AD650 is a particular implementation ofa relaxation oscillator. Figure 3-3 shows a simplified diagram of an AD650 V/F converter. It consists of anintegrator, a comparator, a one-shot, a current source, and an electronic switch. The input resistor Rin, theintegration capacitor Cint, and the one-shot timing capacitor Cos are components whose values are selected basedon desired performance.Figure 3-3 A basic voltage-to-frequency converter.The basic operation of the V/F converter in Figure 3-4 is as follows. A positive input voltage produces an inputcurrent (Iin Vin/Rin) which charges the capacitor Cint, as indicated in Figure 3-4(a). During this integrator outputvoltage is a downward tramp, as shown. When the integrator output voltage reaches zero, the comparatortriggers the one-shot. The one-shot produces a pulse with a fixed width, tos, that switches the 1mA currentsource to the input of the integrator and initiates the reset mode.7

ENGN3227: Analogue Electronics, By Group TA2Figure 3-4 (Floyd, Buchla, pp 740-748)During the reset mode, current through the capacitor is in the opposite direction from the integrate mode, asindicated in Figure 3-4(b). This produces an upward ramp on the integrator output as indicated. After the oneshot times out, the current source is switched back to the integrator output, initializing another integrate modeand the cycle repeats.If the input voltage is held constant, the output waveform of the integrator is as shown in Figure 3-5, where theamplitude and the integrate time remain constant. The final output of the V/F converter is taken off the oneshot, as indicated in Figure 3-5. As long as the input voltage is constant, the output pulse stream has a constantfrequency. An increase in the input voltage, Vin , causes the input current, I in , to increase. In the basicrelationship IC (VC / t )C , the term VC / t is the slope of the capacitor voltage. If the current increases, VC / t alsoincreases since C is constant. As applied to the V/F converter, this means that if the input current ( I in )increases, then the slope of the integrator output during the integrate mode will also increase and reduce theperiod of the final output voltage. Also, during the reset mode, the opposite current through the capacitor, 1mAI in , is smaller, thus decreasing the slope of the upward ramp and reducing the amplitude of the integrator outputvoltage.Figure 3-5 (Floyd, Buchla, pp 740-748)8

ENGN3227: Analogue Electronics, By Group TA2The AD650 is an example of a V/F converter very similar to the basic device that was just discussed. The maindifferences in the AD650 are the output transistor and the comparator threshold voltage of -0.6 V instead ofground. The values of the external components of the AD650 determine the operating characteristics of thedevice. The AD650 circuit was designed to operate from 1kHz-1Mhz. Knowing that the output voltage of theDAC stage is within the range of 0.1-10 V, means that the AD650 needs to be calibrated such that a 0.1V step atthe input, results in a change in frequency of 1kHz at the output. The crucial characteristic about the AD650 isthat it has a linear scale for voltage to frequency. The values of the external components determine the operatingcharacteristics of the device. The pulse width of the one-shot output is set by the following formula:tos Cos (6.8 103 s / F ) 3 10 7 s3-5During the reset interval, the integrator output voltage increases by an amount expressed as,ΔV (1mA I in )tosCint3-6The duration of the integrate interval when the integrator output is sloping downward istint tintt (1mA I in )/CintΔV osI in / CintI in /Cint3-7 1mA 1 tos I in The period of a full cycle consists of the reset interval plus the integrate interval. 1mA 1mA T tos tint tos 1 tos tosI in I in 3-8Therefore, the output frequency can be expressed asf The equation ( f I intos (1mA )I intos (1mA )3-93-9) shows that the frequency is directly proportional to the inputcurrent; and since Iin Vin / Rin , it is also directly proportional to the input voltage and inversely proportional tothe input resistance. Knowing that the maximum frequency output is 1MHz, the duty cycle of the output at1MHz was specified to be 50% nominally. To maintain as close to 50% duty cycle at 1MHz, the closestpossible value for Cos 47pF was chosen, resulting in tos 0.62 μs . Consequently the duty cycle at 1 MHz is62%. Now solving for the full scale input current to maintain 1Mhz output, I in f tos (1mA) 0.62mA . Solvingfor the value of Rin ,Rin Vin / I in 10V / 0.62mA 16.13kΩAn additional trim pot was used in series with Rin to allow for precise calibrationThe Table 3-1 shows the final external components chosen for the AD650 circuit. Figure 3-6 shows thedesigned AD650 circuit with external components.ComponentRinCintCosValue16.2 kΩ2.2 nF47 pFTable 3-19

ENGN3227: Analogue Electronics, By Group TA2Figure 3-63.1.4Frequency dividers and multiplexersFrequency dividers were used to achieve the specified dynamic range 1.00Hz-999KHz. A divide by 1000frequency divider was used to determine the range Hz/KHz. The decimal point decoder logic along with the twodivide by 10 frequency dividers were used to convert the output of the AD650 to the correct range. The FigureA.1 of appendix A, shows the frequency dividers used in conjunction with a number of multiplexers.3.1.5Output level controlThe output of the frequency dividers was passed through a high-precision op-amp circuit which is shown inFigure A.1 of appendix A. The LM318 is a high-speed/precision op-amp needed to clean the pulse widthoutput, and additionally a capacitor was connected in the feedback to provide filtering at 1 MHz. A 10kΩpotentiometer was used to allow the output amplitude to be decreased from 5V to 0V. Note also that the outputof the op-amp is inverted.4ImplementationThe input interface consisted of several individual circuits to take the input from the keypad and process it forthe rest of the circuit. Initially, the only parts of the keypad interface that were bread boarded were the keypadand the BCD to binary decoder. Several problems were encountered during this implementation and the designwas revised accordingly. The output of the decoder was a 4 bit binary number. The decoded BCD has thecorresponding value to the key pressed. At this stage, none of the other keypad circuits had been successfullyimplemented, mainly because of the time required to get the decoder to work.As an alternative to the keypad interface, an input consisting of three BCD DIL rotary switches was developed.There was no available documentation for the rotary switches. As a precautionary measure, one of the switcheswas used as the test dummy. Before connecting the switch to any other components, it was tested by applying 5V, -5V and 0V inputs and observing the output. After several attempts, it was found that each switch has agrounded input and a four bit output. The digits 1-9 are output with floating values for the “low” bits and0(ground) is “high”. These input digits are to be displayed on the LEDs, but the LEDs require positive logic.To solve this problem, all of the outputs for the three rotary switches were connected to inverters, whoseoutputs are active high.10

ENGN3227: Analogue Electronics, By Group TA2In the process of bread boarding the frequency dividers at the output of the AD650, some of the outputs wereoverloaded. Initially it seemed as though the outputs on two of the decade counters no longer functioned,though after waiting a week and then performing several tests with the oscilloscope, no damage could be found.This was presumably due to the effect of proprietary circuit protection inside the IC cutting the outputs due tocurrent overload and then re-enabling them at a later time.The high precision, high speed op-amp at the output of the entire circuit was damaged by static. It wasconnected as an inverting op-amp with a low pass filer in the feedback network. The op-amp was found to benon-operational after it was first hooked up, indicating that it was already damaged, most likely by static. Itwas replaced and included in the PCB design. However, the new op-amp was overheated due to a mix up in thepower rails on the PCB. As a result of this, it could not be included in the final implementation.A voltage reference is used to set the input to the DACs. The required reference for the DACs is 10V. To setthis reference voltage, a potentiometer was connected to pin 1 of the voltage reference. This allowed the tuningof the voltage reference to a constant 10V.To provide a full scale output of 10V, the summing amplifier at the output of the DACs had to be calibrated.This was done by tuning the pots leading to the inverting input of the op-amp. Both 10kΩ and 500Ω variableresistors were used to set the full scale output to 10V. The current to voltage converters at the output of theDACs also had variable resistors in the feedback loop, to make the feedback resistance 5kΩ. These wereomitted from the design, because this resistance is accounted for by the pots at the input of the summingamplifier, as discussed above.As discussed in the text book (Floyd, Buchla, pp 744), the frequency output of the AD650 is proportional to theinput current. Therefore it is also proportional to the input resistance. To provide a fast method of testing theAD650, a potentiometer was connected to the input, rather than a single resistance. This allows the inputcurrent and voltage to the AD650 to be varied, and hence allows the frequency of the output to be controlled.To make sure that the AD650 was not outputting a frequency above 0Hz when an input of 0V was keyed in,another potentiometer was used at the offset inputs (pins 13 and 14) of the AD650. This was to allowadjustment of the offset, if there were any discrepancies in the output frequencies.It was also found that there was a 400KHZ 1Vpp noise waveform appearing on the op-amps located on theAD650 PCB. This noise was independent of the AD650 frequency, suggesting the oscillation was originatingfrom some other source on the board. It was attempted to minimise this noise by implementing a low-passactive filter, however this did not reduce the signal by the theoretical amount. It was decided that the 400KHZnoise oscillation was the result of feedback amongst the many op-amps along with the lack of RF design in thePCBs.After the bread boarded implementation of the voltage to frequency converter was tested, confirmed (simulated)and completed, the next stage in the project was to transfer the design to a printed circuit board. The circuit wasinitially designed using Eagle software. This was convenient because Eagle has a PCB design tool. The onlyavailable Eagle software was trial ware. This meant that the PCB designs could not be bigger than about 10cmx 15cm.To transfer the voltage to frequency converter to a PCB implementation, it was split up into three PCB boards.The three schematics for which were used to design the PCBs are given in appendix A as figures A.1, A.2 andA.3. The corresponding PCB designs which followed are also given in appendix A as figures A.4, A.5 and A.6Before the components were soldered onto the PCBs, it was noted that one of the PCBs was incorrectlymanufactured. This was due to a fault in the original design, where a track was misaligned, connecting it to the11

ENGN3227: Analogue Electronics, By Group TA2wrong pin. The ground track intersected with the output of the first DACs, see figure 2-4. This was easilyfixed by breaking the unwanted track.5ResultsTo test the V/F converter the following steps were carried out,1.Calibration process described in Sections 4.2.Before any steps the output op-amp stage was removed (as described in Section 4).3.Set the 3 BCD input (rotary switch’s) to 10. Set the range select to Hz and the decimal pointselector set to two digits.4.Measured the frequency output of the AD650 (pin 8). The output waveform is recorded in theFigure 5-1.Figure 5-1 input 10, fout 0.1 Hz output, duty cycle 20%The voltage output shown above is 0.1 Hz frequency, as expected. This was the minimum attainable outputfrequency due to limitations in the accuracy of the AD650. The main problem encountered was a significant400KHz noise component in the output of the DAC stages, especially the inverter output (see Section 3.1.2).The noise was measured to have a pk-pk value in the order of 1 Volt. As a result the output frequency of theAD650 is continuously changing, resulting in a clock jitter. As a consequence the V/F converter could only everbe calibrated to within 2 significant figures of frequency, reliably. Considering that frequency division is alinear operation the V/F converter is able to maintain 2 significant figures of accuracy, regardless of selectedfrequency.5.The BCD input was set to 250. The range select was set to kHz. Then the decimal place wasselected to be 0. The output at pin 8 of AD650 was measured. The output waveform was recordedand given in Figure 5-2.12

ENGN3227: Analogue Electronics, By Group TA2Figure 5-2 input 250, fout 251 kHz output, duty cycle 10%6.The output was measured again at the input pin (pin 2) of the CA3130 output op-amp. The outputwas recorded in the Figure 5-3Figure 5-3 input 250, fout 252.5 kHz outputNote that theoretically only the multiplexers and resistances are between the output of the AD650 and the inputto the op-amp. However the output waveform clearly exhibits the characteristics of a parallel capacitance toground. This illustrates one of the major problems of the V/F converter PCB layout design. Higher frequencyoutputs of the AD650 are effected by the internal (parasitic) capacitance of the PCB board. More careful designof the PCB, involving Radio Frequency issues need to be addressed in order to reliably operate the V/Fconverter at Radio Frequencies.7.The BCD input was set to 800. The range select was set to kHz. Then the decimal place wasselected to be 0. The output at pin 8 of AD650 was measured. The output waveform was recordedin Figure 5-4.13

ENGN3227: Analogue Electronics, By Group TA2Figure 5-4 input 800, fout 830 kHz outputNotice that the measured output frequency was inaccurate by a factor of 30 kHz. Thus this is outside thepractical operating range of the V/F converter. This effect could be attributed to the 400kHz noise component inthe AD650 input which may result in significant frequency offset at frequencies close to 400kHz. By furtherexperimentation we were able to find that the output of the AD650 became non-linear at frequencies higher than500 kHz. Therefore the practical operating range of the V/F converter was measured to be 500 kHz. Ourexperimental results showed that for frequencies less than 500kHz the V/F converter output was accurate towithin 2x(least significant figure). i.e. for the kHz range-2 kHz, for 0.1kHz range - 0.2kHz, 1Hz range - 2Hz,etc.One of the other main issues present was the lack of reliability of the PCB for high frequencies due to RFeffects. One good example was the resistor present at the output of the frequency dividers, on the frequencydivider side, the wave was square with minimal distortion. However, on the other side of the resistor a sawtoothwaveform was observed. This suggests that our resistors act as capacitors as well as resistors for higherfrequencies (around a few hundred KHz). To provide more reliable VCO function in this respect, the PCBneeds to be redesigned taking into account RF

accomplish a common goal. The analogue electronics project requires these attributes and acquaints students with the modern applications and implementation of analogue electronics. The project requires the use of ADC/DAC, op-amps or 555 timers and challenges students to produce a design at minimal cost.