Design And Verification Of AMBA APB Protocol - Ijcaonline

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International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Design and Verification of AMBA APB ProtocolShankarDipti GirdharNeeraj Kr. Shukla, Ph.DSchool of Engineering andTechnology,ITM University, Gurgaon, IndiaDepartment of EECEITM University, Gurgaon,IndiaDepartment of EECEITM University, Gurgaon, IndiaABSTRACTThe SoC (System on Chip) uses AMBA (AdvancedMicrocontroller Bus Architecture) as an on chip bus. APB(Advanced Peripheral Bus) is one of the components of theAMBA bus architecture. APB is low bandwidth and lowperformance bus used to connect the peripherals like UART,Keypad, Timer and other peripheral devices to the busarchitecture. This paper introduces the AMBA APB busarchitecture design. The design is created using the verilogHDL and is tested by a verilog testbench. This design isverified using UVM (Universal Verification Methodology).KeywordsAMBA, APB, SoC, UVM, Design, Verification.1. INTRODUCTIONIn system on a chip (SoC) design, Advanced MicrocontrollerBus Architecture (AMBA) is used as on chip bus. Earlier itwas used in the microcontroller devices but now it is widelyused in a large range of ASIC and SoC parts including theapplication processors used in modern portable mobiledevices like smartphones. AMBA is an open standard, on-chipinterconnect specification for the purpose of connecting andmanaging functional blocks in a System-on-Chip (SoC). It2. APB DESIGNhelps in right first time development of the multiprocessordesigns with large number of controllers and peripherals.As seen in the Figure.1, AMBA bus architecture consists ofthree components, namely Advanced High Performance Bus(AHB), Advanced System Bus (ASB), Advanced PeripheralBus (APB)[3]. AMBA AHB or ASB is high performance busand has higher bandwidth. So the components requiringhigher bandwidth like High Bandwidth on chip RAM, Highperformance ARM processor, High Bandwidth MemoryInterface and DMA bus master are connected to the AHB orASB. AMBA APB is low bandwidth and low performancebus. So, the components requiring lower bandwidth like theperipheral devices such as UART, Keypad, Timer and PIO(Peripheral Input Output) devices are connected to the APB.The bridge connects the high performance AHB or ASB busto the APB bus[4]. So, for APB the bridge acts as the masterand all the devices connected on the APB bus acts as theslave. The component on the high performance bus initiatesthe transactions and transfer them to the peripherals connectedon the APB. So, at a time the bridge is used forcommunication between the high performance bus and theperipheral devices.Fig 1: AMBA Bus Architecture[1]also be used to access the programmable control registers ofthe peripheral devices.The APB is the member of the AMBA 3 protocol familywhich implements a low cost interface which minimizes thepower consumption and reduces the interface complexity.Since APB has unpipelined protocol. Therefore, it interfacesto the low bandwidth peripherals that do not demand the highperformance of the pipelined bus interface. All the signaltransitions are associated with the rising edge of the clockwhich makes it simple to integrate APB peripherals into anydesign flow. APB can interface with the AMBA AHB-Liteand AMBA Advanced Extensible Interface(AXI). APB can2.1 APB Block DiagramThe Advanced peripheral bus (APB) is designed as per thedesign specification.[2]. The basic block diagram of theAMBA APB in figure.2 shows the basic interface signals.29

International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Fig 2: Basic block diagram of APB[2]The APB slave takes PCLK, PRESET, PSEL, PENABLE,PWRITE as input control signals and PADDR, PWDATA as32 bits inputs from the bridge and provides 32 bits PRDATAas output.Table 1. List of APB signalsSignalSignal NamePCLKClock signalPRESETnReset signalPADDR32 bit address busPSELxSelect signalPENABLEEnable signalPWRITEDirection signalPWDATA32 bit Write Data busPREADYReady signalPRDATA32 bits read data bus2.2 APB Operating StatesFigure.3 shows the basic state machine that representsoperation of the peripheral bus. There are three states namely,IDLE, SETUP and ACCESS stateFig 3: State Diagram[1]IDLE state is the default state in which no operation is beingperformed. The assertion of the PSEL signal indicates thebeginning of the SETUP phase. The bus enters into theSETUP phase when the data transfer is required. ThePWRITE, PADDR and PWDATA are also provided duringthis phase. The bus remains in the SETUP phase for one clockcycle and on the next rising edge of the clock, the bus willmove to the ACCESS state.The assertion of the PENABLE signal indicates the start ofthe ACCESS phase. All the control signals, address, and thedata signals remains stable during the transition from theSETUP phase to the ACCESS phase. In case of read operationthe PRDATA is present on the bus during this phase.PENABLE signal also remain high for one clock cycle. If nofurther data transfer is required, the bus will move the IDLEstate. But, if further data transfer is required then the bus willmove to the SETUP phase.2.3Write CycleDuring the write transfer operation, the PSEL, PWRITE,PADDR and PWDATA signals are asserted at the T1 clockedge which is called the SETUP cycle. At the next rising edgeof the clock T2, the PENABLE signal and PREADY signalare asserted. This is called the ACCESS cycle. At the clockedge T3, PENABLE signal is disabled and if further datatransfer is required, a high to low transition occurs on thePREADY signal.30

International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Fig 4: APB Write cycle[2]2.4 APB Read CycleDuring the read operation, the PSEL, PENABLE, PWRITE,PADDR signals are asserted at the clock edge T1 (SETUPcycle). At the clock edge T2, (ACCESS cycle), thePENABLE, PREADY are asserted and PRDATA is also readduring this phase.Fig 5: APB Read Cycle[2]3. SIMULATION RESULTS FOR THEDESIGNThe design and the testbench written in verilog[6] has beencompiled using ICARUS verilog. The results show the writeand read operation. It is evident from the figure that whenPWRITE 1, the address and data are written at the sameclock edge. When PWRITE 0, the address is sent on a givenclock edge and the data is read on the following clock edge.31

International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Fig 6: Simultation results for the design4. VERIFICATIONVerification is the most important part of the VLSI designflow. It aims to find out the bugs in the RTL (RegisterTransfer Level) design at an early stage so that it does notprove out destructive at the later stage in the design process.Around 70% of the time is consumed in the verificationprocess. So, it is the most time consuming process. Due to theincrease in number of transistors in the integrated circuit (IC),reducing feature size and improved design tools, thecomplexity of the IC has increased. This raises the probabilityof occurrence of bugs in the design. Hence, the need for theverification of the IC became necessary [7][9].Figure 8 shows the various UVM verification componentscreated to verify APB design.4.1 Sequence itemThe transactions are extended from the uvm sequence item.This component randomizes the address and data. The fieldautomation macros are applied to the data members of thisclass.4.2 SequencesA sequence is a series of transaction. In the sequence class,the users can create complex stimulus. These sequences canbe randomized, extended to create another sequence and canbe combined.4.3 SequencerUVM sequencer coordinates between the driver and sequence.It passes the transaction to the driver for execution and obtainsthe response from the driver. It also acts as an arbitrator formultiple sequences running in parallel.4.4 DriverDriver initiates the request for the next transaction and drivesit to the lower level components. It is created by extending theuvm driver.Fig 7: Position of RTL Verification in the VLSI DesignFlowUniversal Verification Methodology (UVM) is a standardverification methodology used to verify the RTL (RegisterTransfer Level) design. It consists of base class library codedin SystemVerilog[8]. The verification engineer can createdifferent verification components by extending these classes.Moreover, UVM provides many other useful verificationfeatures such as use of macros for implementing complexfunction, factory for object creation [8].4.5 Collector and MonitorThe collector extracts the signal information from the bus andconverts it into the transactions and passes it through theanalysis port to the monitor for further comparing.4.6 AgentThe agent instantiates the verification components driver,monitor, collector and sequencer. It also connects thesecomponents using TLM connections. The agent can have oneof the operating modes active or passive. In the active modeof operation, the agent instantiates driver, sequencer collectorand monitor whereas in the passive mode of operation onlymonitor and collector are instantiated and configured.32

International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Fig 8: UVM Verification components[10]4.7 Environment4.8 TestThe Environment class instantiates all the sub componentssuch as agents, driver, monitor etc. and configures them.The uvm test is extended from the uvm component. Differenttestcases can be generated for the given verificationenvironment5. SIMULATION RESULTS OF VERIFICATIONFig 9: Simulation results from write operation obtained after verification of APB33

International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Figure 9 shows the simulation results obtained by creatingverification environment. It is seen that in the simulationresults there are some additional signals like DIN, DOUT,ADDR WR, ADDR RD. These signals are of the memorywhich is connected to the APB bus.In figure 9, the data 000000aa is written to the memoryaddress 00000001 and in figure 10, the same data is read fromthe same memory location. During write operation in figure.9,the high signal on the PWRITE causes a WR signal of thememory to go high and the data which is applied toPWDATA port is sent to the memory through the DIN port ofthe memory. The address is applied to the PADDR port whichis sent to the ADDR WR port of the memory.During the read operation as shown in figure.10, when thePWRITE signal goes low, it causes RD signal of the memoryto go high and the address is applied to the PADDR portwhich is sent to the ADDR RD port of the memory. The dataobtained at the DOUT port of the memory is read at thePRDATA port.Figure 10: Simulation results for read operation obtained after verification of APBUVM report provides the results obtained after the simulationof UVM testbench. Figure 11 shows the UVM reportsummary generated after running all the UVM phases. TheUVM INFO in the UVM report summary in figure 11 showsthat there are thirty six information messages. The dataprovided by the UVM report summary ensures that design iserror free and does not produce any warnings or fatal errorsincetheUVM ERROR,UVM WARNINGandUVM FATAL is equal to zero.34

International Journal of Computer Applications (0975 – 8887)Volume 95– No.21, June 2014Fig 11: UVM Report Summary6. CONCLUSIONThis paper gives an overview of the AMBA bus architectureand discusses the APB bus in detail. The APB bus is designedusing the verilog HDL according to the specification and isverified using Universal Verification Methodology. Thesimulation results show that the data read from a particularmemory location is same as the data written to the givenmemory location. Hence, the design is functionally correct.The UVM report summary also ensures the functionalcorrectness of the design.The electronic system level model of the same design will becreated in the future since ESL is the requirement of the futurebecause of increasing design complexity. The ESL model ofthe APB design will be created using SystemC. Then thedesign will be verified using UVM testbench. The resultsobtained after the simulation will be compared with the resultsobtained in this paper.7. REFERENCES[1] ARM,“AMBA .IJCATM : www.ijcaonline.orgSpecificationOverview”,[2] ARM, “AMBA ] Akhilesh Kumar, Richa Sinha, “Design and Verificationanalysis of APB3 Protocol with Coverage,” IJAET, Nov2011.[4] Santhi Priya Sarekokku, K. Rajasekhar, “Design andImplementation of APB Bridge based on AMBA AXI4.0,” IJERT, Vol.1, Issue 9, Nov 2012.[5] UVM Reference Manual,[6] Samir Palnitkar, “Verilog HDL: A guide to DigitalDesign and Synthesis (2nd Edition), Pearson, 2008.[7] Chris Spear, “SystemVerilog for verification (2ndEdition): A guide to learning the testbench features,Springer, 2008.[8] URL:[9] Bergeron, “Writing testbenches using SystemVerilog,”Springer, 2009.[10] Vanessa R. Cooper, “Getting Started with UVM: ABeginner’sGuide,”Verilab,2013.35

International Journal of Computer Applications (0975 - 8887) Volume 95- No.21, June 2014 30 Fig 2: Basic block diagram of APB[2] The APB slave takes PCLK, PRESET, PSEL, PENABLE, PWRITE as input control signals and PADDR, PWDATA as 32 bits inputs from the bridge and provides 32 bits PRDATA as output. Table 1. List of APB signals

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