The Technology Roadmap - University Of California, San Diego
The Technology RoadmapECE 260B / CSE 241A Guest LectureAndrew B. KahngProfessor of CSE and ECE, UC San Diegoabk@ucsd.eduhttp://vlsicad.ucsd.edu/
Semiconductor Technology TrendsPerformanceIntegrationPowerCostFigures courtesy IntelAndrew B. Kahng, UCSD ECE 260B, January 21, 20102
What Drives Semiconductor Technology?Modern cellphone chip: 2 processors, modem,graphics and video engines, DSPs in 8mm x 8mmAndrew B. Kahng, UCSD ECE 260B, January 21, 20103
What Does the IC nce TranslationVoice Auto TranslationDolby-AC3MPEGWord RecognitionGraphics3D Graphics 10Mpps100Mpps2D GraphicsCommunicationSW Defined RadioVoIP ModemFace RecognitionRecognition ModemVoice Print RecognitionMoving Picture RecognitionFAXRequired performance for multimedia processing (GOPS: Giga Operations Per Sec)2007 ITRS SOC Consumer-Stationary Driver: 220 TFlops on a single chip by 2022Andrew B. Kahng, UCSD ECE 260B, January 21, 20104
How Is It Connected?SEMATECH Prototype BEOL (“back end of the line”) metal stack, 2000PassivationWireDielectricEtch Stop LayerGlobal (up to 5)ViaDielectric Capping LayerCopper Conductor withBarrier/Nucleation LayerIntermediate (up to 4)Local (2)Pre Metal DielectricTungsten Contact PlugAndrew B. Kahng, UCSD ECE 260B, January 21, 20105
How Is It Manufactured? Sub-wavelength optical lithographySlide courtesy of Numerical Technologies, Inc.Andrew B. Kahng, UCSD ECE 260B, January 21, 20106
(Mask Shapes Used in Lithography)Andrew B. Kahng, UCSD ECE 260B, January 21, 20107
Many Interesting Technology Trends Lithography Minimum feature size scales by 0.7x every three (two?) years Add another pair of layers: last generation’s chip thisgeneration’s module Interconnect delay doesn’t scale well Dominates system performance Coupling gets worse timing uncertainty and design guardband Multiple clock cycles needed to cross chip whether 3 or 15 not as important as “multiple” being 1 How does manufacturing process enter into picture? Lower-permittivity dielectrics organics to aerogels to air gaps Copper interconnects resistivity, reliability Planarization more layers are stackableAndrew B. Kahng, UCSD ECE 260B, January 21, 20108
Many Interesting Design Challenges Result Manufacturability (chip can't be built) antenna rulesminimum area rules for stacked viasCMP (chemical mechanical polishing) area fill ruleslayout corrections for optical proximity effects in subwavelengthlithography Signal integrity (chip fails timing constraints) crosstalk induced errors timing dependence on crosstalk IR drop on power supplies Reliability (chip fails in the field) electromigration on power supplies hot carrier effects on devices wire self-heating effects on clocks and signalsSlide courtesy of Dr. Lou Scheffer, CadenceAndrew B. Kahng, UCSD ECE 260B, January 21, 20109
SRC* Grand Challenges ( 2005)1. Extend CMOS to its ultimate limit2. Support continuation of Moore's Law by providing a knowledge base forCMOS replacement devices3. Enable Wireless/Telecomm systems by addressing technical barriers indesign, test, process, device and packaging technologies4. Create mixed-domain transistor and device interconnection technologies,architectures, and tools for future microsystems that mitigate thelimitations projected by ITRS5. Search for radical, cost effective post NGL patterning options6. Provide low-cost environmentally benign IC processes7. Increase factory capital utilization efficiency through operational modeling8. Provide design tools and techniques which enhance design productivityand reduce cost for correct, manufacturable and testable SOC's and SOP's9. Enable low power and low voltage solutions for mobile/battery conservingapplications through system and circuit design, test and packagingapproaches.10. Enable very low cost components11. Provide tools enabling rapid implementation of new system architectures* Semiconductor Research Corporation, which funds a largeportion of semiconductor-related U.S. academic research.My point: See the big picture!Andrew B. Kahng, UCSD ECE 260B, January 21, 201010
Today’s Agenda What is the semiconductor roadmap? Connections game: Why do we care? Aspects of the Design roadmap Aspects of the System Drivers roadmap and theOverall Roadmap Technology Characteristics(ORTCs) More Than MooreAndrew B. Kahng, UCSD ECE 260B, January 21, 201011
Background Have written the IC physical design roadmapsince 1996 Chair / co-chair of U.S. and International DesignTechnology Working Groups since 2000 Responsible for two chapters in theInternational Technology Roadmap forSemiconductors (ITRS), http://public.itrs.net/ Design chapter: roadmaps for the EDA industry System Drivers chapter: roadmaps for product classesthat consume high-value silicon and drivesemiconductor technologyAndrew B. Kahng, UCSD ECE 260B, January 21, 201012
What is the Semiconductor Roadmap? Something you need to read ! Enabling mechanism for Moore’s Law Synchronizes many industries to “clock” of technologynodes A Very Big Picture ! Lithography, Interconnect, Assembly and Packaging,Test, Design, Technology roadmap (not business roadmap) Structured as requirements potentialsolutions Highly complex and interconnected 1000 people worldwide produce new edition each oddnumbered year, and update in even Many contradictions (predict vs. require, etc.)Andrew B. Kahng, UCSD ECE 260B, January 21, 201013
Today’s Agenda What is the semiconductor roadmap? Connections game: Why do we care? Aspects of the Design roadmap Aspects of the System Drivers roadmap and theOverall Roadmap Technology Characteristics(ORTCs) More Than MooreAndrew B. Kahng, UCSD ECE 260B, January 21, 201014
Lithography Roadmap (January 2009)Year of Production2009201020112012201320142015DRAM ½ pitch (nm)52454036322825CD control (3 sigma) (nm) [B]5.44.74.23.73.32.92.6Contact in resist (nm)57504439353128Contact after etch (nm)5245403632282510.39.08.07.16.45.75.1FlashFlash ½ pitch (nm) (un-contacted poly)40363228252320CD control (3 sigma) (nm) [B]4.23.73.32.92.62.32.1Contact in resist (nm)44393531282522Contact after etch 3632282529352731242822251822172015Gate CD control (3 sigma) (nm) [B] **3.02.82.52.31.91.71.6Contact in resist (nm)64565044393531Contact after etch (nm)58514540363228Overlay [A] (3 sigma) (nm)2Chip size (mm )131110.08.98.07.16.3Maximum exposure field height (mm)2626262626262633333333333333Maximum field area printed by exposure tool (mm )Wafer site flatness at exposure step (nm) [C]85885885885885885885848423733292623Number of mask levels MPU35353535373737Wafer size (diameter, mm)300300300450450450450Overlay [A] (3 sigma) (nm)Overlay [A] (3 sigma) (nm)MPUMPU/ASIC Metal 1 (M1) ½ pitch (nm)MPU gate in resist (nm)MPU physical gate length (nm) *Maximum exposure field length (mm)2Andrew B. Kahng, UCSD ECE 260B, January 21, 201015
Double Patterning Lithography (DPL) DesiredpatternFirst MaskSecond MaskCombinedexposureAndrew B. Kahng, UCSD ECE 260B, January 21, 201016
DPL Layout Decompositiond1 td2 td1 d2 d3 tttd4 td3 td4 t Two features are assigned opposite colors if their spacing isless than the minimum coloring spacing t IF two features within minimum coloring spacing t cannot beassigned different colors THEN at least one feature is split into two or more parts Pattern split increases manufacturing cost, complexity Line ends corner rounding Overlay error and interference mismatch line edge errors tightoverlay control Optimization: minimize cost of layout decomposition Various “Graph Bipartization” engines from my group since 1998Andrew B. Kahng, UCSD ECE 260B, January 21, 201017
Example DPL Layout Decomposition Flow Layout fracturing Polygons rectangles Graph construction Conflict cycle (CC)detection Overlap lengthcomputation If there is a feasibledividing point nodesplitting Otherwise, report anunresolvable conflictcycle (uCC) Graph updating ILP based DPL colorassignmentLayout fracturingGraph constructionConflict cycle detectionConflictcycle?NoILPYesOverlap length computationOverlapmargin?NouCCYesNode splittingGraph updateAndrew B. Kahng, UCSD ECE 260B, January 21, 201018
Process Integration, Device Structures Roadmap(December 2009) – HIGH PERFORMANCEAndrew B. Kahng, UCSD ECE 260B, January 21, 201019
Process Integration, Device Structures Roadmap(December 2009) – HIGH PERFORMANCEAndrew B. Kahng, UCSD ECE 260B, January 21, 201020
Process Integration, Device Structures Roadmap(December 2009) – LOW STANDBY POWERAndrew B. Kahng, UCSD ECE 260B, January 21, 201021
Process Integration, Device Structures Roadmap(December 2009) – LOW OPERATING POWERAndrew B. Kahng, UCSD ECE 260B, January 21, 201022
Comments LSTP subthreshold leakage requirement of 50 pA/ mused to be 1 pA/ m in early 2000’s ! HP scaling of CV/I is now 13%/year, instead ofhistorical 17%/year, based on Design input that theextra speed wasn’t usable because of power limits HP, LSTP correspond to G and LP process flavorsfrom major foundries 2009 LOP roadmap increased VDD especially in longterm years; this is wrong from design and productviewpoint, and is likely to be corrected in 2010 LOP roadmap might also go away in light of previous commentAndrew B. Kahng, UCSD ECE 260B, January 21, 201023
Interconnect Roadmap (January 2009)Year of Production200920102011201220132014MPU/ASIC Metal 1 ½ Pitch (nm)(contacted)524540363228Number of metal levels (includes ground planes & passive 21.81.61.4Interlevel metal insulator – effective dielectric constant rlevel metal insulator – bulk dielectric constant er diffusion barrier and etch stop – bulk dielectric constant l 1 wiring pitch (nm)1049080726456Metal 1 A/R (for Cu)1.81.81.81.81.91.9Barrier/cladding thickness (for Cu Metal 1 wiring) (nm) [3]Cu thinning at minimum pitch due to erosion (nm), 10% height, 50% arealdensity, 500 µm square array3.73.32.92.62.42.1987665Conductor effective resistivity (µΩ cm) Cu Metal 1 wiring including effectof width-dependent scattering and a conformal barrier of thickness specifiedbelow3.804.084.304.534.835.20Interconnect RC delay (ps) for 1 mm Cu Metal 1 wire, assumes widthdependent scattering and a conformal barrier of thickness specified below146521002801349145556405Line length (μm) where 25% of switching voltage is induced on victimMetal 1 wire by crosstalk [4]898278645749Total Metal 1 resistance variability due to CD erosion and scattering (%)303031323231Intermediate wiring pitch (nm)10490807264562Total interconnect length (m/cm ) – Metal 1 and five intermediate levels,active wiring only [1]2-3FITs/m length/cm 10 excluding global levels [2]Andrew B. Kahng, UCSD ECE 260B, January 21, 201024
History: Low-k Roadmap EvolutionEffective Dielectric Constant; keffSince 2003, based on wiring capacitance calculation of three kinds ofdielectric structures and validated against efore 2001,unreasonable RMwithout logical basisITRS1999Year of 1st Shipment2009 decreased max bulk k by 0.1 - no significant change on keffin 2009effAndrew B. Kahng, UCSD ECE 260B, January 21, 201025
Comments AR is important Thickness control (planarization by CMP) specimplies large interconnect RC variation Current processes often have thick-metal ontop two layers (above “global”) Leading-edge designs (clock, analog) will often“staple” (superpose) traces on multiple layersto reduce resistance M1 pitches show that “foundry X nm process”is often not a true X nm process in the ITRSsense – rather, more in a marketing senseAndrew B. Kahng, UCSD ECE 260B, January 21, 201026
Packaging Roadmap (January 2009)Year of Production20092010201120122013Low-cost, hand-held and 54.22-1.81.21 - 1.71.20 - 1.6333333Cost-performance (MPU)0.90.961.131.111.1High-performance 1050Cost performance660–2801660–2783720- 3061720–3367800–3704High performance cost, hand held and .7Cost per Pin Minimum for Contract Assembly (Cents/Pin)Harsh2Maximum Power (Watts/mm )Hand held and memory (Watts)Package Pin count MaximumMinimum Overall Package Profile (mm)Andrew B. Kahng, UCSD ECE 260B, January 21, 201027
Test (Burn-In) Roadmap (January 2009)Year of ProductionClock input frequency (MHz)Off-chip data frequency (MHz)Power dissipation (W per DUT)Power Supply Voltage Range (V)High-performance ASIC / microprocessor / graphicsprocessorLow-end microcontrollerMixed-signalMaximum Number of Signal I/OHigh-performance ASICHigh-performance microprocessor / graphicsprocessor / mixed-signalCommodity memoryMaximum Current (A)High-performance microprocessorHigh-performance graphics processorBurn-in SocketPin countPitch (mm)Power consumption (A/Pin)Wafer Level Burn-InMaximum burn-in temperature (ºC)Pad Layout – LinearMinimum pad pitch (μm)Minimum pad size (μm)Maximum number of probesPad Layout – Periphery, Area ArrayMinimum pad pitch (μm) *1Minimum pad size (μm)Maximum number of probesPower consumption (KW/wafer – Low-endmicrocontroller, DFT/BIST SOC 30000.2530000.2530000.15175 3175 3175 3175 3175 3175 3175 025300k55Andrew B.10Kahng, UCSD10 ECE 260B,10 January10 21, 20101528
Today’s Agenda What is the semiconductor roadmap? Connections game: Why do we care? Aspects of the Design roadmap Aspects of the System Drivers roadmap and theOverall Roadmap Technology Characteristics(ORTCs) More Than MooreAndrew B. Kahng, UCSD ECE 260B, January 21, 201029
Silicon Complexity Challenges Silicon Complexity impact of process scaling, newmaterials, new device/interconnect architectures Non-ideal scaling (leakage, power management, circuit/deviceinnovation, current delivery) Coupled high-frequency devices and interconnects (signalintegrity analysis and management) Manufacturing variability (library characterization, analog anddigital circuit performance, error-tolerant design, layoutreusability, static performance verificationmethodology/tools) Scaling of global interconnect performance (communication,synchronization) Decreased reliability (SEU, gate insulator tunneling andbreakdown, joule heating and electromigration) Complexity of manufacturing handoff (reticle enhancementand mask writing/inspection flow, manufacturing NRE cost)Andrew B. Kahng, UCSD ECE 260B, January 21, 201030
System Complexity Challenges System Complexity exponentially increasing transistorcounts, with increased diversity (mixed-signal SOC, ) Reuse (hierarchical design support, heterogeneous SOCintegration, reuse of verification/test/IP) Verification and test (specification capture, design forverifiability, verification reuse, system-level and softwareverification, AMS self-test, noise-delay fault tests, test reuse) Cost-driven design optimization (manufacturing costmodeling and analysis, quality metrics, die-package cooptimization, ) Embedded software design (platform-based system designmethodologies, software verification/analysis, codesignw/HW) Reliable implementation platforms (predictable chipimplementation onto multiple fabrics, higher-level handoff) Design process management (team size / geog distribution,data mgmt, collaborative design,process improvement)Andrew B. Kahng, UCSD ECE 260B, January 21, 201031
50 0122013201420152016201720182019202020212022Total HW Engineering Costs EDA Tool Costs 47 35 31 34 20 39 27 29 30 18 9 13 21 24 12 45 2 8 29 40 25 33 27 37 17 22 21 16 21 21 31 24 33 15 22 16 20 19 26 33 41 56 79 34 47Executable SpecificationSystem Design AutomationTransactional MemorySMP Parallel ProcessingMany Core Devel. ToolsIntelligent TestbenchAMP Parallel ProcessingVery Large Block ReuseTransaction Level ModelingRTL Functional Verif. Tool SetIC Implementation Tool SetITRS Design Cost Chart 2009 ( M) 150 100 42Total SW Engineering Costs ESDA Tool CostsAndrew B. Kahng, UCSD ECE 260B, January 21, 201032
System-Level Design and Software Hardware design productivity is growing appropriately Requirements correspond roughly with solutions Innovations pacing properly (transistors / designer / year) Large gap in software productivity possibly opening up If hardware accelerators are heavily leveraged, problem mitigated Otherwise, possibly 100X gap can affect memory size, other 2009 ITRS adds new parameters accordingly Hardware design productivity requirement Software design productivity requirement(alternativeScenario)Andrew B. Kahng, UCSD ECE 260B, January 21, 201033
Future Impact of (System-Level, SW/HW)Design on PowerAndrew B. Kahng, UCSD ECE 260B, January 21, 201034
Impact of Design on “Sigma” (Variability) Goal Quantify “how manysigmas” design can“reduce” ITRS 2005: CD 3 tolerance changedfrom 10% 12% perDesign guidance Approach Inventory of designtechniques / tools Match inventory toparameters orcorrelations in model Use variability modelto capture “delta” insigmas See work of S. Nassifet al., IBM ARLSystem / SWCheck overall variationLogic / functionCircuitDeviceManufacturingUse variability modelInputs (manufacturing)Andrew B. Kahng, UCSD ECE 260B, January 21, 201035
Today’s Agenda What is the semiconductor roadmap? Connections game: Why do we care? Aspects of the Design roadmap Aspects of the System Drivers roadmap and theOverall Roadmap Technology Characteristics(ORTCs) More Than MooreAndrew B. Kahng, UCSD ECE 260B, January 21, 201036
0.010.1VideoConsumer 0ExtractionCompressionMPEG4MP/HLSentence TranslationVoice Auto TranslationDolby-AC3MPEGWord RecognitionGraphics3D Graphics 10Mpps100Mpps2D GraphicsCommunicationSW Defined RadioVoIP ModemFace RecognitionRecognition ModemVoice Print RecognitionMoving Picture RecognitionFAX Two flavors: Portable (baseband processor) andStationary (GPU) 2008: Updated with realistic dynamic power Memory dynamic power 10X less than modeled previously4.3 W max total (2022)8 W max total (2022)Figure 6 SoC Power r [mW]Power 001,0000200702008 2009 20102007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022Trend: Memory Static PowerTrend: Memory Dynamic PowerRequirement: Dynamic plus Static PowerTrend: Logic Static PowerTrend: Logic Dynamic Power2011 2012 20132014 20152016 2017 20182019 2020 2021Trend: Memory Static PowerTrend: Logic Static PowerTrend: Memory Dynamic PowerTrend: Logic Dynamic Power2022Requirement: Dynamic plus Static PowerFiSYSD6 SOC CP t bl PCtiTd 2009: Total power budget reduced 1W 0.5W Future: “wireless” driver with RF/A/MS requirements Future: more specific parameters for Test roadmap #clocks, #power domains, #unique cores,#IOs,etc.Andrew B. Kahng,UCSDECE 260B, January 21, 201037
SOC Consumer Portable Architecture Model- #Main Processors grows to 2, 4 and beyond- Power budget reduced to 0.5W- Die size reduces slowly to 44mm2Main MainPrc. Prc.PE-1MainPrc.MainPrc.PE-2MainPrc.MainPrc. PE-nMainMemoryPeripheralsMain MainPrc. alsFunction AFunction BFunction DFunction EFunction CAndrew B. Kahng, UCSD ECE 260B, January 21, 201038
ORTCs: A-Factor Models ( Heart of ITRS)(Area A-factor F2) Logic: A-factor 175NWell SRAM: A-factor 60M2 pitch(PM2 1.25PM1)ActivePolyContactM1M1 pitch (PM1)Contacted-poly pitch(PPoly 1.5PM1)NAND2 Area 3 PPoly 8 PM2 (3 1.5 PM1) (8 1.25 PM1) 45 (PM1)2 180 F2 175 F2Contacted-poly pitch(PPoly 1.5PM1)SRAM Bitcell Area 2 PPoly 5 PM1 3 PM1 5 PM1 15 (PM1)2 15 (2 F)2 60 F2Andrew B. Kahng, UCSD ECE 260B, January 21, 201039
New MPU Density/Power/Frequency RoadmapPhysical Lgate (L)M1 Half-Pitch (F)DecreasePdyn and PleakIncrease Pdyn ,decrease PleakUnit cell sizeA-Factor (A)Logic: 320 (WAS) 175 (IS)SRAM: 100 (WAS) 60 (IS)#core/die, #tr/core12.2% / year (WAS) 18.9% / year ( 2013, IS), 12.2% / year (2014 , IS)Growth of #Tr2x / 3 year (WAS) 2x / 2 year (IS)up to 2013Die size reduction310mm2 (WAS) 260mm2 (IS)Increased Pdyn and PleakAndrew B. Kahng, UCSD ECE 260B, January 21, 201040
Design Pacing, Challenges Unabated 2009: Lgate and M1 HP scaling updates change DriversM1 Half Pitch2 year delay, but faster scaling0.7x / 3yr 0.7 / 2yr ( 2013), 0.7x / 3yr (2014 )Updated MPU model (power)Physical Lgate1 year shift#Tr per dieNew A-factorsFaster M1 half pitch reductionAndrew B. Kahng, UCSD ECE 260B, January 21, 201041
Frequency-PowerEnvelope RemainsCritical System Issue Current priorities Power #1 goal Frequency slowdown Multicore enablestradeoff Point of this slide: ITRSgives a “best-guess”tradeoff Need to track tradeoff Market vigilance Yearly adjustment7.7% / year 2013: 18.9% / year2014 : 12.2% / yearAndrew B. Kahng, UCSD ECE 260B, January 21, 201042
History: Architecture Wakeup Call in 2001 Historical “Moore’s Law” of 2X/node frequencyincrease came from two sources 1.4X from device: (PIDS 17%/year** improvement of CV/I) 1.4X from “microarchitecture” (pipelining, etc.) 2001 ITRS: Clock period 12 FO4 INV delays 200 CV/I “Microarchitectureruns out of steam” Frequency roadmap:2X 1.4X/node**ITRS 2008: PIDS ITWGshifted to 13%/year CV/Iper Design guidanceMPU max on-chip clock frequency went from 3.8GHz inPentium4 to 3.3GHz in Penryn – WHY?Andrew B. Kahng, UCSD ECE 260B, January 21, 201043
History: Power Wakeup Call in 2007 Power is a hard limit E.g., 120W for the desktop platform Previous ITRS allowed max chip power and max W/cm2power density to grow Previous ITRS roadmapped the “power managementgap” – but there can be no “gap” in actual products “New Marketing” (2007): Utility GOPS, not GHz when we can’t scale frequency due to power limit Frequency scaling for MPUs is function of: (1) multicore roadmap, (2) hard limit on power, and (3) MPUarchitecture choicesAndrew B. Kahng, UCSD ECE 260B, January 21, 201044
2007 ITRS: 1X Frequency Scaling for MPU Crude Assumptions Die Area:Number of Cores:Total Pdynamic : (switch factor):Switched cap / mm2:Vdd:Total Pstatic :1X / node (current MPU model)2X / node (current MPU model)1X / node (NEW, CONSTRAINT)1X / node1.15X / node (Borkar/Intel, 2001 reverify)0.95X / node (historical ITRS)1X / node (high-k, #FO4s , ) Implications x C x Vdd2: Frequency: GOPS:1.04X / node (from above)0.98 X / node ( CV2f 1X, P f3, 0.96 0.983)2X / node (2X #cores, 1X frequency)Andrew B. Kahng, UCSD ECE 260B, January 21, 201045
Your Thoughts on Frequency Scaling? Why frequency might scale at 0.98X / node Static power increases rapidly vs. dynamic power Inter-die wires/logic not accounted for Why frequency might scale at 0.98X / node Number of FO4s in the clock period is increasing Save power faster than we give up frequency, due to logicoptimization Static power can be better managed can use more HVT,less LVT High-k dramatically reduces Igate (and improves subthresholdswing) Better opportunity for DVFS with multi-core (andheterogeneity) Application, OS-driven power management Power budget may actually increase very gradually Cores are smaller Need to market new products 2X cores, 1X frequency is value proposition for consumersAndrew B. Kahng, UCSD ECE 260B, January 21, 201046
Energy-Delay Tradeoff Curve Very little bang for the buck at extremes Shape of tradeoff curve, and location on curve, arerelevant as MPU frequency backs away from limits ofprocess E.g., more power reduction (logic, Vt) available when freq E.g., cubic relationship between power and frequencyAndrew B. Kahng, UCSD ECE 260B, January 21, 201047
Other Considerations Consider reliability as a constraintConsider stacking / 3D integrationConsider DVFS impact on peak power, utilityConsider parallel SW impact on utilityConsider frequency-power tradeoff calibrated tostandard ASIC/SOC implementation flows Adjust for 3-year technology node timing Consider server platform vs. desktop platformAndrew B. Kahng, UCSD ECE 260B, January 21, 201048
Today’s Agenda What is the semiconductor roadmap? Connections game: Why do we care? Aspects of the Design roadmap Aspects of the System Drivers roadmap and theOverall Roadmap Technology Characteristics(ORTCs) More Than MooreAndrew B. Kahng, UCSD ECE 260B, January 21, 201049
“More Than Moore” (2007 ITRS) New workIn 2009Moore’s Law & MoreMoreDiversificationthan Moore: DiversificationFunctional(More than Moore)New in 2009: Survey updatesto ORTC Models Equivalent ScalingRoadmap TimingSynchronized withPIDS and FEP[Geometrical & Equivalent scaling]Baseline CMOS: CPU, Memory, aditionalORTC urce: 2009 ITRS Executive Summary Fig 1SensorsActuatorsBiochipsInteracting with peopleand environment130nm90nmHVPassivesPowerNew in 2009: More than Moore“White Paper” More CommentaryIn ITWG ChaptersCCooNon-digital InformationaannddSProcessingSiPi :P:HDigital teSymsstem Online in 2008:s SIP “White Paper”www.itrs.net/papers.htmlBeyond CMOSNew in 2009: Research and PIDS transfer timing clarified Work underway to identify next storage elementAndrew B. Kahng, UCSD ECE 260B, January 21, 201050
2007/08 ITRS “Moore’s Law and More”Alternative Definition Graphic[2009 – rs,ActuatorsBio-chips,Fluidics“More Moore”“More than Moore”Computing &Data StorageSense, interact,EmpowerHeterogeneous IntegrationSystem on Chip (SOC) and System In Package (SIP)Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)Andrew B. Kahng, UCSD ECE 260B, January 21, 201051
2008 ITRS “Beyond CMOS” Definition Graphic[2009 – Unchanged]Baseline UltimatelyCMOS ScaledCMOS32n22nm 16nmmNanowire Ferromagnetic Spin LogicElectronics Logic Devices DevicesFunctionallyEnhanced CMOS11nm8nmMultiple gate MOSFETsChannel Replacement MaterialsLow Dimensional Materials ChannelsNew State VariableNew DevicesNew Data RepresentationNew Data ProcessingAlgorithms“More Moore”“Beyond CMOS”Computing and Data Storage Beyond CMOSSource: Emerging Research Device Working GroupAndrew B. Kahng, UCSD ECE 260B, January 21, 201052
Recap What is the semiconductor roadmap? Connections game: Why do we care? Aspects of the Design roadmap Aspects of the System Drivers roadmap and theOverall Roadmap Technology Characteristics(ORTCs) More Than MooreAndrew B. Kahng, UCSD ECE 260B, January 21, 201053
BACKUPAndrew B. Kahng, UCSD ECE 260B, January 21, 201054
Problem: Uncontrollable Variation Chips don’t work asdesigned Loss of predictability Guardbands Overdesign Worse time to market,cost, power Loss of product valueFigure courtesy IntelAcross-wafer frequency variation What performance spec for thischip?Andrew B. Kahng, UCSD ECE 260B, January 21, 201055
Problem: Yield and Cost and Risk Chips are thrown away Consider a cellphone chip selling 100M copies Design house pays 5K/300mm wafer in 90nmtechnology 10mm x 10mm die size at 90nm 700 die/wafer 90% vs. 95% yield 630 vs. 665 good die per wafer 158730 vs. 150370 wafers needed to meet thedemand 42M difference What matters is good die/wafer Not too slow, not too power-hungry .Andrew B. Kahng, UCSD ECE 260B, January 21, 201056
Leakage Power Leakage power unwantedcurrent in transistors “Wasted power” Thought of as biggest potentialroadblock to Moore’s Law Subthreshold leakage biggestleakage component at operatingtemperatures (exponential dep)Figure courtesy Roy et al. Back of envelope: 30% of 100W power per uP is leakage200M uP chips sold100W-yr 714 pounds of coal burned10% leakage savings 3W per uP1W to cool per 1W dissipatedSaves (3 x 200M) x (714 / 100) x 2 8,568,000,000 pounds of coal peryear (x2.86) 24,504,000,000 poundsof CO2 per year About 0.2% of total of USA or ChinaFigure courtesy Blaauw et al.Andrew B. Kahng, UCSD ECE 260B, January 21, 201057
1.41.330%Normalized FrequencyLeakage Power Variability1.21.120x1.00.905101520Normalized Leakage Leakage power variability Subthreshold leakage is exponential in almost everything (L, Vt,Tox, Temperature, Voltage.) 5-20X variation is common Gate length ( “Lgate”, or “CD” – “critical dimension”)manufacturing variation is biggest source Power-limited yield loss Problematic leakage power and ‘burn-in’ testing Design must deal with this manufacturing-inducedvariationAndrew B. Kahng, UCSD ECE 260B, January 21, 201058
DPL Also Causes A “Bimodal” Problem TWO CD distributions and TWO different colorings TWO different timingsM12-type cellM21-type cell
What is the Semiconductor Roadmap? Something you need to read ! Enabling mechanism for Moore's Law Synchronizes many industries to "clock" of technology nodes A Very Big Picture ! Lithography, Interconnect, Assembly and Packaging, Test, Design, Technology roadmap (not business roadmap) Structured as requirements potential
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Dr. Sunita Bharatwal** Dr. Pawan Garga*** Abstract Customer satisfaction is derived from thè functionalities and values, a product or Service can provide. The current study aims to segregate thè dimensions of ordine Service quality and gather insights on its impact on web shopping. The trends of purchases have
Chính Văn.- Còn đức Thế tôn thì tuệ giác cực kỳ trong sạch 8: hiện hành bất nhị 9, đạt đến vô tướng 10, đứng vào chỗ đứng của các đức Thế tôn 11, thể hiện tính bình đẳng của các Ngài, đến chỗ không còn chướng ngại 12, giáo pháp không thể khuynh đảo, tâm thức không bị cản trở, cái được
Le genou de Lucy. Odile Jacob. 1999. Coppens Y. Pré-textes. L’homme préhistorique en morceaux. Eds Odile Jacob. 2011. Costentin J., Delaveau P. Café, thé, chocolat, les bons effets sur le cerveau et pour le corps. Editions Odile Jacob. 2010. Crawford M., Marsh D. The driving force : food in human evolution and the future.
Le genou de Lucy. Odile Jacob. 1999. Coppens Y. Pré-textes. L’homme préhistorique en morceaux. Eds Odile Jacob. 2011. Costentin J., Delaveau P. Café, thé, chocolat, les bons effets sur le cerveau et pour le corps. Editions Odile Jacob. 2010. 3 Crawford M., Marsh D. The driving force : food in human evolution and the future.
