IPC TRAINING - Texas Instruments

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IPC TRAININGProcessor Communication Link11/13/2014Version 2.21This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.IPC 3.30

Agenda Overview IPC Modules Configuration Scalability Optimization FootnotesIPC 3.302

Overview Inter-Processor Communication (IPC) Communication between processors Synchronization between processors Two modes Peer-to-peer All cores running TI-RTOS Master-slave Master core running HLOS (e.g. Linux, QNX, Android) Slave cores running TI-RTOSIPC 3.303

Overview Rich device support Homogeneous devices C6472, C6678, . Heterogeneous devices OMAP5, DRA7XX, TCI6638K2X, OMAP-L138, F28M35, .IPC 3.304

Overview Flexible design supports many use cases Many thread combinations (Task, Swi, Hwi) Two types of messaging: notification, message queuing Multi- or uni-processor environments Hardware abstraction Device-specific support for hardware spinlocks, inter-processormailbox IPC APIs are same across devices (e.g. GateMP implemented withhardware spinlock or software Peterson algorithm as needed) OS-agnostic Same APIs on all operating systemsIPC 3.305

Overview - ArchitectureApplicationIPCSYS/BIOSHardwareIPC 3.306

Overview Top-level modules, used by ateMPIPC 3.307

Overview – create/open Create/open model used to share instances of IPCmodules Shared objects are “created” by the owner and “opened”by the user(s) Some objects may be opened multiple times (e.g. MessageQ,GateMP). Objects must have system-wide unique names Delete/close methods are used to finalize objects Owner should not delete until all users have closedIPC 3.308

Overview Cache Management Cache coherency operations are performed by the module whenshared state is accessed/modified Shared data is padded to prevent sharing cache line with otherdata Data Protection Shared data is protected by a multi-processor gate whenaccessed/modifiedIPC 3.309

Agenda Overview Lab 1 – ex01 hello Configuration Scalability Optimization FootnotesIPC 3.3010

IPC Modules Ipc – IPC Manager MessageQ – send and receive messages NameServer – distributed name/value database Notify – send and receive event notifications MultiProc – processor identification SharedRegion – shared memory address translation GateMP – protect a critical section HeapMemMP, HeapBufMP – multi-processor memoryallocatorIPC 3.3011

Ipc Module Ipc – IPC Manager Used to initialize IPC and synchronize with other processors. Application must call Ipc start and Ipc attach. Two startup protocols Ipc.ProcSync ALL - all processors start at same time Ipc.ProcSync PAIR – host processor starts first Configuration Ipc.procSync configures startup protocol When using Ipc.ProcSync ALL, Ipc attach is calledinternally from Ipc start. Application does not call Ipc attach.IPC 3.3012

Ipc Module – Ipc.ProcSync ALLapp.cfgvar Ipc xdc.useModule('ti.sdo.ipc.Ipc');Ipc.procSync Ipc.ProcSync ALL;var MultiProc setConfig(proc, ["HOST", "IPU1", "DSP1"]);SR 0ReservedHeaderhost is ownerof SR 0FlagsHOSTIpc start()Log print("IPC ready")handshakecompletesHeapIPU1Ipc start()Log print("IPC ready")DSP1Ipc start()Log print("IPC ready")IPC 3.3013

IPC Module – Ipc.ProcSync PAIRvar Ipc xdc.useModule('ti.sdo.ipc.Ipc');Ipc.procSync Ipc.ProcSync PAIR;HOSThandshakecompletesSR 0host is ownerof SR 0Ipc start()do {status Ipc attach(IPU1)} while (status Ipc E NOTREADY)Log print("IPC to IPU1 ready")do {status Ipc attach(DSP1)} while (status Ipc E NOTREADY)Log print("IPC to DSP1 ready")IPU1ReservedHeaderFlagsHeapIpc start()do {status Ipc attach(HOST)} while (status Ipc E NOTREADY)Log print("IPC to HOST ready")DSP1Ipc start()do {status Ipc attach(HOST)} while (status Ipc E NOTREADY)Log print("IPC to HOST ready")IPC 3.3014

Ipc Module Topology Topology expresses which processors communicate with IPC Transport created between two processors when they attach In previous example, HOST attached to IPU1 and DSP1. If IPU1 and DSP1 need to communicate with IPC, they must alsoattach to each other. Using Ipc.ProcSync ALL creates transports between allprocessors.HOSTtransportDSP1IPU1IPU1 and DSP1 must attachto create their own transportIPC 3.3015

Ipc Module Why have two modes? Because some applications are static and some are dynamic. Static System In a static system all processors are started at the same time. Oncethe processor is loaded, same application runs forever. IPC startupis part of device boot phase. This is typical for homogeneousdevices. Base station, telecommunication, single purpose application. Dynamic System In a dynamic system, host processor boots first. Slave processorsare booted later depending on application. Slave is shut downwhen application terminates. Slave reloaded many times, possiblywith different executable. Consumer electronics, cell phone.IPC 3.3016

Ipc Module - API API Summary Ipc start – reserve memory, create default gate and heap Ipc stop – release all resources Ipc attach – setup transport between two processors Ipc detach – finalize transportIPC 3.3017

Ipc Module - ROV ROV screen shotIPC 3.3018

MessageQ MessageQ – send and receive messages A message queue receives messages Single reader, multiple writers on same message queue Message queue instance created by reader, opened by writermsgmsgwriterIPC 3.3019

MessageQ — transport Transport-independent API, works with local memory, sharedmemory, copy based transport (SRIO) Default transport offers zero-copy transfers via shared eQTransportTransportIPC 3.3020

MessageQ Message structure Every message contains an embedded message queue headerfollowed by the payload. Application is responsible for the headerallocation. Message size must include header and payload sizes. Actual message size is typically paddedMessageQ MsgHeaderPayloadmessagesizetypedef struct {Bits32 reserved0;Bits32 reserved1;Bits32 msgSize;Bits16 flags;Bits16 msgId;Bits16 dstId;Bits16 dstProc;Bits16 replyId;Bits16 replyProc;Bits16 srcProc;Bits16 heapId;Bits16 seqNum;Bits16 reserved;} MessageQ MsgHeader/*/*/*/*/*/*/*/*/*/*/*/*/*reserved for List.elem- nextreserved for List.elem- prevmessage sizebitmask of different flagsmessage iddestination queue iddestination processor idreply idreply processorsource processorheap idsequence numberreserved*/*/*/*/*/*/*/*/*/*/*/*/*/typedef struct {MessageQ MsgHeader reserved;char payload[50];} App Msg;IPC 3.3021

MessageQ Message types MessageQ MsgHeader is structure type definition.typedef struct {.} MessageQ MsgHeader; MessageQ Msg is pointer to structure type definition.typedef MessageQ MsgHeader *MessageQ Msg; Message Allocation Message allocation must be large enough to hold the embeddedmessage queue header and your payload. See Message structure.IPC 3.3022

MessageQ – reader/writer IPU DSP Send a message from IPU to DSP (one-way message) Both processors register a heap with MessageQ module Receiving processor creates a message queue (DSP) Sending processor opens the message queue (IPU) Sending processor will. allocate a message write the payload send message Receiving processor will. get message read the payload free the messageIPC 3.3023

MessageQ – reader/writer IPU DSPIPUDSPSharedRegion #0ReservedHeaderMessageQHeapId IHeap Handle2MessageQHeapId IHeap Handlesr0: HeapMemMP2sr0: HeapMemMPWritersr0: HeapMemMPReaderDSP.workq:MessageQMessageQ allocMessageQ getmsgmsgMessageQ putmsgMessageQ freeIPC 3.3024

MessageQ – reader/writerIPU (writer)#include xdc/std.h #include ti/ipc/MessageQ.h #include ti/ipc/SharedRegion.h #define HEAP ID 2#define MSG SZ sizeof(MessageQ MsgHeader) 50Ptr heap;MessageQ Msg msg;MessageQ QueueId qid;heap SharedRegion getHeap(0);MessageQ registerHeap(HEAP ID, heap);do {status MessageQ open("DSP1.workq", &qid);Task sleep(1);} while (status MessageQ E NOTFOUND);while (running) {msg MessageQ alloc(HEAP ID, SIZE)/* write payload */MessageQ put(qid, msg)}IPC 3.3025

MessageQ – reader/writerDSP (reader)#include xdc/std.h #include ti/ipc/MessageQ.h #include ti/ipc/SharedRegion.h #define HEAP ID 2Ptr heap;MessageQ Handle que;MessageQ Msg msg;heap SharedRegion getHeap(0);MessageQ registerHeap(HEAP ID, heap);que MessageQ create("DSP1.workq", NULL);while (running) {MessageQ get(que, &msg, MessageQ FOREVER);/* read payload */MessageQ free(msg);}IPC 3.3026

MessageQ – client/server IPU DSP IPU Send a message from IPU to DSP and back again (round tripmessage) Both processors create a message queue IPU processor will. allocate a message write the payload send message wait for return message read payload free the message DSP processor will. wait for message read the payload write new payload send messageIPC 3.3027

MessageQ – client/server IPU DSP IPUIPUSharedRegion #0DSPReservedHeaderMessageQMessageQsr0: HeapMemMPClientMemory allocServermsgMessageQ staticMsgInitMessageQ setReplyQueueDSP.workq:MessageQmsgMessageQ getmsgMessageQ putmsgMessageQ getReplyQueueMessageQ putn: MessageQMessageQ getmsgmsgMemory freeIPC 3.3028

MessageQ – client/serverIPU (client)#include#include#include#include#include xdc/std.h xdc/runtime/IHeap.h xdc/runtime/Memory.h ti/ipc/MessageQ.h ti/ipc/SharedRegion.h #define MSG SZ sizeof(MessageQ MsgHeader) 50IHeap Handle heap;MessageQ Handle ipuQ;MessageQ Msg msg;MessageQ QueueId dspQ;heap (IHeap Handle)SharedRegion getHeap(0);ipuQ MessageQ create(NULL, NULL);do {status MessageQ open("DSP.workq", &dspQ);} while (status MessageQ E NOTFOUND);msg Memory alloc(heap, SIZE, 0, NULL);MessageQ staticMsgInit(msg, SIZE);MessageQ setReplyQueue(ipuQ, msg);/* write payload */MessageQ put(dspQ, msg);MessageQ get(ipuQ, &msg, MessageQ FOREVER);/* read payload */Memory free(heap, msg, SIZE);IPC 3.3029

MessageQ – client/serverDSP (server)#include xdc/std.h #include ti/ipc/MessageQ.h #include ti/ipc/SharedRegion.h MessageQ Handle dspQ;MessageQ QueueId qid;MessageQ Msg msg;dspQ MessageQ create("DSP.workq", NULL);while (running) {MessageQ get(dspQ, &msg, MessageQ FOREVER);/* process payload */qid MessageQ getReplyQueue(msg);MessageQ put(qid, msg);}IPC 3.3030

MessageQ MessageQ works with any SYS/BIOS threading model: Hwi: hardware interrrupts Swi: software interrupts Task: threads that can block and yield Variable size messages Timeouts are allowed when a Task receives messages Message Ownership Rules Acquire ownership with MessageQ alloc, MessageQ get Loose ownership with MessageQ free, MessageQ put Do not dereference a message when you don’t have ownershipIPC 3.3031

MessageQ Uses an IHeap heap implementation to supportMessageQ alloc and MessageQ free. Heaps are coordinated across processors by a commonindex which is registered using MessageQ registerHeapAPI Heap ID is stored in message headerIPC 3.3032

MessageQ - API API Summary MessageQ create – create a new message queue MessageQ open – open an existing message queue MessageQ alloc – allocate a message from the pool MessageQ free – return message to the pool MessageQ put – send a message MessageQ get – receive a message MessageQ registerHeap – register a heap with MessageQIPC 3.3033

MessageQ - ROV ROV screen shotIPC 3.3034

Lab ‒ ex01 hello Please open the PowerPoint slide namedIPC Lab 1 HelloIPC 3.3035

NameServer Module NameServer – distributed name/value database Manages name/value pairs Used for registering data which can be looked up by otherprocessors API Summary NameServer create – create a new database instance NameServer add – add a name/value entry into database NameServer get – retrieve value for given nameIPC 3.3036

NameServer IPU – create NameServer instance DSP – query IPU for name/value pairIPUDSPApplicationApplicationNameServer createNameServer createNameServer addNameServer getemail: NameServerJohnDoeemail: NameServerjohndoe@mm.comIPC 3.3037

NameServer IPU – create NameServer instance DSP – query IPU for name/value pairIPUDSP#include string.h #include xdc/std.h #include ti/ipc/NameServer.h #include xdc/std.h #include ti/ipc/NameServer.h NameServer Handle ns;Char buf[32];Int len;NameServer Handle ns;Char buf[];Int len;ns NameServer create("email", NULL);ns NameServer create("email", NULL);NameServer get(ns, “JohnDoe", buf, &len, NULL);strcpy(buf, “johndoe@mm.com");Int len strlen(buf);NameServer add(ns, “JohnDoe", buf, len);IPC 3.3038

NameServer Module ROV screen shotIPC 3.3039

Notify Module Notify – send and receive event notifications Inter-processor notifications Multiplex 32 events using single interrupt line Some events are used by IPC Notification is point-to-point Callback functions Register for a specific procId lineId eventId triplet Callback can be reused (use procId and lineId to de-multiplex) Callbacks can be chained (all callbacks are invoked) Callback function receives procId, eventId, arg, payload API Summary Notify sendEvent – raise an event Notify registerEvent – register a callback for an event Notify registerEventSingle – register for exclusive use of event Notify FnNotifyCbck – callback function type definitionIPC 3.3040

Notify IPU DSP IPU sends a notification to the DSP IPU processor will. Send a NOP event to test the connection (optional) Send periodic event to the DSP DSP processor will. Create a semaphore to synchronize between callback and task Register for event notification Notify callback will post the semaphore Task will runIPC 3.3041

Notify IPU DSPDSPIPUn: TaskApplicationn: SemaphoreNotify sendEventSemaphore postnotifyCBApplicationIPCIPCraise interruptMailboxipc: HwiCPUIPC 3.3042

NotifyIPU#include xdc/std.h #include ti/ipc/MultiProc.h #include ti/ipc/Notify.h #define EVT 12#define NOP 0UInt16 dsp MultiProc getId("DSP");UInt32 payload;do {s Notify sendEvent(dsp, 0, EVT, NOP, TRUE);if (s Notify E EVTNOTREGISTERED) {Task sleep(1);}} while (s Notify E EVTNOTREGISTERED);do {/* work */payload .;Notify sendEvent(dsp, 0, EVT, payload, TRUE);} until(done);IPC 3.3043

NotifyDSP#include#include#include#include xdc/std.h ti/sysbios/knl/Semaphore.h. ti/ipc/MultiProc.h ti/ipc/Notify.h #define EVT 12#define NOP 0UInt16 IPU MultiProc getId("IPU");Semaphore Handle sem;sem Semaphore create(0, NULL, NULL);Notify registerEvent(IPU, 0, EVT, notifyCB, (UArg)sem);do {Semaphore pend(sem, BIOS WAIT FOREVER);/* work */} until(done);Void notifyCB(UInt16 procId, UInt16 lineId,UInt32 eventId, UArg arg, UInt32 payload){Semaphore Handle sem (Semaphore Handle)arg;if (payload ! NOP) {Semaphore post(sem);}}IPC 3.3044

Notify Module ROV screen shotIPC 3.3045

MultiProc Module MultiProc – processor identification Stores processor ID of all processors in the multi-core application Stores processor name Processor ID is a number from 0 – (n-1) Processor name is defined by IPC IPC Release Notes Package Reference Guide ti.sdo.utils.MultiProc Configuration Settings MultiProc.setConfig Click on Table of Valid Names for Each Device API Summary MultiProc getSelf – return your own processor ID MultiProc getId – return processor ID for given name MultiProc getName – return processor nameIPC 3.3046

SharedRegion Module SharedRegion – shared memory address translation Manages shared memory and its cache configuration Manages shared memory using a memory allocator SRPtr is a portable pointer type Multiple shared regions are supported Each shared region has optional HeapMemMP instance Memory is allocated and freed using this HeapMemMP instance HeapMemMP create/open and managed internally at IPCinitialization SharedRegion getHeap API to get this heap handleIPC 3.3047

SharedRegion Module SharedRegion #0 is special Always contains a heap Contains global state that all cores need to access (reservedheader) Must be placed in memory that is accessible by all BIOS cores inthe system API Summary SharedRegion getHeap – return the heap handle SharedRegion getId – return region ID for given address SharedRegion getPtr – translate SRPtr into local address SharedRegion getSRPtr – translate local address into SRPtrIPC 3.3048

SharedRegion Module ROV screen shotIPC 3.3049

SharedRegion Sometimes, shared memory has different address ondifferent processors. Use SharedRegion to translate addresses.IPU0xA00000002: SharedRegionIPC 3.300x80000000DSP50

SharedRegionipu.cfgvar SharedRegion xdc.useModule('ti.sdo.ipc.SharedRegion');var sr2 new SharedRegion.Entry({name:"SR eta(2, sr2);dsp.cfgvar SharedRegion xdc.useModule('ti.sdo.ipc.SharedRegion');var sr2 new SharedRegion.Entry({name:"SR eta(2, sr2);IPC 3.3051

SharedRegionIPUDSP#include xdc/std.h #include ti/ipc/SharedRegion.h #include xdc/std.h #include ti/ipc/SharedRegion.h Ptr ptr 0xA0004000;SRPtr srptr SharedRegion getSRPtr(ptr, 2);/* Receive message, translate* embedded SRPtr into local pointer.*/MessageQ get(q, &msg);/* Write SRPtr into message payload* and send message to DSP.*/msg- srptr srptr;MessageQ put(q, msg);SRPtr srptr msg- srptr;Ptr ptr SharedRegion getPtr(srptr);/* ptr 0x80004000 */IPC 3.3052

GateMP Module GateMP – protect a critical section Multiple processor gate that provides context protection againstthreads on both local and remote processors API Summary GateMP create – create a new instance GateMP open – open an existing instance GateMP enter – acquire the gate GateMP leave – release the gateIPC 3.3053

GateMP Use GateMP instance to protect buffer from concurrentaccess IPU processor will. create a GateMP instance enter the gate modify shared memory leave the gate DSP processor will. open the GateMP instance enter the gate modify shared memory leave the gateIPC 3.3054

GateMPIPUDSPApplicationApplicationGateMP createGateMP openbuf: GateMPGateMP enterGateMP enter2: SharedRegion/* modify buffer */buf/* modify buffer */GateMP leaveGateMP leaveIPC 3.3055

GateMP ModuleIPUDSP#include xdc/std.h #include ti/ipc/GateMP.h #include xdc/std.h #include ti/ipc/GateMP.h GateMP Params params;GateMP Handle gate;GateMP Handle gate;GateMP open("BufGate", &gate);GateMP Params init(¶ms);params.name "BufGate";params.localProtect GateMP LocalProtect NONE;params.remoteProtect GateMP RemoteProtect SYSTEM;GateMP enter(gate);/* modify buffer */GateMP leave(gate);gate GateMP create(params);GateMP enter(gate);/* modify buffer */GateMP leave(gate);IPC 3.3056

HeapMemMP HeapBufMP Modules HeapMemMP, HeapBufMP – multi-processor memory allocator Shared memory allocators that can be used by multiple processors HeapMemMP – variable size allocations HeapBufMP – fixed size allocations, deterministic, ideal for MessageQ IPC’s versions of HeapBuf, adds GateMP and cache coherencyto the version provided by SYS/BIOS. All allocations are aligned on cache line size. Warning: Small allocations will occupy full cache line. Uses GateMP to protect shared state across cores. HeapBufMP. All buffers are same size (per instance) Every SharedRegion uses a HeapMemMP instance to managethe shared memoryIPC 3.3057

HeapMemMP HeapBufMP Modules API Summary HeapMemMP create – create a heap instance HeapMemMP delete – delete a heap instance HeapMemMP open – open a heap instance HeapMemMP close – close a heap instance HeapMemMP alloc – allocate a block of memory HeapMemMP free – return a block of memory to the pool HeapBufMP create – create a heap instance HeapBufMP delete – delete a heap instance HeapBufMP open – open a heap instance HeapBufMP close – close a heap instance HeapBufMP alloc – allocate a block of memory HeapBufMP free – return a block of memory to the poolIPC 3.3058

HeapMemMP Module ROV screen shotIPC 3.3059

HeapMemMP Create a heap and share it between IPU and DSP IPU processor will. Creates a heap instance Use Memory module to allocate memory DSP processor will. Open the heap instance Use Memory module to allocate memoryIPC 3.3060

HeapMemMP MemMP createHeapMemMP openMemory allocdata: HeapMemMPIPC 3.30Memory alloc61

HeapMemMP Module Casting the heap handle is one of the few places you need to call an IPCPackage API.IPU#include#include#include#include#includeDSP xdc/std.h xdc/runtime/IHeap.h xdc/runtime/Memory.h ti/ipc/HeapMemMP.h ti/sdo/ipc/heaps/HeapMemMP.h #include#include#include#include#include xdc/std.h xdc/runtime/IHeap.h xdc/runtime/Memory.h ti/ipc/HeapMemMP.h ti/sdo/ipc/heaps/HeapMemMP.h HeapMemMP Params params;HeapMemMP Params init(¶ms);params.name "DataHeap";params.regionId 0;params.sharedBufSize 0x100000;HeapMemMP Handle handle;HeapMemMP open("DataHeap", &handle);HeapMemMP Handle handle;handle HeapMemMP create(¶ms);ptr Memory alloc(heap, size, align, NULL);IHeap Handle heap;heap HeapMemMP Handle upCast(handle);IHeap Handle heap;heap HeapMemMP Handle upCast(handle);ptr Memory alloc(heap, size, align, NULL);IPC 3.3062

Agenda Overview IPC Modules Scalability Optimization FootnotesIPC 3.3063

IPC Configuration The RTSC configuration phase is when components areintegrated. Each component uses its configurationparameters to express its system requirement. The application configuration script is the starting point. Itdefines which components are needed by the applicationand configures those components depending on itsneeds.Application willuse MessageQvar MessageQ ameLen 48; /* default 32 */ApplicationCreate long messagequeue namesMessageQapp.cfg A rule of thumb: If you include theheader file in your C code, then youneed to "use" the module in theconfiguration script.IPC 3.3064

IPC Configuration – documentation Navigate to the IPC product folder C:\Products\ipc 3 30 pp bb Open the release notes ipc 3 30 pp bb release notes.html Scroll down to the documentation section Click on Package Reference Guide (cdoc) Tip: the Package Reference Guide is also available in CCS Help. Tip: the Package Reference Guide is also available on-line. Open 'all modules' section Click on a module (e.g. MessageQ) Click on Configuration settings linkIPC 3.3065

IPC Configuration - documentation The documentation shows how to include the module in theapplication configuration script. Scroll down to the 'module-wide config parameters' for a list of allconfiguration parameters.IPC 3.3066

IPC Configuration - documentation When a config param has a default value, it will be indicated after the type. If the config param does not have a default value, this is indicated by thekeyword undefined. Sometimes default values are computed during theconfiguration phase. Scroll down to the 'module-wide functions' section. Sometimes you will needto use these to set a config param.IPC 3.3067

IPC Configuration - documentation Instance Configuration Parameters Some config params are specified when creating an instance. These are listed inthe 'per-instance config parameters' section. However, IPC modules only support instance creation at run-time. You willneed to find the equivalent create parameter in the IPC API Reference Guide. Open the release notes ipc 3 30 pp bb release notes.html Scroll down to the documentation section. Click on IPC Application Programming Interface (API) Reference Guide (HTML) Tip: the IPC API Reference Guide is also available in CCS Help. Tip: the IPC API Reference Guide is also available on-line.IPC 3.3068

Ipc Module Configuration IPC configuration requires the following modules ti.sdo.ipc.Ipc ti.sdo.utils.MultiProc ti.sdo.ipc.SharedRegion Define Ipc startup protocol Ipc.procSync – controls attach behavior Ipc.ProcSync ALL – Attach to all processors simultaneously. Ipc.ProcSync PAIR – Attach to remote processor one-by-one. All processors must use the same startup protocol.var Ipc xdc.useModule('ti.sdo.ipc.Ipc');Ipc.procSync Ipc.ProcSync PAIR;IPC 3.3069

Ipc Module Configuration SharedRegion #0 Memory Setup On some systems, the SR 0 memory may not be available at boot time.Host processor might map the memory into the slaves MMU. Thisconfiguration flag is used to block the slave until the memory is available.Ipc start will spin until this flag is set true by host. Ipc.sr0MemorySetup true; Ipc start will access SR 0 memory immediately. Ipc.sr0MemorySetup false; Ipc start will spin until host sets flag to true. Requires symbol address accessfrom host.IPC 3.3070

Ipc Module Configuration Attach and detach hooks You can register hook functions to be called during each attach and detachcall. Use the hook function to perform application specific tasks.var Ipc xdc.useModule('ti.sdo.ipc.Ipc');var fxn new Ipc.UserFxn;fxn.attach '&userAttachFxn';fxn.detach '&userDetachFxn';Ipc.addUserFxn(fxn, arg); The hook functions have the following type definitions.Int (*attach)(UArg arg, UInt16 procId);Int (*detach)(UArg arg, UInt16 procId);IPC 3.3071

MultiProc Configuration Define the processors in the IPC application. This example defines three processors: CORE0, CORE1, CORE2. Name order defines MultiProc ID (zero based counting number) CORE0 configurationvar procNameAry ["CORE0", "CORE1", "CORE2" ];var MultiProc setConfig("CORE0", procNameAry); CORE1 configurationvar procNameAry ["CORE0", "CORE1", "CORE2" ];var MultiProc setConfig("CORE1", procNameAry); CORE2 configurationvar procNameAry ["CORE0", "CORE1", "CORE2" ];var MultiProc setConfig("CORE2", procNameAry);IPC 3.3072

SharedRegion Configuration Define number of shared regions in the system. This config param must be the same across all processors in the system.Increasing the number of regions reduces the maximum size of eachregion.var SharedRegion ion.numEntries 8;IPC 3.3073

SharedRegion Configuration Define number of shared regions in the system. This config param must be the same across all processors in the system.Increasing the number of regions reduces the maximum size of eachregion.var SharedRegion ion.numEntries 8; Cache Line Size This value is used to align items on a cache line boundary. For example,memory allocations from the shared region heap will be aligned and sizedon this boundary. It must be the same value for all processors using theshared region. It must be the worst case valueSharedRegion.cacheLineSize 128;IPC 3.3074

SharedRegion Configuration Define SharedRegion #0 The shared region base and size are defined in the platform memory m6678:core0"] {.externalMemoryMap: [["SR 0", {name: "SR 0", space: "data", access: "RW",base: 0x84000000, len: 0x200000,comment: "SR#0 Memory (2 MB)"}], Reference the memory map from platform to configure SR 0app.cfgvar SR0Mem Program.cpu.memoryMap["SR 0"];SharedRegion.setEntryMeta(0,new SharedRegion.Entry({name:"SR sValid:true,cacheEnable:true}));IPC 3.3075

SharedRegion Configuration Cache setting for a shared region. Reports memory cache setting This config param does not control the cache behavior, it reflects thecache behavior. In other words, if the shared memory is eligible forcaching, then this parameter must be set true. Controls IPC cache operations When set to true, IPC will perform the necessary cache operations. Processor relative It may be different on each processor using the same shared region.This comes about because each processor defines its cache behavior.IPC 3.3076

Build Configuration Build module used to configure library type.var Build xdc.useModule('ti.sdo.ipc.Build');Build.LibType Build.LibType NonInstrumented; Build.LibType Build.LibType Instrumented – Prebuild library supplied in IPC product.Optimized with logging and asserts enabled. Build.libType NonInstrumented – Prebuilt library supplied in IPC product.Optimized without instrumentation. Build.libType Custom – Rebuilds IPC libraries from source for eachexecutable. Optimized by default. Use Build.customCCOpts to modify compileroptions. Build.libType Debug – Rebuilds IPC libraries from source for each executable.Non-optimized, useful for debugging IPC sources.IPC 3.3077

Build Configuration Build module used to configure library type.var Build xdc.useModule('ti.sdo.ipc.Build');Build.LibType Build.LibType NonInstrumented; Build.LibType Build.LibType Instrumented – Prebuild library supplied in IPC product.Optimized with logging and asserts enabled. Build.libType NonInstrumented – Prebuilt library supplied in IPC product.Optimized without instrumentation. Build.libType Custom – Rebuilds IPC libraries from source for eachexecutable. Optimized by default. Use Build.customCCOpts to modify compileroptions. Build.libType Debug – Rebuilds IPC libraries from source for each executable.Non-optimized, useful for debugging IPC sources. Build.libType PkgLib – Links with package libraries in the IPC product. Theselibraries to not ship with the product. You must rebuild the IPC product to generatethe package

Ipc Module Ipc - IPC Manager Used to initialize IPC and synchronize with other processors. Application must call Ipc_start and Ipc_attach. Two startup protocols Ipc.ProcSync_ALL - all processors start at same time Ipc.ProcSync_PAIR - host processor starts first Configuration Ipc.procSync configures startup protocol When using Ipc.ProcSync_ALL, Ipc_attach is .

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discussed. IPC-6011, IPC-6012C, J-STD-003B and IPC-A-600H Block 3: 1400-1500 (Including one coffee break) Electronic Assembling and Soldering. What is a lead free process. Acceptability and Requirements for Electronic Assemblies will be discussed using IPC Standards; J-STD-001F, IPC-610F, IPC-7711/21B and IPC-620B

IPC-3, IPC-5 USER MANUAL REV. 2.04 7 TEKNIC, INC.PHONE (585)784-7454 IPC-3 SPECIAL SAFETY NOTE Unlike the IPC-5, the IPC-3 is an open frame power supply. As such, there are user-accessible, hazardous voltage points present on the device.

IPC-4101 Specification for Base Materials for Rigid and Multilayer Printed Boards IPC-4101 December 1997 Supercedes IPC-L-108, IPC-L-109, IPC-L-112, IPC-L-115 IPC-AM-361 TheInstitutefor Interconnecting andPackaging ElectronicCircuits A standard developed by the Institute for Interconnecting

API Recommended Practice 2A-WSD Planning, Designing, and Constructing Fixed Offshore Platforms—Working Stress Design TWENTY-SECOND EDITION NOVEMBER 2014 310 PAGES 395.00 PRODUCT NO. G2AWSD22 This recommended practice is based on global industry best practices and serves as a guide for those who are concerned with the design and construction of new fixed offshore platforms and for the .