Evolution Of Processor Architecture In Mobile Phones

International Journal of Computer Applications (0975 – 8887)Volume 90 – No 4, March 2014Evolution of Processor Architecture in Mobile PhonesMahendra Pratap SinghResearch Scholar,Department of Computer Science, MohanlalSukhadia University, Udaipur, IndiaABSTRACTMobile phone has become a vital component of our daily life.Technological advancements have resulted in significantchanges in the processor architecture of mobile phones;transforming the typical mobile phones of 1990’s to modernsmart phones. The design and deployment of mobileprocessors over the years is largely affected byCommunication, performance, and low-power operation. Thetransition from analog to digital telephony has resulted inmobile devices delivering a wide range of data services. Tosupport these services, processor architecture has now becomemuch more complex. Mobile processors are growing rapidlywith each passing generation. The goal of this paper is toreview various processor architectures for mobile phones.KeywordsProcessor architecture, DSP, VLIW, SoC, ARM processors1. INTRODUCTIONSmartphone hardware mainly consists of applicationprocessors (System-on-a-Chip), RAM (mobile SDRAM/mobile DDR), DSP, CPU (ARM processor), etc. Accordingto Farinaz et al [1], Processors that are used for mobile phonesare subject to design metrics that emphasize cost, time-tomarket, and low power. Because of the constrained resourcesof power and cost, and the real-time computationrequirements, the processors for use in mobile applicationspossess a number of distinct characteristics such as limitedprogrammability.Processor architecture of mobile devices delivering dataservices must provide support for much more complex userinterface, dynamic operating environments, and support foradditional services. To provide for these additionalrequirements, advanced architectures may include multipleDSP’s or hardware coprocessors.2. MOBILE PROCESSORARCHITECTURE TRENDS2.1 Traditional DSP (Digital SignalProcessor) ArchitecturesManoj Kumar Jain, Ph. DAssociate Professor, Computer ScienceMohanlal Sukhadia UniversityUdaipur, IndiaThere have been two distinct approaches for implementationof cellular handsets. One approach emphasizes programmableDSP’s, while the other approach utilizes ASIC (Applicationspecific integrated circuit) techniques [6].DSP is a specialized microprocessor used for mobile phones.Historically DSP’s were designed around single stand-aloneintegrated circuits (ICs). Embedded DSP’s are now widelyadopted for VLSI designs. Programmable DSP’s are dominantin wireless handset market for digital cellular telephony.First generation of mobile communications i.e. 1G systemsused analog transmission with the limitations of requiringmore power for transmission and allowing limited users[2].Global System for Mobile Communications (GSM) standardevolved after first generation of mobile communication foranalog cellular networks. DSP processors form one of themost important classes of mobile embedded processors insecond generation i.e. 2G systems.DSP architectures are preferred over ASIC due to shorterproduct life cycle and they are extensively used in GSMmobiles. Programmable DSP’s provide a cost-effective andflexible architecture for cellular telephones. AT&T in 1979introduced first DSP, and subsequently Texas Instrumentscame up with other DSP’s.Traditionally, DSP used Harvard architecture whichphysically separates storage and signal pathway forinstructions and data [2]. This is in contrast with VonNeumann Architecture, where data and instructions are storedin the same memory. As shown in Figure 1, it requires datamemory and instruction memory to execute instructions. Ithas separate data and instruction buses allowing simultaneoustransmission. Subsequently, the output of multiplication unitconnects to an adder, thereby adding and saving all partialresults for further processing.This architecture results in fewer cycles for executing aparticular function as it enables high memory bandwidth andmultiple operand operations. Multiply-accumulate (MAC)instructions are commonly associated with DSP architectures.34

International Journal of Computer Applications (0975 – 8887)Volume 90 – No 4, March 2014DATAMEMORYCONTROL& LOUTSTATUSCLOCKFigure 1: Traditional DSP Architecture (Harvard Architecture)2.2 Modern DSP ArchitecturesApart from traditional architectures, some modern DSParchitectures have evolved for mobile devices. TMS320C55 isa modern DSP architecture which implements Harvardarchitecture utilizing one and three read buses for code anddata, respectively [2]. With TMS320C55 DSP architecture,features like programmable idle modes and automatic powersaving were incorporated for better processor utilization at topspeeds.TMS320C62XX is an example of VLIW (Very longinstruction word) DSP processor. VLIW architecture in DSPprovides a compiler based programmer friendly environment.These VLIW processors follow explicitly parallel instructioncomputing (EPIC) architectures.The TigerSHARK DSP architecture has a series of advancedfeatures like the use of “short vectors” to process informationusing SIMD (single instruction multiple memory) architecture[2].DSPs have become common in mobile devices because theyprovide real-time operation at low power costs. Future mobiledevices have to be aligned to integrate more s.Advancements in DSP lead to higher clock frequencies aswell as a reduced power consumption per MIPS for mobilephones [3].One way of customization is parallelism in superscalardesigns, which is widely implemented for future mobileprocessors. VLIW and SIMD architectures in modern cellulardevices are becoming more and more popular; because theyallow reducing the frequency and voltage of the CPU chipswithout losing performance. Modern DSPs can be moreeffective if they are able to support parallel processing.In modern DSP architectures, computational power hasgreatly improved due to advancements in chip fabrication. Asshown in Table 1 below, the same DSP chip was providingapproximately 5 GIPS (Giga Instructions per Second) in 2000,in contrast to 5 MIPS in 1980 and it has grown to 50 GIPS inthe year 2010. Considering other factors also, theadvancements in DSP integration is significant.Table 1: DSP Integration over the YearsParameter1980199020002010Die Size 40500050000MHz2080100010000RAM (bytes)2562000320001000000Price ansistors50000500000550millionmillionWafer Size361212(inches)Source: Past and Projected Evolution of DSP [Gene 2000)A number of FPGA (Field-programmable gate array)architectures have been specifically designed for DSP toeffectively utilize VLSI resources. VLIW compilers areextensively used in DSP architectures to support instructionlevel parallelism [. The trend in modern DSP architectures isto develop fault-tolerant and reliable DSP systems. DSPsystems are reconfigured keeping in mind a number of designgoals like performance, power, reliability, cost, anddevelopment time. Modern DSP systems are implementedbased on reconfigurable DSP architectures.In modern DSP’s, architecture can be extended by duplicatingthe processor cores. Enhanced DSP’s utilizes SIMDoperations, while multiple-issue DSP’s may implement eitherVLIW or superscalar architectures.2.3 System on Chip (SoC) basedarchitecturesMobile device processor architecture became simple withSOC designs. Real time responsiveness in mobile devices canbe managed by using an enhanced DSP hybrid chip. Loweringthe voltage of the chip enables low power operation in mobiledevices.35

International Journal of Computer Applications (0975 – 8887)Volume 90 – No 4, March 2014Matthias et al [5] proposed a new scalable DSP architecturefor SoC domains. In SoC based designs, system tasks can bemanaged by integrating microcontrollers, dedicated ASIC’s,or DSP’s in a single chip as shown in Figure 2 below:30Figure 2: Traditional DSP Architecture (HarvardArchitecture)Direct Memory AccessNICAUDI020151050StorageARM CPUDigital SignalProcessor (DSP)Operations per CycleMultimedia Decoders/EncodersMemorySoC Chip25USBVIDEOHighly integrated SoC’s leveraging multicore technology hasemerged for higher performance and low power designs. Lowpower operation often limits the architectural choices. Highthroughput of VLIW architectures in mobile devices requiresa fast memory system like cache memories.To speed up the operation of mobile devices, instruction secustomizations have been done by many companies.ARMLtd. has done extensive instruction set customization byencoding most used instructions in 16-bit, so as to supportmore read-write operations.The effect of instruction set customization on performanceand memory utilization can be understood from Figure 3. Aswe customize instruction set from 32-bit data types to 8-bittypes, we are able to effectively improve memory utilizationand the overall performance.Martin at el [13] proposed reconfigurable processorarchitecture for mobile phones. Dynamically ConfigurableSystem on Chip (CSoC) architecture has been optimized formobile communications. CSoC’s are customized for a specificapplication and its architecture consists of processor core,memory, ASIC cores, and on-chip reconfigurable hardwareunits.Most of the smart phones today are single or dual-core SoC’s.For most of the mobile applications, faster dual-core CPUprovides better performance than quad-core SoC’s. FutureSoC’s for mobile will become more sophisticated improvingthe overall performance.Floating32-bit16-bit8-bitPerformance and Memory UtilizationFigure 3: Effect of Instruction Set Customization onperformance and memory utilization2.4 ARM Processors for MobilesARM based processors are the most widely used in modernSmart phones. ARM is a32-bit instruction set architecturebased on RISC architecture [10]. ARM processors areparticularly used in Smart phones because of its low powerconsumption and great performance.ARM holdings provide chip design and instruction setcustomization licenses to third party vendors like Apple,Qualcomm etc. who design their own products based on theprovided architecture.Various ARM architectures used in Smartphone are ARMv5utilized in low-end devices, and ARMv6, ARMv7 utilized inrecent high performance devices. ARMv7 includes ahardware floating-point unit (FPU) providing improved speed.The 32-bit ARM architecture, such as ARMv7-A, is the mostextensively used architecture in mobile devices.ARM architecture is the main hardware architecture for mostof the operating systems of mobile devices such as iOS,Android, Windows Phone, Windows RT, Bada, BlackberryOS/Blackberry10, MeeGo, FirefoxOS, Tizen, UbuntuTouch, Sailfish and Igelle OS.3. COMPARATIVE STUDY OFCONTEMPORARY MOBILE PHONEPROCESSORSARM Cortex, Snapdragon, Nvidia Tegra are among the mostwidely used mobile processors.3.1 ARM Cortex ProcessorsARM Cortex processors cores are categorized into thefollowing variants: Cortex-A Processors (ARM Application Processors) Cortex-R Processors (ARM Embedded Real-timeProcessors) Cortex-M Processors (ARM Embedded Processors)36