Mailbox V2.1 LogiCORE IP Product Guide (PG114)
Mailbox v2.1LogiCORE IP Product GuideVivado Design SuitePG114 April 4, 2018
Table of ContentsIP FactsChapter 1: OverviewFeature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 2: Product SpecificationStandards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Chapter 3: Designing with the CoreGeneral Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20202021Chapter 4: Design Flow StepsCustomizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22262727Appendix A: Migrating and UpgradingMigrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Appendix B: DebuggingFinding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback2
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Appendix C: Application Software DevelopmentDevice Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Appendix D: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback34343535363
IP FactsIntroductionLogiCORE IP Facts TableIn a multiprocessor environment, theprocessors need to communicate data witheach other. The easiest method is to set upinter-processor communication through amailbox. The Mailbox core features abidirectional communication channel betweentwo processors. The Mailbox core can beconnected to the processor either throughAXI4-Lite or AXI4-Stream interfaces. Theinterfaces are available for connection to any IPthat supports them, for example MicroBlaze .Core SpecificsSupportedDevice Family(1)UltraScale UltraScale Zynq -7000 All Programmable SoC7 SeriesSupported UserInterfacesAXI4-Lite, AXI4-StreamResourcesProvided with CoreDesign FilesNot ProvidedTest BenchNot ProvidedConstraints FileNot ProvidedSimulationModel SupportedS/W Driver (2)Configurable depth of mailboxDesign Entry Configurable interrupt thresholds andmaskable interruptsSimulation Standalone driver: mboxVivado Design SuiteFor supported simulators, see theXilinx Design Tools: Release Notes GuideSynthesisConfigurable synchronous or asynchronousoperationBidirectional communicationVHDL BehavioralTested Design Flows(3) Vivado: RTLExample DesignFeaturesSupports AXI4-Lite and AXI4-Streamindependently on each of the portsPerformance and Resource Utilization web pageVivado SynthesisSupportProvided by Xilinx at the Xilinx Support web pageNotes:1. For a complete listing of supported devices, see the Vivado IPcatalog.2. Standalone driver details can be found in the SDK directory( install directory /SDK/ release /data/embeddedsw/doc/xilinx drivers.htm). Linux OS and driver support informationis available from the Xilinx Wiki page.3. For the supported versions of the tools, see theXilinx Design Tools: Release Notes Guide.LogiCORE IP Mailbox v2.1PG114 April 4, 20184Product SpecificationSend Feedbackwww.xilinx.com
Chapter 1OverviewThe Mailbox core is used for bidirectional inter-processor communication. A mailbox is alink between two otherwise separate processor systems. Other multi-port IP blocks, such asa memory controller, can also be shared by the two sub systems.In addition to sending the actual data between processors, the Mailbox core can be used togenerate interrupts between the processors.The Mailbox core in a typical AXI4-Lite system is shown in the top-level block diagram inFigure 1-1. The AXI4-Stream option has the Mailbox core interface connected directly to amaster with no bus in between.X-Ref Target - Figure 1-1System No. 1AXI4-LiteProcessorNumber 1Mailbox CoreLocal IPs forSystem No. 1Figure 1-1:LogiCORE IP Mailbox v2.1PG114 April 4, 2018System No. 2AXI4-LiteOtherMulti-port IPsProcessorNumber 2Local IPs forSystem No. 2Mailbox Core in an AXI4-Lite Systemwww.xilinx.comSend Feedback5
Chapter 1: OverviewFeature SummaryBus InterfacesThe Mailbox core has two bus interfaces to access the internal resources, usually connectedto different processors in a multi-processor system. Both interfaces can be independentlyconfigured to use an AXI4-Lite or AXI4-Stream interface.RegistersThe Mailbox core provides several types of registers, available with the AXI4-Lite businterface, to exchange information and handle interrupts: Read and Write Data registers, which provide the primary way to transfer data with theMailbox core. These registers act as a FIFO, to allow data transfers from one processor(writing to the FIFO) to the other (reading from the FIFO). The FIFO size can beconfigured to hold from 16 up to 8192 values. Status and control registers, to determine FIFO and interrupt threshold status. Interrupt registers, which control the behavior of interrupts, in particular FIFO fillthresholds to determine when an interrupt is generated.Streaming AccessWhen using the AXI4-Stream bus interface, data transfer FIFOs are available to read from orwrite to an interface. It is possible to check if the FIFO is full before writing or empty beforereading, by using a non-blocking test instruction (for example, tnput or tnget).Licensing and OrderingThis Xilinx LogiCORE IP module is provided at no additional cost with the XilinxVivado Design Suite under the terms of the Xilinx End User License. Information aboutthis and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Propertypage. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback6
Chapter 2Product SpecificationStandardsThe Mailbox core adheres to the ARM AMBA AXI and ACE Protocol Specification [Ref 1].The Mailbox core adheres to the ARM AMBA AXI4-Stream Protocol Specification [Ref 2].PerformanceThe frequency and latency of the Mailbox core are optimized for use with MicroBlaze . Thismeans that the frequency targets are aligned to MicroBlaze targets.Maximum FrequenciesFor details about performance, visit Performance and Resource Utilization.Latency and ThroughputThe latency and throughput of accesses to the Mailbox core FIFO depends on the businterface. The latency for each interface when reading or writing, as well as the throughput,is shown in Table 2-1, according to the parameter settings affecting the measurements.Table 2-1:Latency and ThroughputBus InterfaceRead Latency(clock cycles)MinimumTypicalWrite Latency(clock cycles)MinimumTypicalThroughput(clock cycles/word)MinimumTypicalSynchronous Distributed RAM (C ASYNC CLKS 0, C IMPL STYPE us Block RAM or Ultra RAM (C ASYNC CLKS 0, C IMPL STYPE 1 or 2):AXI4-Lite312413725AXI4-Stream110111221LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback7
Chapter 2: Product SpecificationTable 2-1:Latency and Throughput (Cont’d)Bus InterfaceRead Latency(clock cycles)MinimumTypicalWrite Latency(clock cycles)MinimumTypicalThroughput(clock cycles/word)MinimumTypicalAsynchronous Distributed RAM (C ASYNC CLKS 1, C IMPL STYPE nous Block RAM (C ASYNC CLKS 1, C IMPL STYPE 1):AXI4-Lite3124131129AXI4-Stream110111225The minimum number only takes into account the effect of the hardware implementation,whereas the typical value also accounts for the typical default software driver overhead.The throughput denotes the time for one write access followed by one read access. Ifseveral writes and reads are performed, they might partly overlap. As the number ofaccesses increases, this overlap causes the throughput to approach the access latency.When using the AXI4-Stream interface, the software can be optimized by reading or writingseveral words in sequence, but in this case care must be taken to avoid stalls due tointermediate instructions. The stream instructions must be consecutive to achieve theminimum latency.Resource UtilizationFor details about resource utilization, visit Performance and Resource Utilization.Port DescriptionsThe Mailbox core has two interfaces that are used to connect to the rest of the system. Bothinterfaces can be independently configured to use the AXI4-Lite or AXI4-Stream interface.The signal descriptions are included in three tables:1. The AXI4-Lite signals are described in Table 2-2.2. The AXI4-Stream signals are described in Table 2-3.3. The common signals are described in Table 2-4.All signals in Table 2-2 through Table 2-4 apply to both interface sides; x denotes theinterface number, which can be 0 or 1.LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback8
Chapter 2: Product SpecificationTable 2-2:AXI4-Lite I/O Signal DescriptionPortInitialInterface I/O StateSignal NameDescriptionSystem SignalsP43S x AXI ACLKSystemI-AXI clockP44S x AXI ARESETNSystemI-AXI reset, active-LowAXI Write Address Channel SignalsP45S x AXI AWADDR[C S x AXI ADDR WIDTH-1:0]AXII-AXI write address. The write addressbus gives the address of the writetransaction.P46S x AXI AWVALIDAXII-Write address valid. This signalindicates that valid write address isavailable.P47S x AXI AWREADYAXIO0Write address ready. This signalindicates that the slave is ready toaccept an address.AXI Write Channel SignalsP48S x AXI WDATA[C S x AXI DATA WIDTH - 1: 0]AXII-Write dataP49S x AXI WSTB[C S x AXI DATA WIDTH/8-1:0] (1)AXII-Write strobes. This signal indicateswhich byte lanes to update inmemory.(1)P50S x AXI WVALIDAXII-Write valid. This signal indicates thatvalid write data and strobes areavailable.P51S x AXI WREADYAXIO0Write ready. This signal indicates thatthe slave can accept the write data.AXI Write Response Channel SignalsWrite response. This signal indicatesthe status of the write transaction.P52S x AXI BRESP[1:0]AXIO0x0P53S x AXI BVALIDAXIO0Write response valid. This signalindicates that a valid write response isavailable.P54S x AXI BREADYAXII-Response ready. This signal indicatesthat the master can accept theresponse information.00 - OKAY10 - SLVERR11 - DECERRAXI Read Address Channel SignalsP55S x AXI ARADDR[C S x AXI ADDR WIDTH -1:0]LogiCORE IP Mailbox v2.1PG114 April 4, 2018AXIIwww.xilinx.com-Read address. The read address busgives the address of a read transaction.Send Feedback9
Chapter 2: Product SpecificationTable 2-2:AXI4-Lite I/O Signal Description (Cont’d)PortSignal NameInterface I/O InitialStateDescriptionP56S x AXI ARVALIDAXII-Read address valid. This signalindicates, when High, that the readaddress is valid and remains stableuntil the address acknowledge signal,S x AXI ARREADY, is High.P57S x AXI ARREADYAXIO1Read address ready. This signalindicates that the slave is ready toaccept an address.AXI Read Data Channel SignalsP58S x AXI RDATA[C S x AXI DATA WIDTH -1:0]AXIO0x0Read dataRead response. This signal indicatesthe status of the read transfer.P59S x AXI RRESP[1:0]AXIO0x0P60S x AXI RVALIDAXIO0Read valid. This signal indicates thatthe required read data is available andthe read transfer can completeP61S x AXI RREADYAXII-Read ready. This signal indicates thatthe master can accept the read dataand response information00 - OKAY10 - SLVERR11 - DECERRNotes:1. This signal is not used. The Mailbox core assumes that all byte lanes are active.Table 2-3:PortAXI4-Stream I/O Signal DescriptionSignal NameInterface I/O InitialStateDescriptionSystem SignalsP62S x AXIS ACLKSystemI-AXI clockP63M x AXIS ACLKSystemI-AXI clockAXI Slave Channel SignalsP64S x AXIS TDATA[C S x AXIS DATA WIDTH - 1: 0]AXISI-DataP65S x AXIS TLASTAXISI-Last data flag, indicates that this is the lastword.P66S x AXIS TVALIDAXISI-Data valid. This signal indicates that validdata and last flag are available.P67S x AXIS TREADYAXISO0Data ready. This signal indicates that theslave can accept the data.LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback10
Chapter 2: Product SpecificationTable 2-3:AXI4-Stream I/O Signal Description (Cont’d)PortInterface I/O InitialStateSignal NameDescriptionAXI Master Channel SignalsP68M x AXIS TDATA[C M x AXIS DATA WIDTH -1:0]AXISO0x0P69M x AXIS TLASTAXISO0Last data flag, indicates that this is the lastword.P70M x AXIS TVALIDAXISO0Data valid. This signal indicates that validdata and last flag are available.P71M x AXIS TREADYAXISI-Data ready. This signal indicates that theslave can accept the data.Table 2-4:DataMailbox Common I/O Signal DescriptionPort Signal Name Interface I/OInitialStateDescriptionCommon Interface SignalsP82P83FSL ClkSYS RstSystemSystemIIN/AThis is the input clock to the Mailbox core when used insynchronous FIFO mode (C ASYNC CLKS 0) and bothinterfaces are AXI4-Stream based(C INTERCONNECT PORT x 4). The FSL Clk is in this caseused to clock the core, in all other cases the internal Mailboxcore clock is automatically derived from S x AXI ACLK.N/AExternal system reset. This signal is only required when bothinterfaces are configured to be streaming interfaces(AXI4-Stream). If any AXI4-Lite interface is available this signalis optional.Common SignalsP85Interrupt 0SystemO0Interrupt signal that data is available at interface 0P86Interrupt 1SystemO0Interrupt signal that data is available at interface 1LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback11
Chapter 2: Product SpecificationRegister SpaceEach interface of the Mailbox core has the same set of information registers. Theinformation at each interface is not identical but rather localized for that interface becausethe communication is bidirectional.Table 2-5 shows all the Mailbox core registers and their addresses for AXI4-Lite case. Muchof the information can be acquired for the AXI4-Stream case with the use ofS x AXIS TREADY and M x AXIS TVALID.Table 2-5:Mailbox RegistersBase Address Offset (hex)Register Access DefaultNameType Value (hex)DescriptionBASEADDR 0x0WRDATAWriteN/AWrite Data address. Write only.BASEADDR 0x4ReservedN/AN/AReserved for future useBASEADDR 0x8RDDATAReadN/ARead Data address. Read onlyBASEADDR 0xCReservedN/AN/AReserved for future useBASEADDR 0x10STATUSRead0x1Status flags for Mailbox core. Read only.BASEADDR 0x14ERRORRead0x0Error flags, clear on read. Read only.BASEADDR 0x18SIT--Send Interrupt Threshold. Read/WriteBASEADDR 0x1CRIT--Receive Interrupt Threshold. Read/WriteBASEADDR 0x20IS--Interrupt Status register. Read/WriteBASEADDR 0x24IE--Interrupt Enable register. Read/WriteBASEADDR 0x28IP--Interrupt Pending register. Read onlyBASEADDR 0x2CCTRLWriteN/ABASEADDR 0x30Reserved--Reserved for future useBASEADDR 0x34Reserved--Reserved for future useBASEADDR 0x38Reserved--Reserved for future useBASEADDR 0x3CReserved--Reserved for future useLogiCORE IP Mailbox v2.1PG114 April 4, 2018Control Register. Write only.www.xilinx.comSend Feedback12
Chapter 2: Product SpecificationWrite Data Register (WRDATA)Writing to this register results in the data being transferred to the RDDATA register at theother interface. Trying to write while the full flag is set results in an error and theFULL ERROR bit is set. The register is write only and a read request issued to WRDATA isignored. Bit assignment in the WRDATA register is described in Table 2-7.Table 2-6:Write Data RegisterWRDATA310Table 2-7:Mailbox Write Data Register Bit ATAWrite-DescriptionWrite register to send data to the other interfaceMailbox Read Data Register (RDDATA)Reading from this register pops one value from the mail FIFO. Trying to read while theempty flag is set results in an error and the EMPTY ERROR bit is set. The register is read onlyand a write request issued to RDDATA is ignored. Bit assignment in the RDDATA register isdescribed in Table 2-9.Table 2-8:Read Data RegisterRDDATA310Table 2-9:Mailbox Read Data Register Bit DefinitionsBit(s)Name31–0RDDATALogiCORE IP Mailbox v2.1PG114 April 4, 2018Core ResetAccess ValueRead-DescriptionRead register to get data word sent from the other interfacewww.xilinx.comSend Feedback13
Chapter 2: Product SpecificationMailbox Status Register (STATUS)The Mailbox Status Register contains the current status of the Mailbox core. The register isread only and a write request issued to STATUS is ignored. Bit assignment in the STATUSregister is described in Table 2-11.Table 2-10:Status RegisterReserved314Table 2-11:Name31–4Reserved2STAFullEmpty3210Mailbox Status Register Bit DefinitionsBit(s)3RTARTASTACore ResetAccess ValueDescriptionReserved for future useReadRead00Receive Threshold Active indicates the current FIFO status of thisinterface in the receive direction0 The receive FIFO level is less than or equal to the RIT threshold1 The receive FIFO level is greater than the RIT thresholdSend Threshold Active indicates the current FIFO status of thisinterface in the send direction0 The send FIFO level is greater than the SIT threshold1 The send FIFO level is less than or equal to the SIT thresholdIndicates the current status of this interface in the send direction1FullRead00 There is room for more data1 The FIFO is full; any attempts to write data are ignored and anerror is generatedIndicates the current status of this interface in the receive direction0EmptyLogiCORE IP Mailbox v2.1PG114 April 4, 2018Read10 There is data available1 The FIFO is empty, any attempts to read data are ignored and anerror is generatedwww.xilinx.comSend Feedback14
Chapter 2: Product SpecificationMailbox Error Register (ERROR)The Mailbox Error Register contains the error flags for AXI4-Lite accesses from thisinterface. The error register is cleared at read, this means that all bits are sticky and thatthey indicate any errors that occurred since last time the error register was read. Theregister is read only and a write request issued to ERROR is ignored. Bit assignment in theERROR register is described in Table 2-13.Table 2-12:Error RegisterReserved312Table 2-13:FullErrorEmptyError10Mailbox Error Register Bit DefinitionsCore ResetAccess ValueBit(s)Name31–2ReservedReserved for future useFull ErrorIndicates if there has been any attempts to write to the WRDATAregister while the Full flag was asserted since the error register waslast read1Read0Description0 No error has occurred1 One or more attempts to write while Mailbox FIFO is full0EmptyErrorRead0Indicates if there has been any attempts to read from the RDDATAregister while the Empty flag was asserted since the error registerwas last read0 No error has occurred1 One or more attempts to read while Mailbox FIFO is emptyMailbox Send Interrupt Threshold Register (SIT)The Mailbox Send Interrupt Threshold Register contains the interrupt threshold for thisinterface in the send direction. Depending on the send FIFO data level writing a new SIT cancause a rising edge on STA that can generate a STI interrupt if it is enabled in the IE register.Bit assignment in the SIT register is described in Table 2-15.Table 2-14:SIT RegisterSIT31Log2(C MAILBOX DEPTH)-1Table 2-15:0Mailbox SIT Register Bit onLog2(C MAILBOX DEPTH)SITRead/Write0Lower Log2(C MAILBOX DEPTH) bits used, rightjustified to bit 0LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback15
Chapter 2: Product SpecificationMailbox Receive Interrupt Threshold Register (RIT)The Mailbox Receive Interrupt Threshold Register contains the interrupt threshold for thisinterface in the receive direction. Depending on the receive FIFO data level writing a newRIT can cause a rising edge on RTA that can generate a RTI interrupt if it is enabled in theIE register. Bit assignment in the RIT register is described in Table 2-17.Table 2-16:RIT RegisterRIT31Log2(C MAILBOX DEPTH)-1Table 2-17:0Mailbox RIT Register Bit DefinitionsBit(s)NameCoreAccessResetValueLog2(C MAILBOX DEPTH)RITRead/Write0DescriptionLower Log2(C MAILBOX DEPTH) bits used,right justified to bit 0Mailbox Interrupt Status Register (IS)The Mailbox Interrupt Status Register contains the current interrupt status for this interface.There are three types of interrupts that can be generated. Mailbox Error interrupt aregenerated when any of the bits in the ERROR register is set. The other two interrupts areFIFO related: RTI is generated for a rising edge on the RTA bit in the STATUS register and STIthat is generated for a rising edge on the STA STATUS register bit. RTI and STI are used toindicate that it is time to read from or write to the FIFOs to avoid any stalls in the data flow.Bit assignment in the IS register is described in Table 2-19.Table 2-18:IS RegisterReserved313Table 2-19:ERRRTISTI210Mailbox IS Register Bit ValueDescriptionReserved for future useMailbox Error Interrupt Status for this interface.Values for read:2ERRRead/Write00 No interrupt event has occurred.1 A Mailbox error has occurred.Values for write:0 No change1 Acknowledge and clear the interrupt if it is activeLogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback16
Chapter 2: Product SpecificationTable 2-19:Bit(s)Mailbox IS Register Bit Definitions ox Receive Threshold Interrupt pending status for thisinterface.Values for read:1RTIRead/Write00 No interrupt event has occurred.1 Data level in the receive FIFO has caused a RTI.Values for write:0 No change1 Acknowledge and clear the interrupt if it is activeMailbox Send Threshold Interrupt pending status for thisinterface.Values for read:0STIRead/Write00 No interrupt event has occurred.1 Data level in the send FIFO has caused a STI.Values for write:0 No change1 Acknowledge and clear the interrupt if it is activeMailbox Interrupt Enable Register (IE)The Mailbox Interrupt Enable Register contains the mask for the allowed interrupts on thisinterface. Bit assignment in the IE register is described in Table 2-21.Table 2-20:IE RegisterReserved313Table 2-21:ERRRTISTI210Mailbox IE Register Bit ValueDescriptionReserved for future useMailbox Error Interrupt Enable for this ite00 ERR interrupt is disabled1 ERR interrupt is enabledMailbox Receive Threshold Interrupt Enable for this interface0 RTI interrupt is disabled1 RTI interrupt is enabledMailbox Send Threshold Interrupt Enable for this interfaceLogiCORE IP Mailbox v2.1PG114 April 4, 20180 STI interrupt is disabled1 STI interrupt is enabledwww.xilinx.comSend Feedback17
Chapter 2: Product SpecificationMailbox Interrupt Pending Register (IP)The Mailbox Interrupt Pending Register contains the currently pending interrupts from thisinterface. It is a read only register generated by performing a bitwise AND between the ISand IE registers. A write request issued to the IP is ignored. Bit assignment in the IP registeris described in Table 2-23. All the bits in this register are OR’d together to generate theinterrupt output signal for this interface. When an interrupt has been serviced it isacknowledged by writing the corresponding bit to the IS Register.Table 2-22:IP RegisterReserved313Table 2-23:ERRRTISTI210Mailbox IP Register Bit DefinitionsBit(s)Name31–3ReservedCore ResetAccess ValueDescriptionReserved for future useMailbox Error Interrupt Pending status for this interface2ERRRead00 No pending interrupt1 Pending interrupt for Mailbox errorsMailbox Receive Threshold Interrupt Pending status for this interface1RTIRead00 No pending interrupt1 Pending interrupt for data level in receive FIFOMailbox Send Threshold Interrupt Pending status for this interface0STIRead00 No pending interrupt1 Pending interrupt for data level in send FIFOMailbox Control Register (CTRL)The Mailbox Control Register is used to clear (reset) the Receive and Send FIFO from eachinterface. This can be useful to ensure that no stale data remains in the FIFO, for examplewhen resetting or restarting software on a processor connected to the Mailbox. It is a writeonly register. A read request issued to the CTRL register is ignored. Bit assignment in theCTRL register is described in Table 2-25.Table 2-24:CTRL RegisterReserved31LogiCORE IP Mailbox v2.1PG114 April 4, 20182www.xilinx.comCRFCSF10Send Feedback18
Chapter 2: Product SpecificationTable 2-25:Mailbox CTRL Register Bit DefinitionsBit(s)Name31–2ReservedCore ResetAccess ValueDescriptionReserved for future useClear Mailbox receive FIFO for this interface1CRFWrite-0CSFWrite-0 Do nothing1 Clear receive FIFOClear Mailbox send FIFO for this interfaceLogiCORE IP Mailbox v2.1PG114 April 4, 20180 Do nothing1 Clear send FIFOwww.xilinx.comSend Feedback19
Chapter 3Designing with the CoreGeneral Design GuidelinesThis chapter includes guidelines and additional information to facilitate designing with thecore.ClockingThe Sn AXI ACLK (n 0, 1) input is only used when the AXI4-Lite interconnect is used.Then it should normally be connected to the same clock as the interconnect.The Mn AXIS ACLK or Sn AXIS ACLK (n 0, 1) are only used when AXI4-Stream is used.Then they should be connected to the corresponding stream clock.With synchronous operation (C ASYNC CLKS 0), the two clock inputs used must both beconnected to the same clock signal in all the cases above.The FSL Clk input is only used with synchronous operation (C ASYNC CLKS 0) andwhen both interfaces use AXI4-Stream. Then it should be connected to the commonAXI4-Stream clock signal.ResetsThe Sn AXI ARESETN (n 0, 1) input is only used when the AXI4-Lite interconnect is used.Then it should normally be connected to the same reset as the interconnect.The SYS Rst input is necessary when both interfaces use AXI4-Stream, because thestreaming interfaces do not have dedicated resets.All enabled reset signals are treated equally and reset the entire Mailbox core, including anyAXI4-Lite interfaces. With asynchronous operation (C ASYNC CLKS 1) synchronization ofthe reset signals to the different clock domains is handled automatically internally.IMPORTANT: It is recommended that the reset signals are asserted for at least 16 clock cycles of theslowest clock connected to the Mailbox core.LogiCORE IP Mailbox v2.1PG114 April 4, 2018www.xilinx.comSend Feedback20
Chapter 3: Designing with the CoreProtocol DescriptionSee the ARM AMBA AXI and ACE Protocol Specification [Ref 1] for a description of theAXI4-Lite protocol.See the ARM AMBA AXI4-Stream Protocol Specification [Ref 2] for a
LogiCORE IP Mailbox v2.1 5 PG114 April 4, 2018 www.xilinx.com Chapter 1 Overview The Mailbox core is used for bidirectional inter-processor communication. A mailbox is a link between two otherwise separate processor sy stems. Other multi-port IP blocks, such as a memory controller, can also be shared by the two sub systems.
Scenario 2: Restoring a Mailbox Database to a Recovery Database without Mailbox Recovery. 32. Scenario 3: Restoring a Mailbox Database to a Recovery Database with the Mailbox Recovery. Scenario 3: Restoring a Mailbox Database to a Recovery Database with the Mailbox Recovery. 33. Scenario 4: Restoring Mailboxes with the Mailbox Recovery Wizard. 35
LogiCORE IP Mailbox (v1.00a) Functional Description The Mailbox is used for bi-directional inter-processor communication. A mailbox is a link between two otherwise separate processor systems. Other multi-port IP blocks, such as a memory controller, may also be shared by the two sub systems.
Export GroupWise Mailbox into live exchange Public Folder. 12. Export GroupWise Mailbox into live exchange Archive Mailbox. 13. Export GroupWise Mailbox into office 365 public Folder. 14. Export GroupWise Mailbox into office 365 Archive Mailbox. 15. Supports GW-2014, GW-2014, GW-8.0, GW
T erms and conditions for pr oduct documentation . . 40 . iv Sterling B2B Integrator: Mailbox. Mailbox Mailbox of fers document r epositories accessible only to specific users and applications. Use the Mailbox when it is necessary to stor e messages and documents for pr ocessing at a later time.
LogiCORE IP Multi-Port Memory Controller (v6.06.a) DS643 February 22, 2013 Product Specification LogiCORE IP Facts Table Core Specifics Supported Device Family(1) 1. For a complete list of supported derivative devices, see Embedded Edition Derivative Device Support. Virtex-6(2), Spartan-6, Virtex-5, Spartan-3/3A/3E/3AN/3A DSP, Virtex-4 2.
AXI4 Memory Map and AXI4-Lite interfaces Supports connection to AXI3 Protocol Cores LogiCORE IP ChipScope AXI Monitor (v3.02.a) DS810 January 18, 2012 Product Specification LogiCORE IP Facts Table Core Specifics Supported Device Family (1) Virtex -7, Kintex -7(6), Virtex-6(3), Spartan -6(4) Supported User Interfaces AXI4, AXI4-Lite .
6 Family/ Extension Mailbox Set-up Create your extension(s): 1 Set up your Main mailbox as instructed above in 2) “First Time Set-up”. 2 Then create the extension(s) you require. This must be done via the Web. a) Go to strong voicemail /strong .telus.com b) Login using your Main mailbox passcode. c) Go to Profile, strong Voicemail /strong , Family Mailbox d) Select Add to create 1, 2 or 3 extension mailboxes
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