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LogiCORE IP Mailbox (v1.00a)DS776 September 21, 2010Product SpecificationIntroductionLogiCORE IP Facts TableIn a multiprocessor environment, the processors needto communicate data with each other. The easiestmethod is to set up inter-processor communicationthrough a mailbox. Mailbox features a bi-directionalcommunication channel between two processors. TheMailbox can be connected to the processor eitherthrough a PLB, AXI4-Lite, AXI4-Stream, or FSLinterface. The PLB interface option is available for theMicroBlaze processor, PowerPC processor, or anyother PLBv46 master. The AXI4-Lite, AXI4-Stream, andFSL options are available for connection to any IP thatsupports them, for example MicroBlaze.Core SpecificsSupportedDevice Family(1Spartan -3, Spartan-3E, Spartan-6,Spartan-3A/3AN/3A DSP, Virtex -4, Virtex-5,Virtex-6Supported UserInterfacesAXI lite, PLBLUTsResources UsedFFsDSPSlicesFMAX(MHz)See Table 27.BlockRAMs0Provided with CoreDocumentationProduct SpecificationDesign FilesVHDLExample DesignNot ProvidedTest BenchNot ProvidedFeaturesConstraints FileNot Provided Supports AXI4-Lite, AXI4-Stream, PLB v4.6 andFSL independently on each of the portsSimulation Model Configurable depth of mailbox Configurable interrupt thresholds and maskableinterruptsDesign EntryTools Configurable synchronous or asynchronousoperationMentor Graphics ModelSim v6.5c and aboveTested Design ToolsSimulationXPS 12.3Mentor Graphics ModelSim v6.5cSynthesis ToolsISE 12.3SupportProvided by Xilinx, Inc.Bi-directional communication1.For a complete listing of supported devices, see the release notes for thiscore. Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx in theUnited States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. AMBA, AMBA Designer, ARM,ARM1176JZ-S, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners.DS776 September 21, 2010Product Specificationwww.xilinx.com1

LogiCORE IP Mailbox (v1.00a)Functional DescriptionThe Mailbox is used for bi-directional inter-processor communication. A mailbox is a link between two otherwiseseparate processor systems. Other multi-port IP blocks, such as a memory controller, may also be shared by the twosub systems.In addition to sending the actual data between processors, the mailbox can be used to generate interrupts betweenthe processors.The Mailbox in a typical PLBv46 system is shown in the top-level block diagram in Figure 1. The same systempartitioning is also used for AXI4-Lite interface option. FSL and AXI4-Stream options will have the Mailboxinterface connected directly to a master with no bus inbetween.X-Ref Target - Figure 1System No. 1PLBv46 BusSystem No. 2PLBv46 BusProcessorNumber 1MailboxLocal IPs forSystem Number 1OtherMulti-port IPsProcessorNumber 2Local IPs forSystem Number 2DS776 01Figure 1: Mailbox in a PLBv46 SystemMailbox I/O SignalsThe Mailbox has two interfaces that are used to connect to the rest of the system. Both interfaces can beindependently configured to use the PLBv46, AXI4-Lite, AXI4-Stream, or FSL interface. The signal descriptions areincluded in five tables:1. The PLB signals are described in Table 1.2. The AXI4-Lite signals are described in Table 2.3. The AXI4-Stream signals are described in Table 3.4. The FSL signals are described in Table 4.5. The common signals are described in Table 5.All signals in Table 1 through Table 4 apply to both interface sides; x denotes the interface number, which may be0 or 1.DS776 September 21, 2010Product Specificationwww.xilinx.com2

LogiCORE IP Mailbox (v1.00a)Table 1: PLBv46 I/O Signal DescriptionPortSignal NameInterfaceI/OInitialStateDescriptionSystem SignalsP1SPLB x ClkSystemI-PLB clockP2SPLB x RstSystemI-PLB reset, active highPLB Interface SignalsP3PLB x ABus[0:31]PLBI-PLB address busP4PLB x PAValidPLBI-PLB primary address validP5PLB x masterID[0:C SPLB x MID WIDTH - 1]PLBI-PLB current master identifierP6PLB x RNWPLBI-PLB read not writeP7PLB x BE[0:(C SPLB x DWIDTH/8) - 1]PLBI-PLB byte enablesP8PLB x size[0:3]PLBI-PLB size of requested transferP9PLB x type[0:2]PLBI-PLB transfer typeP10PLB x wrDBus[0:C SPLB x DWIDTH - 1]PLBI-PLB write data busUnused PLB Interface SignalsP11PLB x UABus[0:31]PLBI-PLB upper address bitsP12PLB x SAValidPLBI-PLB secondary address validP13PLB x rdPrimPLBI-PLB secondary to primary read requestindicatorP14PLB x wrPrimPLBI-PLB secondary to primary write requestindicatorP15PLB x abortPLBI-PLB abort bus requestP16PLB x busLockPLBI-PLB bus lockP17PLB x MSize[0:1]PLBI-PLB data bus width indicatorP18PLB x lockErrPLBI-PLB lock errorP19PLB x wrBurstPLBI-PLB burst write transferP20PLB x rdBurstPLBI-PLB burst read transferP21PLB x wrPendReqPLBI-PLB pending bus write requestP22PLB x rdPendReqPLBI-PLB pending bus read requestP23PLB x wrPendPri[0:1]PLBI-PLB pending write request priorityP24PLB x rdPendPri[0:1]PLBI-PLB pending read request priorityP25PLB x reqPri[0:1]PLBI-PLB current request priorityP26PLB x TAttribute[0:15]PLBI-PLB transfer attributePLB Slave Interface SignalsP27Sl x addrAckPLBO0Slave address acknowledgeP28Sl x SSize[0:1]PLBO0Slave data bus sizeDS776 September 21, 2010Product Specificationwww.xilinx.com3

LogiCORE IP Mailbox (v1.00a)Table 1: PLBv46 I/O Signal Description (Cont’d)PortSignal NameInterfaceI/OInitialStateDescriptionP29Sl x waitPLBO0Slave waitP30Sl x rearbitratePLBO0Slave bus rearbitrateP31Sl x wrDAckPLBO0Slave write data acknowledgeP32Sl x wrCompPLBO0Slave write transfer completeP33Sl x rdDBus[0:C SPLB x DWIDTH - 1]PLBO0Slave read data busP34Sl x rdDAckPLBO0Slave read data acknowledgeP35Sl x rdCompPLBO0Slave read transfer completeP36Sl x MBusy[0:C SPLB x NUM MASTERS - 1]PLBO0Slave busyP37Sl x MWrErr[0:C SPLB x NUM MASTERS - 1]PLBO0Slave write errorP38Sl x MRdErr[0:C SPLB x NUM MASTERS - 1]PLBO0Slave read errorUnused PLB Slave Interface SignalsP39Sl x wrBTermPLBO0Slave terminate write burst transferP40Sl x rdWdAddr[0:3]PLBO0Slave read word addressP41Sl x rdBTermPLBO0Slave terminate read burst transferP42Sl x MIRQ[0:C SPLB x NUM MASTERS - 1]PLBO0Master interrupt requestInterfaceI/OInitialStateTable 2: AXI4-Lite I/O Signal DescriptionPortSignal NameDescriptionSystem SignalsP43S x AXI ACLKSystemI-AXI ClockP44S x AXI ARESETNSystemI-AXI Reset, active lowAXI Write Address Channel SignalsP45S x AXI AWADDR[C S x AXIADDR WIDTH-1:0]AXII-AXI Write address. The write address busgives the address of the write transaction.P46S x AXI AWVALIDAXII-Write address valid. This signal indicatesthat valid write address is available.P47S x AXI AWREADYAXIO0Write address ready. This signal indicatesthat the slave is ready to accept anaddress.AXI Write Channel SignalsP48S x AXI WDATA[C S x AXIDATA WIDTH - 1: 0]AXII-Write dataP49S x AXI WSTB[C S x AXIDATA WIDTH/8-1:0] (1)AXII-Write strobes. This signal indicates whichbyte lanes to update in memory.(1)DS776 September 21, 2010Product Specificationwww.xilinx.com4

LogiCORE IP Mailbox (v1.00a)Table 2: AXI4-Lite I/O Signal Description (Cont’d)PortSignal NameInterfaceI/OInitialStateDescriptionP50S x AXI WVALIDAXII-Write valid. This signal indicates that validwrite data and strobes are available.P51S x AXI WREADYAXIO0Write ready. This signal indicates that theslave can accept the write data.AXI Write Response Channel SignalsP52S x AXI BRESP[1:0]AXIO0x0Write response. This signal indicates thestatus of the write transaction.“00“ - OKAY“10“ - SLVERR“11“ - DECERRP53S x AXI BVALIDAXIO0Write response valid. This signal indicatesthat a valid write response is available.P54S x AXI BREADYAXII-Response ready. This signal indicatesthat the master can accept the responseinformation.AXI Read Address Channel SignalsP55S x AXI ARADDR[C S x AXI ADDR WIDTH -1:0]AXII-Read address. The read address busgives the address of a read transaction.P56S x AXI ARVALIDAXII-Read address valid. This signal indicates,when HIGH, that the read address is validand will remain stable until the addressacknowledge signal,S x AXI ARREADY, is high.P57S x AXI ARREADYAXIO1Read address ready. This signal indicatesthat the slave is ready to accept anaddress.AXI Read Data Channel SignalsP58S x AXI RDATA[C S x AXIDATA WIDTH -1:0]AXIO0x0Read dataP59S x AXI RRESP[1:0]AXIO0x0Read response. This signal indicates thestatus of the read transfer.“00“ - OKAY“10“ - SLVERR“11“ - DECERRP60S x AXI RVALIDAXIO0Read valid. This signal indicates that therequired read data is available and theread transfer can completeP61S x AXI RREADYAXII-Read ready. This signal indicates that themaster can accept the read data andresponse informationNotes:1.This signal is not used. The Mailbox assumes that all byte lanes are active.DS776 September 21, 2010Product Specificationwww.xilinx.com5

LogiCORE IP Mailbox (v1.00a)Table 3: AXI4-Stream I/O Signal DescriptionPortSignal NameInterfaceInitialStateI/ODescriptionSystem SignalsP62S x AXIS ACLKSystemI-AXI ClockP63M x AXIS ACLKSystemI-AXI ClockAXI Slave Channel SignalsP64S x AXIS TDATA[C S x AXIS DATA WIDTH - 1: 0]AXISI-DataP65S x AXIS TLASTAXISI-Last data flag, indicates that this is the last word.P66S x AXIS TVALIDAXISI-Data valid. This signal indicates that valid dataand last flag are available.P67S x AXIS TREADYAXISO0Data ready. This signal indicates that the slavecan accept the data.AXI Master Channel SignalsP68M x AXIS TDATA[C M x AXIS DATA WIDTH -1:0]AXISO0x0P69M x AXIS TLASTAXISO0Last data flag, indicates that this is the last word.P70M x AXIS TVALIDAXISO0Data valid. This signal indicates that valid dataand last flag are available.P71M x AXIS TREADYAXISI-Data ready. This signal indicates that the slavecan accept the data.DataTable 4: FSL I/O Signal DescriptionPortSignal NameInterfaceI/OInitialStateDescriptionFSL Master Interface SignalsP72FSL x M ClkMFSLIN/AThis port provides the input clock to the FSL masterinterface of the mailbox when used in the asynchronousFIFO mode (C ASYNC CLKS 1). All transactions onthe master interface use this clock when implemented inthe asynchronous modeP73FSL x M DataMFSLI0The data input to the FSL master interface of the mailboxP74FSL x M ControlMFSLI0Unused for mailboxP75FSL x M WriteMFSLI0Input signal that controls the write enable signal of theFSL master interface of the FIFO. When set to 1, thevalue of FSL x M Data is pushed into the mailboxFIFO on a rising clock edge.P76FSL x M FullMFSLON/AOutput signal on the FSL master interface of the FIFOindicating that the FIFO is full.FSL Slave Interface SignalsP77FSL x S ClkDS776 September 21, 2010Product SpecificationSFSLIN/AThis port provides the input clock to the FSL slaveinterface on the mailbox when used in the asynchronousFIFO mode (C ASYNC CLKS 1). All transactions onthe slave interface use this clock when implemented inthe asynchronous modewww.xilinx.com6

LogiCORE IP Mailbox (v1.00a)Table 4: FSL I/O Signal Description (Cont’d)PortSignal NameInterfaceI/OInitialStateDescriptionP78FSL x S DataSFSLON/AThe data output bus onto the FSL slave interface of themailboxP79FSL x S ControlSFSLON/AUnused for mailboxP80FSL x S ReadSFSLI0Input signal on the FSL slave interface that controls theread acknowledge signal of the FIFO. When set to 1, thevalue of FSL x S Data is popped from the FIFO on arising clock edge.P81FSL x S ExistsSFSLON/AOutput signal on the FSL slave interface indicating thatFIFO contains valid data.Table 5: Mailbox Common I/O Signal DescriptionPortSignal NameInterfaceI/OInitialStateDescriptionFSL Common Interface SignalsP82FSL ClkSystemIN/AThis is the input clock to the mailbox when used insynchronous FIFO mode (C ASYNC CLKS 0) and bothinterfaces are FSL based (C INTERCONNECT PORT x 3). The FSL Clk is in this case used to clock the core, in allother cases are the internal mailbox clock automaticallyderived from either SPLB x Clk, S x AXI ACLK orS x AXIS ACLK depending on the settings.'External system reset. This signal is only required when bothinterfaces are configured to be streaming interfaces (FSL orAXI4-Stream). If any PLB or AXI4-Lite interface is availablethis signal is optional.P83SYS RstSystemIN/AP84FSL RstSystemO0Output reset signal generated by the FSL reset logic. Anyperipherals connected to the FSL bus may use this resetsignal to operate the peripheral reset.Common SignalsP85Interrupt 0SystemO0Interrupt signal that data is available at interface 0P86Interrupt 1SystemO0Interrupt signal that data is available at interface 1DS776 September 21, 2010Product Specificationwww.xilinx.com7

LogiCORE IP Mailbox (v1.00a)ParametersTo allow the user to obtain a Mailbox that is uniquely tailored for the system, certain features can be parameterizedin the Mailbox design. This allows the user to configure a design that utilizes the resources required by the systemonly and that operates with the best possible performance. The features that can be parameterized in the Mailboxdesign are as shown in Table 6. The interface related generics, G3 through G19, are separately configured for eachinterface.Table 6: Mailbox Design ParametersGenericFeature/DescriptionParameter NameAllowable tem ParameterG1Target FPGA familyC FAMILYspartan3, aspartan3, spartan3e,aspartan3e, spartan3a, aspartan3a,spartan3adsp, aspartan3adsp,spartan6, aspartan6, spartan6l,qsspartan6, qsspartan6l, virtex4,qrvirtex4, qvirtex4, virtex5, qrvirtex5,virtex6, virtex6, virtex6l, qrvirtex6G2Level of external resetC EXT RESETHIGH0 or 1PLB ParametersG3PLB Base AddressC SPLB x BASEADDRValid Address(1)None(2)std logicvectorG4PLB High AddressC SPLB x HIGHADDRValid Address(3)None(2)std logicvectorG5PLB least significantaddress bus widthC SPLB x AWIDTH3232integerG6PLB data widthC SPLB x DWIDTH32, 64, 12832integerG7Selects point-to-point orshared bus topologyC SPLB x P2P0 Shared Bus Topology1 Point-to-Point Bus Topology(4)0integerG8PLB Master ID Bus WidthC SPLB x MIDWIDTHlog2(C SPLB NUMMASTERS) with a minimum value of11integerG9Number of PLB MastersC SPLB x NUMMASTERS1 - 161integerG10Support BurstsC SPLB x SUPPORT BURSTS00integerG11Width of the Slave DataBusC SPLB NATIVEDWIDTH3232integerG12Frequency of PLBinterfaceC SPLB x CLKFREQ HZinteger100 000000integerAXI4-Lite ParametersG13AXI Base AddressC S x AXIBASEADDRValid Address(1)None(2)std logicvectorG14AXI High AddressC S x AXIHIGHADDRValid Address(3)None(2)std logicvectorDS776 September 21, 2010Product Specificationwww.xilinx.com8

LogiCORE IP Mailbox (v1.00a)Table 6: Mailbox Design Parameters (Cont’d)GenericFeature/DescriptionParameter NameAllowable ValuesDefaultValueVHDLTypeG15AXI address bus widthC S x AXIADDR WIDTH3232integerG16AXI data bus widthC S x AXI DATAWIDTH3232integerG17AXI interface typeC S x AXIPROTOCOLAXI4LITEstringAXI4LITEAXI4-Stream ParametersG18AXI data bus widthC S x AXIS DATAWIDTH3232integerG19AXI data bus widthC M x AXIS DATA32WIDTH32integerMailbox ParametersG20Specify if interfaces aresynchronous orasynchronousC ASYNC CLKS0-10IntegerG21Use BRAMs to implementFIFOC IMPL STYLE0-11IntegerG22FSL bus widthC FSL DWIDTH3232IntegerG23Select interface type thatshall be used on port 0:1 - PLBv462 - AXI4-Lite3 - FSL4 - AXI4-StreamC INTERCONNECTPORT 01-40IntegerG24Select interface type thatshall be used on port 1:1 - PLBv462 - AXI4-Lite3 - FSL4 - AXI4-StreamC INTERCONNECTPORT 11-40IntegerG25FIFO depth of mailboxC MAILBOXDEPTH16IntegerDS776 September 21, 2010Product Specification16 - 8192www.xilinx.com9

LogiCORE IP Mailbox (v1.00a)Table 6: Mailbox Design Parameters (Cont’d)GenericFeature/DescriptionParameter NameG26Read Clock period forinterface 0 whenasynchronous LUTRAMis used (in ps)C READ CLOCKPERIOD 0G27Read Clock period forinterface 1whenasynchronous LUTRAMis used (in ps)C READ CLOCKPERIOD 0DefaultValueVHDLType 0 when enabled0Integer 0 when enabled0IntegerAllowable ValuesNotes:The user must set the values. The C interface BASEADDR must be a multiple of the range, where the range isC interface HIGHADDR - C interface BASEADDR 1.2. No default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler error will begenerated.3. C interface HIGHADDR - C interface BASEADDR must be a power of 2 greater than equal toC interface BASEADDR 0xFF.4. Value of ’1’ is not supported in this core.1.Parameter - Port DependenciesThe dependencies between the Mailbox core design parameters and I/O signals are described in Table 7. Inaddition, when certain features is deselected, the related logic will no longer be a part of the design. The unusedinput and output signals are set to a specified value.Table 7: Mailbox Parameter-Port DependenciesGenericor PortNameAffectsDependsRelationship DescriptionDesign ParametersG6C SPLB x DWIDTHP7, P10, P33-G8C SPLB x MID WIDTHG9Affects the number of bits in data busP5G9C SPLB x NUM MASTERSP36, P37,P38, P42-Affects the number of PLB mastersG15C S x AXI ADDR WIDTHP45, P55-Defines the width of the portsG16C S x AXI DATA WIDTHP48, P49,P58-Defines the width of the portsG18C S x AXIS DATA WIDTHP64-Defines the width of the portsG19C M x AXIS DATA WIDTHP68-Defines the width of the portsG22C FSL DWIDTHP73, P78-Affects the number of bits in data busThis value is calculated as:log2(C SPLB x NUM MASTERS) with aminimum value of 1I/O SignalsP5PLB x masterID[0:C SPLB x MID WIDTH - 1]-G8Width of the PLB x masterID variesaccording to C SPLB x MID WIDTHP7PLB x BE[0:(C SPLB x DWIDTH/8) -1]-G6Width of the PLB x BE varies according toC SPLB x DWIDTHP10PLB x wrDBus[0:C SPLB x DWIDTH - 1]-G6Width of the PLB x wrDBus variesaccording to C SPLB x DWIDTHDS776 September 21, 2010Product Specificationwww.xilinx.com10

LogiCORE IP Mailbox (v1.00a)Table 7: Mailbox Parameter-Port Dependencies (Cont’d)Genericor PortNameAffectsDependsRelationship DescriptionP33Sl x rdDBus[0:C SPLB x DWIDTH - 1]-G6Width of the Sl x rdDBus varies accordingto C SPLB x DWIDTHP36Sl x MBusy[0:C SPLB x NUM MASTERS - 1]-G9Width of the Sl x MBusy varies according toC SPLB x NUM MASTERSP37Sl x MWrErr[0:C SPLB x NUM MASTERS - 1]-G9Width of the Sl x MWrErr varies accordingto C SPLB x NUM MASTERSP38Sl x MRdErr[0:C SPLB x NUM MASTERS - 1]-G9Width of the Sl x MRdErr varies accordingto C SPLB x NUM MASTERSP42Sl x MIRQ[0:C SPLB x NUM MASTERS - 1]-G9Width of the Sl x MIRQ varies according toC SPLB x NUM MASTERSP45S x AXI AWADDR[C S x AXIADDR WIDTH-1:0]-G15Port width depends on the genericC S x AXI ADDR WIDTHP48S x AXI WDATA[C S x AXIDATA WIDTH-1:0]-G16Port width depends on the genericC S x AXI DATA WIDTHP49S x AXI WSTB[C S x AXIDATA WIDTH/8-1:0]-G16Port width depends on the genericC S x AXI DATA WIDTHP55S x AXI ARADDR[C S x AXIADDR WIDTH -1:0]-G15Port width depends on the genericC S x AXI ADDR WIDTHP58S x AXI RDATA[C S x AXIDATA WIDTH -1:0]-G16Port width depends on the genericC S x AXI DATA WIDTHP64S x AXIS TDATA[C S x AXISDATA WIDTH -1:0]-G18Port width depends on the genericC S x AXIS DATA WIDTHP68M x AXIS TDATA[C M x AXISDATA WIDTH -1:0]-G19Port width depends on the genericC M x AXIS DATA WIDTHP74FSL x M DataG22Width of the FSL x M Data variesaccording to C FSL DWIDTHP79FSL x S DataG22Width of the FSL x S Data varies accordingto C FSL DWIDTHRegister DescriptionsEach interface of the Mailbox core has the same set of information registers. The information at each interface is notidentical but rather localized for that interface since the communication is bi-directional.Table 8 shows all the Mailbox registers and their addresses for the PLB and AXI4-Lite cases. Much of theinformation can be acquired for the FSL and AXI4-Stream cases with the use of FSL x M Full/FSL x S Existsor S x AXIS TREADY/M x AXIS TVALID respectively.Table 8: Mailbox RegistersRegister NameAccess TypeDefault Value(hex)BASEADDR 0x0WRDATAWriteN/AWrite Data address. Write only.BASEADDR 0x4ReservedN/AN/AReserved for future useBASEADDR 0x8RDDATAReadN/ARead Data address. Read onlyBASEADDR 0xCReservedN/AN/AReserved for future useBase Address Offset(hex)DS776 September 21, 2010Product Specificationwww.xilinx.comDescription11

LogiCORE IP Mailbox (v1.00a)Table 8: Mailbox RegistersBase Address Offset(hex)Register NameAccess Type Default Value(hex)DescriptionBASEADDR 0x10STATUSRead0x1Status flags for mailbox. Read only.BASEADDR 0x14ERRORRead0x0Error flags, clear on read. Read only.BASEADDR 0x18SIT--Send Interrupt Threshold. Read/WriteBASEADDR 0x1CRIT--Receive Interrupt Threshold. Read/WriteBASEADDR 0x20IS--Interrupt Status register. Read/WriteBASEADDR 0x24IE--Interrupt Enable register. Read/WriteBASEADDR 0x28IP--Interrupt Pending register. Read onlyBASEADDR 0x2CReserved--Reserved for future useBASEADDR 0x30Reserved--Reserved for future useBASEADDR 0x34Reserved--Reserved for future useBASEADDR 0x38Reserved--Reserved for future useBASEADDR 0x3CReserved--Reserved for future useWrite Data Register (WRDATA)Writing to this register will result in the data transferred to the RDDATA register at the other interface. Trying towrite while the full flag is set will result in an error and the FULL ERROR bit will be set. The register is write onlyand a read request issued to WRDATA will be ignored. Bit assignment in the WRDATA register is described inTable 10.Table 9: Write Data RegisterWRDATA0C FSL DWIDTH-1Table 10: Mailbox Write Data Register Bit DefinitionsBit(s)NameCoreAccessResetValue0 - C FSL DWIDTH - 1WRDATAWrite-DescriptionWrite register to send data to the other interfaceMailbox Read Data Register (RDDATA)Reading from this register will pop one value from the mail FIFO. Trying to read while the empty flag is set willresult in an error and the EMPTY ERROR bit will be set. The register is read only and a write request issued toRDDATA will be ignored. Bit assignment in the RDDATA register is described in Table 12.Table 11: Read Data RegisterRDDATA0C FSL DWIDTH-1Table 12: Mailbox Read Data Register Bit on0 - C FSL DWIDTH - 1RDDATARead-Read register to get data word sent from the other interfaceDS776 September 21, 2010Product Specificationwww.xilinx.com12

LogiCORE IP Mailbox (v1.00a)Mailbox Status Register (STATUS)The Mailbox Status Register contains the current status of the mailbox. The register is read only and a write requestissued to STATUS will be ignored. Bit assignment in the STATUS register is described in Table 14Table 13: Status RegisterReserved027RTASTAFullEmpty28293031Table 14: Mailbox Status Register Bit DefinitionsCoreAccessResetValueBit(s)Name0 - 27ReservedReserved for future useRTA0Receive Threshold Active indicates the current FIFO status of thisinterface in the receive direction’0’ The receive FIFO level is less than or equal to the RIT threshold’1’ The receive FIFO level is greater than the RIT threshold0Send Threshold Active indicates the current FIFO status of thisinterface in the send direction’0’ The send FIFO level is greater than the SIT threshold’1’ The send FIFO level is less than or equal to the SIT threshold’0’Indicates the current status of this interface in the send direction’0’ There is room for more data’1’ The FIFO is full, any attempts to write data will be ignored andgenerate an error’1’Indicates the current status of this interface in the receive direction’0’ There is data available’1’ The FIFO is empty, any attempts to read data will be ignored andgenerate an onMailbox Error Register (ERROR)The Mailbox Error Register contains the error flags for PLB and AXI4-Lite accesses from this interface. The errorregister will be cleared at read, this means that all bits are sticky and that they indicate any errors that occurred sincelast time the error register was read. The register is read only and a write request issued to ERROR will be ignored.Bit assignment in the ERROR register is described in Table 16.Table 15: Error RegisterReserved0DS776 September 21, 2010Product Specification29www.xilinx.comFull ErrorEmpty Error303113

LogiCORE IP Mailbox (v1.00a)Table 16: Mailbox Error Register Bit DefinitionsCoreAccessResetValueBit(s)Name0 - 29ReservedReserved for future useFull Error’0’Indicates if there has been any attempts to write to the WRDATAregister while the Full flag was asserted since the error register waslast read’0’ No error has occurred’1’ One or more attempts to write while FSL link was full’0’Indicates if there has been any attempts to read from the RDDATAregister while the Empty flag was asserted since the error registerwas last read’0’ No error has occurred’1’ One or more attempts to read while FSL link was empty3031ReadEmpty ErrorReadDescriptionMailbox Send Interrupt Threshold Register (SIT)The Mailbox Send Interrupt Threshold Register contains the interrupt threshold for this interface in the senddirection. Depending on the send FIFO data level writing a new SIT can cause a rising edge on STA that cangenerate a STI interrupt if it is enabled in the IE register. Bit assignment in the SIT register is described in Table 18.Table 17: SIT RegisterSIT032-Log2(C MAILBOX DEPTH)31Table 18: Mailbox SIT Register Bit onLog2(C MAILBOX DEPTH)SITRead/Write0Lower Log2(C MAILBOX DEPTH) bits used, right justified to bit 31Mailbox Receive Interrupt Threshold Register (RIT)The Mailbox Receive Interrupt Threshold Register contains the interrupt threshold for this interface in the receivedirection. Depending on the receive FIFO data level writing a new RIT can cause a rising edge on RTA that cangenerate a RTI interrupt if it is enabled in the IE register. Bit assignment in the RIT register is described in Table 20.Table 19: RIT RegisterRIT032-Log2(C MAILBOX DEPTH)31Table 20: Mailbox RIT Register Bit DefinitionsBit(s)NameCoreAccessResetValueLog2(C MAILBOXDEPTH)RITRead/Write0DS776 September 21, 2010Product SpecificationDescriptionLower Log2(C MAILBOX DEPTH) bits used, rightjustified to bit 31www.xilinx.com14

LogiCORE IP Mailbox (v1.00a)Mailbox Interrupt Status Register (IS)The Mailbox Interrupt Status Register contains the current interrupt status for this interface. There are three typesof interrupts that can be generated. Mailbox Error interrupt are generated when any of the bits in the ERRORregister is set. The other two interrupts are FIFO related: RTI is generated for a rising edge on the RTA bit in theSTATUS register and STI that is generated for a rising edge on the STA STATUS register bit. RTI and STI are used toindicate that it is time to read from or write to the FIFOs to avoid any stalls in the data flow. Bit assignment in theIS register is described in Table 22.Table 21: IS RegisterReserved028ERRRTISTI293031Table 22: Mailbox IS Register Bit DefinitionsBit(s)Name0 - iptionReserved for future useRead/WriteRead/WriteRead/Write’0’Mailbox Error Interrupt Status for this interface.Values for read:’0’ No interrupt event has occurred.’1’ A Mailbox error has occurred.Values for write:’0’ No change’1’ Acknowledge and clear the interrupt if it is active’0’Mailbox Receive Threshold Interrupt pending status for this interface.Values for read:’0’ No interrupt event has occurred.’1’ Data level in the receive FIFO has caused a RTI.Values for write:’0’ No change’1’ Acknowledge and clear the interrupt if it is active’0’Mailbox Send Threshold Interrupt penging status for this interface.Values for read:’0’ No interrupt event has occurred.’1’ Data level in the send FIFO has caused a STI.Values for write:’0’ No change’1’ Acknowledge and clear the interrupt if it is activeMailbox Interrupt Enable Register (IE)The Mailbox Interrupt Enable Register contains the mask for the allowed interrupts on this interface. Bit assignmentin the IE register is described in Table 24.Table 23: IE RegisterReserved0DS776 September 21, 2010Product Specification28www.xilinx.comERRRTISTI29303115

LogiCORE IP Mailbox (v1.00a)Table 24: Mailbox IE Register Bit on0 - 28Reserved29ERRRead/Write’0’Mailbox Error Interrupt Enable for this interface’0’ ERR interrupt is disabled’1’ ERR interrupt is enabled30RTIRead/Write’0’Mailbox Receive Threshold Interrupt Enable for this interface’0’ RTI interrupt is disabled’1’ RTI interrupt is enabled31STIRead/Write’0’Mailbox Send Threshold Interrupt Enable for this interface’0’ STI interrupt is disabled’1’ STI interrupt is enabledReserved for future useMailbox Interrupt Pending Register (IP)The Mailbox Interrupt Pending Register contains the currently pending interrupts from this interface. It is a readonly register generated by performing bit-wise AND between the IS and IE registers. A write request issued to IPwill be ignored. Bit assignment in the IP register is described in Table 26. All the bits in this register are ORedtogether to generate the interrupt output signal for this interface. When an interrupt has been serviced it isacknowledge by writing the corresponding bit to the IS Register.Table 25: IP RegisterReserved028ERRRTISTI293031Table 26: Mailbox IP Register Bit me0 - 28Reserved29ERRRead’0’Mailbox Error Interrupt Pending status for this interface’0’ No pending interrupt’1’ Pending interrupt for Mailbox errors30RTIRead’0’Mailbox Receive Threshold Interrupt Pending status for this interface’0’ No pending interrupt’1’ Pending interrupt for data level in receive FIFO31STIRead’0’Mailbox Send Threshold Interrupt Pending status for this interface’0’ No pending interrupt’1’ Pending interrupt for data level in send FIFOReserved for future useDesign ImplementationTarget T

LogiCORE IP Mailbox (v1.00a) Functional Description The Mailbox is used for bi-directional inter-processor communication. A mailbox is a link between two otherwise separate processor systems. Other multi-port IP blocks, such as a memory controller, may also be shared by the two sub systems.

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LogiCORE IP Mailbox v2.1 5 PG114 April 4, 2018 www.xilinx.com Chapter 1 Overview The Mailbox core is used for bidirectional inter-processor communication. A mailbox is a link between two otherwise separate processor sy stems. Other multi-port IP blocks, such as a memory controller, can also be shared by the two sub systems.

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