A New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to .

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2020 IEEE 70th Electronic Components and Technology Conference (ECTC)A New RDL-First PoP Fan-Out Wafer-Level Package Process withChip-to-Wafer Bonding TechnologySeungNam Son1, DongHyun Khim1, SeokHun Yun1, JunHwan Park1, EunTaek Jeong1, JiHun Yi1,JinKun Yoo1, KiYeul Yang2, MinJae Yi2, SangHyoun Lee1, WonChul Do1, and JinYoung Khim1Amkor Technology Korea, Inc., 150, Songdomirae-ro, Yeonsu-gu, Incheon 21991, Koreae-mail: SeungNam.Son@amkor.co.krAbstract ü Fan-Out Wafer-Level Interposer Package-onPackage (PoP) design has many advantages for mobileapplications such as low power consumption, short signal path,small form factor and heterogeneous integration for multifunctions. In addition, it can be applied in various packageplatforms, including PoP, System-in-Package (SiP) and ChipScale Package (CSP). These advantages come from advancedinterconnection technology called a redistribution layer (RDL).However, a PoP-type RDL-base platform requires dual-sideRDLs on both top and bottom sides to stack another packageon top. In a monolithic process flow, that means the secondRDL only can be fabricated after finishing all the first RDLand the assembly processes such as flip-chip bonding, moldingand grinding. Therefore, this process flow is not quite asadvantageous as a non-PoP type platform because chips can belost during the second RDL process.For these reasons, Interposer PoP is mostly used for mobileapplication processors (APs)Although Interposer PoP based on laminate substratetechnology is a very powerful platform to satisfy the currentdemands in the industry, it still has limitations in reducingpackage thickness and body size due to a limited capabilityin current substrate manufacturing. In addition to thepackage size limitations, advanced packages for the 5G erarequire higher input/output (I/O) quantity which needs finerinterconnections, fine bump pitch and multiple chips.In this paper, to address this RDL-base Interposer PoPchallenge, a real chip-last process flow with a chip-to-wafer(C2W) bonding technology is introduced. And the results arepresented of building and testing an RDL-base wafer-levelInterposer PoP with a size of 12.5 x 12.5 mm2 and thickness of0.357 mm including solder ball. The bottom side has a 3-layerRDL structure and the top RDL for the package stacking has a1-layer structure. These RDLs are implemented with copper(Cu) lines with 5 μm/10 μm of line & space (L/S) and copper(Cu) cored solder balls (CCSBs) are used as the verticalinterconnect components. The silicon die and CCSBs’ jointquality is confirmed by reliability testing. The test vehiclepackage passed all the reliability tests of moisture resistancetest (MRT) L3, Temperature Cycle, Condition B (TCB) 1,000cycles and high temperature storage (HTS) 1,000 hrs.Keywords—Fan-Out package, FOWLP, Chip-to-wafer, C2W,Interposer PoP, Chip-last, RDL-first, PoPI.INTRODUCTIONInterposer Package-on-Package (PoP) is an enablingpackaging technology to satisfy the requirements of a threedimension (3D) structure by stacking two different laminatesubstrates (top interposer and bottom substrate) with copper(Cu) cored solder balls (CCSBs) or through mold vias(TMVs) for vertical interconnections. Using two substratesprovides the benefits of easier warpage management andflexible construction with lower cost. The package warpagecan be controlled by optimizing the substrate materials anddesign. The top interposer contributes design flexibility foreither commercially available or customized memory use.2377-5726/20/ 31.00 2020 IEEEDOI 10.1109/ECTC32862.2020.00298Figure 1. Illustration of Interposer PoP: a) Laminate-based; b) RDL-based.Many companies are focusing on new material andassembly technology to satisfy the new requirementsmentioned above. One of the promising technologies in themarket is a Interposer PoP platform utilizing Curedistribution layer (RDL) technology which is alreadyapplied in flagship mobile processors. This RDL-based 3Dpackage has many advantages such as form factor, featuresize, electrical and thermal benefits [1, 2]. Figure 1 showstwo different Interposer PoPs: (a) laminated-based, and (b)RDL-based.RDL manufacturing technology is based on waferprocessing which enables thinner and finer electrical traces.RDL is conventionally fabricated by an additive layermethod on a silicon (Si) or glass wafer. By repeated build-1910

up of a passivation layer and a metal interconnection layer,multiple RDLs are possible. Each metal line is mechanicallyand electrically connected through vias patterned in thepassivation layers.to assess package characteristics regarding structure andreliability. A key difference of the new process is that eachRDL is prepared separately and assembled after the chipattachment. One of the benefits of this process is that interimtests prior to the actual chip assembly step can identifyknown-good sites. The actual chips can then be allocatedonly on the known-good RDL sites. In other words, theactual chip loss during the RDL process can be prevented byseparating the RDL preparation. Another benefit is a samplehandling efficiency because both top and bottom RDL layersare formed directly on carrier wafers without anyintermediate materials such as EMC underfill. Therefore, thewafers provide a flat surface during the RDL process and,eventually, those process features contribute overall yieldimprovement of the RDL and assembly process.Figure 3. Illustration of RDL-based Interposer PoP with CCSBsFigure 2. Illustration of Process Flow: a) Chip First; b) Chip Last.There are two major process concepts for the RDL-baseInterposer PoP as shown in Figure 2: (a) chip first, and (b)chip last. In the chip-first process, chips are bonded face-upon a with or without interposer RDL layer and thenencapsulated with an epoxy molding compound (EMC)material. For electrical connections, metal pads on the chipare exposed by wafer grinding. Finally, multiple RDLs arefabricated on the mold exposed side. This multiple RDLsacts as the bottom RDL substrate. The chips are attached onthe wafer before the fabrication of the complex multiplebottom RDL layers. The chip-last process has an oppositeprocess flow to the chip first. The bottom RDL substratelayer is first prepared on a wafer and then the chips are flipchip bonded as shown in Figure 2 (b). The top RDLinterposer can be fabricated in demand.The two options have their own merits and demeritsregarding yield management and build cycle-time control.However, if both top and bottom RDL layers are required,both options cannot avoid a risk of chip loss, because at leastone (top or bottom) RDL layer should be fabricated after thechip bonding. This process flow also impacts the processcycle-time increment, because of the sequential process flow.A new hybrid assembly process has been introduced thatcan overcome the technical barriers mentioned above. Asample build was conducted with a fan-out type test vehicleInstead of tall copper pillars for the verticalinterconnection, CCSBs are applied in the hybrid processlike the laminate-base Interposer PoPs shown in Figure 3.The latest RDL-based 3D packaging platform adopts tallcopper pillar. However, in this new process, the electroplatedcopper pillars may not provide robustness during theassembly process. CCSB technology is a well-known andmature approach for the vertical interconnections inlaminate-based mobile packages because it can control thegap height between the top interposer and bottom substratedue to un-melting the Cu core balls during the mass reflowprocess [3-6].This work provides the results of a test vehicle buildusing the new process flow and its reliability performance.The advantages will also be discussed in following sections.II.TEST VEHICLE INFORMATIONA. Package StructureFigure 4 shows a 3D illustration of the Interposer PoPtest vehicle. It is composed of a silicon die, CCSBs, top RDLInterposer RDL layer and bottom RDL layer. The silicon dieis flip bonded on the bottom RDL substrate with 45 μmbumps for the peripheral array and 65 μm bumps for the corearray pitched micro-bumps. An EMC material is filledbetween these two RDL layers and encapsulates the die andthe CCSBs.The top RDL interposer layer has array of under-bumpmetal (UBM) pads for electrical connections with mobile1911

memory packages or passive components such as capacitorsand inductors. The signal path of the top RDL interposer isexpanded to the bottom RDL layer through the CCSBsconnecting vertically between the two layers. The pitch ofthe 360 CCSBs is 250 μm.Figure 4.3D illustration of the RDL-based Interposer PoP.The bottom RDL substrate consists of three metal layersand four dielectric organic passivation layers. The minimumline and space (L/S) width of the bottom RDLs is 5 μm and10 μm, respectively. This fine width of the metalinterconnection lines improves the signal integration whilemaintaining a limited package size. The encapsulating EMCprovides structural robustness, electrical insulation andenvironmental protection for the silicon die and CCSBs. Aball grid array (BGA) is formed under package bottom side.The solder ball height after soldering by mass reflow and thepitch are 135 μm and 350 μm, respectively. The top RDLinterposer and bottom RDL substrate are the same size of12.5 x 12.5 mm2. Total package thickness including thesolder ball is 357 μm. Table 1 summarizes the informationof the test vehicle package.TABLE I. Size[mm2]Thickness[μm]I/O diameter[μm]I/O pitch[μm]I/O count[ea]most susceptible areas to the thermal cycling test. The othertwo chains are for the package core area and the top RDLinterposer area. The bottom RDL to silicon die path isdesigned to test the micro-bump joints between the bottomRDL substrate and the silicon die. The last path checks themetal interconnection lines inside the bottom RDL substrate.These daisy chains help identify failed locations before andafter the reliability tests.THE INFORMATION OF THE TEST VEHICLESilicon DieTop RDLInterposerBottom RDLSubstrate8.7 x 9.112.5 x 12.512.5 x 12.51002245Peripheral: 45Core: 65240215903503502800560880B. Daisy Chain DesignThe test vehicle has daisy chains for electrical open/short(O/S) testing before and after the reliability tests. A total ofseven daisy chains are embedded that can be divided intothree major interconnection paths as shown in Figure 5: (a)bottom RDL to top RDL, (b) bottom RDL to silicon die and(c) bottom inter-RDL path.The bottom RDL to top RDL path checks the verticalconnectivity with three daisy chains. One of these threechains loops around the four package corners which are theFigure 5. Schematic figure of the three daisy chains’ paths.III.PROCESS FLOWA. Preparation of Top and Bottom RDLAs mentioned, the separate build-up of the top andbottom RDL layers before die attachment is the keyadvantage of this new process. Each RDL is prepared at thewafer level. Figure 6 illustrates preparation sequences. Thewafer act as a temporary carrier which will be removed inthe final fabrication stage.Figure 6. Preparation of (a) top RDL interposer and (b) bottom RDLsubstrate.The top RDL interposer consists of single layer of Cumetal lines and UBM pads for the CCSBs. An organicpassivation material encapsulates the metal interconnections.The CCSB is dropped on each UBM Pad and reflowed in thewafer level as shown in Figure 6-a. Each top RDLinterposer is singulated for flip chip attachment on thebottom RDL substrate wafer.1912

The bottom RDL substrate has multiple layers of metallines. The same organic material is applied between the lines.The silicon chips are flip chip bonded on the bottom RDLwafer. By inspecting the bottom RDL before the die attach,the silicon chips can be attached only on known-good sites.That avoids losing expensive application-specific integratedcircuit (ASIC) chips in actual production. A conventionalmass reflow process can be applied for the flip chip bondingbecause the bottom RDL wafer has little warpage unlike thinorganic substrates. The gap between the die and bottomsubstrate is filled with an underfill material as shown inFigure 6-b.B. Assembly of Top Interposer and Bottom RDLSubstrateAfter separate preparation, the singulated top RDLinterposers are flip bonded onto the bottom RDL substratewafer as shown in Figure 7. All the samples can be inspectedto eliminate any flaws before bonding, so known-good topinterposers are attached only on known-good bottomsubstrate sites. This is one of the key advantages ofseparating the two RDLs.In the next step, gap filling between the top and bottomlayer is accomplished using a molding process at the waferlevel. The molding compound completely fills the gapwithout any voids. Then, the wafer piece on each single topRDL layer is removed by laser irradiation process. Atemporary carrier is bonded to the top RDL layer forsubstrate carrier debonding and BGA attachment processes.After mounting the BGA on the bottom RDL substrate by amass reflow process, singulation was performed to the finalsingle packages.IV.KEY TECHNOLOGIES AND FABRICATIONRESULTThe RDL-base Integrated PoP is manufactured with threekey technologies: (a) wafer support system (WSS), (b) RDLfabrication and (c) CCSBs for the vertical interconnections.A. Wafer Support System (WSS)Thin top and bottom RDLs are prepared simultaneouslyutilizing WSS technology. The temporary carrier wafer actsas a support structure during the RDL fabrication because thethickness of the RDL layers is less than 50 μm. Mostavailable WSS processes utilize a sacrificial layer appliedbetween the carrier wafer and the RLD for easy separation.The sacrificial layer material can be a liquid or a film type. Itshould stand high temperature processes without anydegradation or delamination. There are several separationmethods such as thermal sliding, chemical etching,mechanical detachment and laser irradiation. The carrierwafer also needs to maintain its flatness through all the RDLprocessing. Therefore. all the material properties andcharacteristic should be carefully reviewed and tested forstable fabrication.B. RDL TechnologyThe introduction of RDL technology has led to visiblechanges in Interposer PoP that impact form factor and L/Sfor the electric signal path. To fabricate the bottom RDLsubstrate, four layers of dielectric organic passivation andthree layers of copper metal lines are sequentially built-up.Finally, landing UBM pads are plated for the silicon die andCCSB attachment. The minimum L/S is 5 μm/10 μm andtotal thickness is 45 μm with UBM. Figure 8 showsrepresentative cross-sectional images of the bottom RDLsubstrate.Figure 8. Cross-sectional images of the bottom RDL substrate.Figure 7. Process flow for RDL-based Interposer PoP with CCSBs.One of the major benefits of using RDLs for theIntegrated PoP is the thickness reduction. The packagethickness of the RDL-based Integrated PoP is about 30%thinner than a conventional laminate-based package. Figure9 illustrate the thickness comparison between a laminate andan RDL Integrated PoP.1913

Figure 11. SAT images.Figure 9. Comparison between a laminated and an RDL-based InterposerPoPC. CCSB as a Vertical InterconnectionCCSB is one of the representative components forvertical interconnection between the top and bottom RDLsubstrates. The CCSB is composed of three materials: the Cucore ball, a nickel (Ni) layer and solder cladding. The size ofCCSB should be chosen by both package height and CCSBlanding pad pitch/diameter to avoid any solder bridge or nonwet problem during the CCSB drop process or the topinterposer bonding process. Figure 10 shows cross-sectionalimages of the RDL-based Integrated PoP test vehicle.Figure 12. Cross-sectional images of Silicon die mirco-bump joint: a) TC‘B’ 1000 cycles with Precon L3 and b) after HTS 1000 hrs.Figure 10. Cross-sectional image: a) CCSB b) Top RDL Interposer c)Bottom RDL Interposer d) Silicon Die and e) Pkg. thickness except BGAV.RELIABILITY PERFORMANCEComponent level reliability (CLR) testing was performedon the RDL-based Integrated PoP test vehicles. Testing wasperformed in accordance with the JEDEC standard as shownin Table I. The test d samples passed all the requirements:(a) Thermal cycle (TC) condition B of 1,000 cycles afterMoisture Sensitivity Test (Precon) L3/260 C condition, (b)High temperature storage (HTS) of 1,000 hrs without Precon.Table I shows reliability test items, conditions, samplequantities and results.All samples were checked by electrical O/S testing andscanning acoustic tomography (SAT) testing (see Figure 11).Figure 12 and 13 show the cross-sectional images of microbump joints and CCSBs after TC ‘B’ and HTS test. Thejoints showed no abnormality after all the reliability tests.TABLE II.RELIABILITY TEST CONDITIONS AND RESULTSReliability test itemsConditionRead points Sample # ResultsPrecon (L3)L3 / 260 C-76PassTC 'B'-55 C / 125'C1000x76PassHTS150'C1000hrs73PassFigure 13. Cross-sectional images of CCSB joint: a) TC ‘B’ 1000 cycleswith Precon L3 and b) after HTS 1000 hrs.VI.CONCLUSIONSA new RDL-based Integrated PoP process has beendeveloped and evaluated by reliability testing. The separatebuild-up of the top and bottom RDL leads to cost reductionbecause the silicon chip loss can be minimized by attachingto only known-good sites. It also shortens the assemblycycle-time because the two the RDLs are fabricated inparallel. In comparison to a build-up process from one sideRDL to the other side RDL sequentially the benefits are asfollows:x Increasing capability for yield management:mapping known-good sites by an interim test enablesa selective assembly minimizing any loss of goodchips.x Shortening cycle-time: separate fabrication of bothtop and bottom RDLs in parallel.x Decreasing form factor: the RDL-based IntegratedPoP is 30% thinner than current mass-producedlaminate-based Integrated PoP.1914

ACKNOWLEDGMENTThe authors have special thanks for collaboration withJiYeon Ryu and TaeKi Kim from Design Team and YongSong from Mechanical Simulation Team. The authors wouldalso like to thank the Fabrication Technology DevelopmentTeam and the Advanced Assembly TechnologyDevelopment Team. Finally, the authors would like to thankGyuWan Han, GiTae Lim from the Product DevelopmentTeam for being technical advisers.REFERENCES[1]SeungNam Son, HoDol Yoo, JiHyun Kim, JooHyun Kim, DooWonLee, WonChul Do, Yun Ra, KwangSup So, WooHyun Paik, andKangWook Lee, “A Novel System in Package using High DensityFan-out Technology for Heterogeneous Integration,” 2018 IEEE 2ndElectron Devices Technology and Manufacturing Conference(EDTM), pp. 230-232, March 2018.[2][3][4][5][6]1915Curtis Zwenger, George Scott, Bora Baloglu, Mike Kelly, WonChulDo, WonGeol Lee, JiHun Yi, “Electrical and Thermal Simulation ofSWIFT High-density Fan-out PoP Technology,” 2017 IEEE 67thElectronic Components and Technology Conference, pp. 1962-1967,June 2017.Y. Machida, “Development of Molded Core embeddedPackage(MCeP),” JIEP EPADs workshop, 2008, pp. 62-73.Yunsung Kim, Hyelim Choi, Hyoungjoo Lee, Dongjun Shin, JinhanCho, Heeman Choe, “Improved reliability of copper-cored solderjoints under a harsh thermal cycling condition,” MicroelectronicsReliability 52(2012), pp. 1441-1444.Yunsung Kim, Hyelim Choi, Hyoungjoo Lee, Dongjun Shin JengtakMoon, Heeman Choe.”Fracture behavior of Cu-cored solder joint,”J.Materal Science (2011), pp. 6897-6903.Xiaoqiang Xie, Lei Wang, Taekoo Lee, “Drop test failure analysis ofSAC BGA solder joints using Ni/Au and Cu-OSP pad finish,” IEEE7th International Conference on Electronic Packaging Technology &High Density Packaging · ICEPT 2006.

A New RDL-First PoP Fan-Out Wafer-Level Package Process with Chip-to-Wafer Bonding Technology SeungNam Son1, DongHyun Khim1, SeokHun Yun1, JunHwan Park 1, EunTaek Jeong1, JiHun Yi1, JinKun Yoo1, KiYeul Yang2, MinJae Yi2, SangHyoun Lee1, WonChul Do1, and JinYoung Khim1 Amkor Technology Korea, Inc., 150, Songdomirae-ro, Yeonsu-gu, Incheon 21991, Korea

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