Zynq UltraScale RFSoC RF Data Converter LogiCORE IP Product Guide
Zynq UltraScale RFSoC RFData Converter v2.2LogiCORE IP Product GuideVivado Design SuitePG269 (v2.2) October 30, 2019
Table of ContentsChapter 1: IP Facts. 5Features. 5IP Facts.6Chapter 2: Overview.7RF-ADC. 9RF-DAC. 13Applications.15Licensing and Ordering. 15Chapter 3: Product Specification. 16Performance. 18Resource Use. 18Port Descriptions.18Register Space. 25Chapter 4: Designing with the Core. 36IP Core Configuration in the Vivado Design Suite.36Software Driver.36RF-ADC. 37RF-DAC. 75Quadrature Modulator Correction .98Coarse Delay. 101Dynamic Update Events. 102PLL.104Interrupt Handling. 105Clocking. 110Resets.115Power-up Sequence. 116Bitstream Reconfiguration.118Interfacing to the AXI4-Stream Interface. 118Applications Overview. 119PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com2
Chapter 5: Design Flow Steps.138Customizing and Generating the Core. 138Simulation. 152Synthesis and Implementation. 152Chapter 6: Example Design. 153RF-ADC Data Capture Block. 154RF-DAC Data Stimulus Block. 156Digital Data Format.158Chapter 7: Test Bench.159Analog Signaling. 161Appendix A: Upgrading. 164Changes from V2.1 to V2.2 . 164Changes from V2.0 to V2.1. 164Changes from V1.2 to V2.0. 166Changes from V1.1 to V1.2. 166Appendix B: Debugging.168Finding Help on Xilinx.com. 168Debug Tools. 169Hardware Debug. 170Interface Debug. 170Appendix C: Zynq UltraScale RFSoC RF Data Converter Baremetal/Linux Driver. 172Overview.172Data Structures.173User API Functions. 190Interrupt Handling. 228In-line Functions.234Appendix D: RF Analyzer.250Clocking. 252Address Space.254User Interface. 254Hardware Trigger. 255PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com3
Appendix E: Additional Resources and Legal Notices.257Xilinx Resources.257Documentation Navigator and Design Hubs. 257References.257Revision History. 258Please Read: Important Legal Notices. 260PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com4
Chapter 1IP FactsThe Xilinx LogiCORE IP Zynq UltraScale RFSoC RF Data Converter IP core provides aconfigurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integratordesigns.IMPORTANT! In this guide reference is made to the Dual and Quad tiles; for the actual sampling ratespecifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). Notethat Dual and Quad refers to the tile configuration and not the number of converters.Features Up to 16 14-bit RF-DACs Eight 12-bit Dual RF-ADCs, or 16 12-bit Quad RF-ADCs, depending on device Supports alignment between multiple converters Pre-programs RF-DAC and RF-ADC with key user-defined parameters Multiple AXI4-Stream data interfaces for RF-ADCs and RF-DACs Single AXI4-Lite configuration interface 1x (bypass), 2x, 4x, 8x interpolation 1x (bypass), 2x, 4x, 8x decimation Digital complex mixers Numerical Controlled Oscillator (NCO) Quadrature Modulation Correction (QMC) On-chip PLL and VCO per tilePG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com5
Chapter 1: IP FactsIP FactsLogiCORE IP Facts TableCore SpecificsSupported DeviceFamily1Zynq UltraScale RFSoCSupported User InterfacesAXI4-Stream, AXI4-Lite Control/StatusResourcesPerformance and Resource Use web pageProvided with CoreDesign FilesRTLExample DesignVerilogTest BenchVerilogConstraints FileXilinx Design Constraints (XDC)Simulation ModelSupported S/WDriver2VerilogStandalone and LinuxTested Design Flows3Design EntryVivado IP IntegratorSimulationFor supported simulators, see the Xilinx Design Tools:Release Notes Guide.SynthesisVivado SynthesisSupportRelease Notes and Known IssuesMaster Answer Record: 69907All Vivado IP Change LogsMaster Vivado IP Change Logs: 72775Xilinx Support web pageNotes:1.For a complete list of supported devices, see the Vivado IP catalog.2.Stand-alone driver details can be found in the software development kit Install Directory /Vitis/ Release /data/embeddedsw/doc/Xilinx drivers.htm.Bare Meta/Linux documentation is available in Appendix C: Zynq UltraScale RFSoC RF Data Converter Bare-metal/Linux Driver.3.For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com6
Chapter 2OverviewThe Xilinx Zynq UltraScale RFSoC family integrates the key subsystems required toimplement a complete software-defined radio including direct RF sampling data converters,enabling eCPRI and Gigabit Ethernet-to-RF on a single, highly programmable SoC.Each RFSoC offers multiple RF-sampling analog-to-digital (RF-ADC) and RF-sampling digital-toanalog (RF-DAC) data converters. The data converters are high-precision, high-speed and powerefficient. Both are highly configurable and tightly integrated with the programmable logic (PL)resources of the Zynq UltraScale RFSoC.The RF-ADC supports device-dependent sample rates and input signal frequencies listed in theZynq UltraScale RFSoC Data Sheet: Overview (DS889), with excellent dynamic range performance.The RF-DAC generates output carrier frequencies at rates defined in the Zynq UltraScale RFSoCData Sheet: DC and AC Switching Characteristics (DS926), depending on the device (see the ZynqUltraScale RFSoC Data Sheet: Overview (DS889) for device information.The RF data converters also include power efficient digital down converters (DDCs) and digital upconverters (DUCs) that include programmable interpolation and decimation rates, a numericallycontrolled oscillator (NCO), and a complex mixer. The DDCs and DUCs can also support multiband operation. The following figure shows the block diagram of the Zynq UltraScale RFSoCRF Data Converter.The RF-ADCs and RF-DACs are organized into tiles, each containing two or four RF-ADCs orfour RF-DACs. Multiple tiles are available in each Zynq UltraScale RFSoC (see the specificdevice data sheet for the number of tiles and converters per device). Each tile also includes ablock with a PLL and all the necessary clock handling logic and distribution routing for the analogand digital logic.This guide describes the Zynq UltraScale RFSoC RF Data Converter IP core and softwaredrivers that are used to configure the data converters and instantiate them for use in a design.For device specifications and additional information, see: Zynq UltraScale RFSoC Data Sheet: Overview (DS889) Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) Zynq UltraScale Device Technical Reference Manual (UG1085).PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com7
Chapter 2: OverviewFigure 1: Zynq UltraScale RFSoC RF Data Converter IP Core in Zynq UltraScale RFSoCZynq UltraScale RFSoCData Converter IP CoreDUCAXI4-StreamProcessing SystemQuad ARM Cortex-A53Dual ARM Cortex-R5DAC4 to 16 TX cControl andConfigurationDDCAXI4-StreamADCGTY SerialTransceivers4 to 16 RX ChannelsDDCAXI4-StreamADCX19532-062819Figure 2: RF-ADC Tile StructuremX3 axisData PathADCVinX3mX3 axisData PathADCmX2 axisData PathADCVinX2mX2 axisData PathADCmX1 axisData PathADCVinX1mX1 axisData PathADCVinX 23VinX 01mX0 axisData PathADCQuad RF-ADC TileVinX0mX0 axisData PathADCDual RF-ADC TileX23275-100919PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com8
Chapter 2: OverviewFigure 3: RF-DAC Tile StructuresX3 axisData PathDACVoutX3sX2 axisData PathDACVoutX2sX1 axisData PathDACVoutX1sX0 axisData PathDACVoutX0Quad RF-DAC TileX23274-092319RF-ADCThere are two types of RF-ADC tile, the Dual RF-ADC and the Quad RF-ADC tile. The type oftile available is device dependent (see the Zynq UltraScale RFSoC Data Sheet: Overview (DS889)).Each tile includes a PLL and clocking instance. All RF-ADCs within a tile share this commonclocking infrastructure.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com9
Chapter 2: OverviewThe Quad RF-ADC tile consists of four RF-ADCs, arranged in two pairs. Each of these converterscan be configured individually for real input signals or, as a pair, for I/Q input signals. Thefollowing figure shows an overview of the Quad RF-ADC tile.Figure 4: Quad RF-ADC Tile OverviewVCMVIN PVIN NIADCBUFQuad Tile0 90 Q0 90 VIN PVIN NADCBUFQuad TileQNCONCOSampling Clock/PLL Reference ClockSampling ClockADC CLK PADC CLK NDDCPLLVIN PVIN NBUFIADCQuad Tile0 90 0 90 VIN PBUFVIN NADCQuad TileQQNCONCOVCMX18282-090419PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com10
Chapter 2: OverviewThe Dual RF-ADC tile consists of two RF-ADCs. These converters can be configured individuallyfor real input signals or, as a pair, for I/Q input signals. The following figure shows an overview ofthe Dual RF-ADC tile.Figure 5: Dual RF-ADC Tile OverviewVCMIVIN P100 ΩVIN NRFADCADCBUFDualTile12-bits12-bits4GS/s0 90 QNCOSampling Clock/PLL Reference ClockSampling ClockADC CLK PDDC100 ΩADC CLK NPLLIVIN P100 ΩBUFVIN NRFADCADCDualTile12-bits12-bits4GS/s0 90 QVCMNCOX18283-070219RF-ADC Features Tile configuration Four or two RF-ADCs and one PLL per tile12-bit RF-ADC resolution, with 16-bit digital signal processing datapath; each 12-bit datastream is MSB-aligned to 16 bit samples at the output of the RF-ADC core before passingto the DDC blockPG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com11
Chapter 2: Overview Implemented as either four channels (Quad) or two channels (Dual) (the sampling rate isdevice dependent; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)) Decimation filters 1x (bypass filter), 2x, 4x, 8x 80% of Nyquist bandwidth, 89 dB stop-band attenuation Digital Complex Mixers Full complex mixers support real or I/Q inputs from the RF-ADC 48-bit Numeric Controlled Oscillator (NCO) per RF-ADC Fixed Fs/4, Fs/2 low power frequency mixing mode, where Fs is the sample frequencyI/Q and real input signals supported Single/multi-band flexibility 2x bands per RF-ADC pair 4x bands per Quad RF-ADC tile Can be configured for real or I/Q inputs Full bandwidth of the RF-ADC can be accessed in bypass mode Input signal amplitude threshold: Two programmable threshold flags per RF-ADC Built-in digital correction for external analog quadrature modulators: Supports gain, phase, and offset correction for an I/Q input pair (two RF-ADCs) SYSREF input signal for multi-channel synchronization Flexible AXI4-Stream interface supports a wide range of programmable logic clock rates andconverter sample rates Per tile current-mode logic (CML) clock input buffer with on-chip calibrated 100Ωtermination; supplies the RF-ADC sampling clocks or provides a reference clock for the onchip PLL Dedicated high-speed, high-performance, differential input buffer per RF-ADC with on-chipcalibrated 100Ω termination (on-die termination) Output common mode reference voltage for DC-coupling RF-ADC inputsPG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com12
Chapter 2: OverviewRF-DACEach RF-DAC tile consists of four RF-DACs that can be configured individually for real outputsignals or, as a pair, for I/Q output signal generation. Each RF-DAC runs at a data rate specified inthe Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). The RF-DACtile has one PLL and a clocking instance. The following figure shows an overview of the RF-DAC.Figure 6: RF-DAC Overview50 ΩDAC AVTT50 ΩI0 Σ90 Q0 VOUT PDACVOUT NΣ90 NCOVOUT PDACVOUT NQNCOSampling Clock/PLL Reference ClockDAC CLK PDUC100 ΩDAC CLK NPLLI0 Σ90 VOUT PDACNCOQ0 90 VOUT NΣVOUT PDACQNCOVOUT N50 Ω50 ΩDAC AVTTX18281-082019PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com13
Chapter 2: OverviewRF-DAC Features Tile configuration Four RF-DACs and one PLL per tile14-bit RF-DAC resolution with 16-bit digital signal processing path; the data is MSBaligned to 16 bitsDevice-dependent sampling speed; see the Zynq UltraScale RFSoC Data Sheet: Overview(DS889)Device-dependent full power output bandwidth; see the Zynq UltraScale RFSoC DataSheet: Overview (DS889) Interpolation 1x (bypass filter), 2x, 4x, 8x 80% pass band, 89 dB stop band attenuation Digital Complex Mixers Full complex mixers support real or I/Q output signals to the RF-DACs 48-bit NCO per RF-DAC Fixed Fs/4, Fs/2 low-power frequency mixing modeSupports mixed mode RF-DAC functionality which maximizes RF-DAC power in the secondNyquist zone Single/multi-band flexibility 2x bands per RF-DAC pair 4x bands per RF-DAC tile Can be configured for real or I/Q outputs Full Nyquist bandwidth in bypass mode Digital Correction for external analog quadrature modulators: Supports gain, phase, and offset correction for an I/Q output pair (two RF-DACs) Sinc correction for first Nyquist zone External input signal (SYSREF) for multi-channel synchronization of data converter channels Per tile current mode logic (CML) clock input buffer with on-chip calibrated 100Ω termination;supplies the RF-DAC sampling clocks or provides a reference clock for the on-chip PLL Supports 20 mA or 32 mA output power modeFor the RF-ADC and RF-DAC operating and absolute maximum/minimum parameters see:PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com14
Chapter 2: Overview Zynq UltraScale RFSoC Data Sheet: Overview (DS889) Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)Applications Multi-band, multi-mode 3G, 4G, and 5G cellular radios Multiple antenna systems (Massive MIMO, AAS, AAA) Cable infrastructure (DOCSIS 3.x) Software defined radios Microwave and millimeter wave radios Test and measurement applicationsRelated InformationApplications OverviewLicensing and OrderingThis Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License.Note: To verify that you need a license, check the License column of the IP Catalog. Included means that alicense is included with the Vivado Design Suite; Purchase means that you have to purchase a license touse the core.Information about other Xilinx LogiCORE IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IPmodules and tools, contact your local Xilinx sales representative.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com15
Chapter 3: Product SpecificationChapter 3Product SpecificationThe Zynq UltraScale RFSoC RF Data Converter IP core provides a way of instantiating all theRF-DAC and RF-ADC blocks in Zynq UltraScale RFSoCs in IP integrator. A single IP coreinstance allows access to all converters in the device. The IP ensures that all enabled blocks arepowered up and that unused converters are disabled.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com16
Chapter 3: Product SpecificationFigure 7: IP Core OverviewZynq UltraScale RFSoC RF Data Converter IP CoreAXI4-Stream x4 or x2Power-OnSequencerAXI4-Stream x4 or x2Power-OnSequencerPower-OnSequencerAXI4-Stream x4 or x2Power-OnSequencerReal-TimeInputsRF-ADC Tile 225AXIS OutAnalogInputsRF-ADC Tile 226AXIS OutAnalogAXI4-Stream x4 or x2AXI4-LiteRF-ADC Tile 224AXIS OutAnalogControl &Status IFAXI4-Stream x4 or x2Power-OnSequencerAXI4-Stream x4 or x2Power-OnSequencerAXI4-Stream x4 or x2Power-OnSequencerAXI4-Stream x4 or x2Power-OnSequencerInputsRF-ADC Tile 227AXIS OutAnalogInputsVIN x4 or x2VIN x4 or x2VIN x4 or x2VIN x4 or x2Control &StatusSignalsRF-DAC Tile 228AXIS DataAnalogInputsOutputsVOUT x4RF-DAC Tile 229AXIS DataAnalogInputsOutputsVOUT x4RF-DAC Tile 230AXIS DataAnalogInputsOutputsRF-DAC Tile 231AXIS DataAnalogInputsOutputsVOUT x4VOUT x4X18850-082019An RF-ADC tile has two or four RF-ADCs; an RF-DAC tile has four RF-DACs. The number ofconverters and the maximum sample rate depend on the device and package. The converters ineach tile are the same type.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com17
Chapter 3: Product SpecificationRelated InformationPower-up SequencePerformanceTo see the performance of the RF-ADC and RF-DAC blocks, see the Zynq UltraScale RFSoC DataSheet: DC and AC Switching Characteristics (DS926).Related InformationClockingResource UseFor full details about performance and resource utilization, visit the Performance and ResourceUtilization web page (registration required).Port DescriptionsConfiguration Interface PortsTable 1: Configuration Interface PortsPort NameI/OClocks axi aclkInN/AAXI clock input (continuous clock)s axi aresetnInN/AReset for the aclk domain. The deassertion of thereset should be synchronous to s axi aclk.s axi awaddr[17:0]Ins axi aclkWrite Addresss axi awvalidIns axi aclkWrite Address Valids axi awreadyOuts axi aclkWrite Address Readys axi wdata[31:0]Ins axi aclkWrite Datas axi wstrb[3:0]Ins axi aclkWrite Data Byte Strobes axi wvalidIns axi aclkWrite Data Valids axi wreadyOuts axi aclkWrite Data Readys axi bresp[1:0]Outs axi aclkWrite Responses axi bvalidOuts axi aclkWrite Response Valids axi breadyIns axi aclkWrite Response ReadyPG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterDescriptionSend Feedbackwww.xilinx.com18
Chapter 3: Product SpecificationTable 1: Configuration Interface Ports (cont'd)Port NameI/OClocks axi araddr[17:0]Ins axi aclkRead Addresss axi arvalidIns axi aclkRead Address Valids axi arreadyOuts axi aclkRead Address Readys axi rdata[31:0]Outs axi aclkRead Datas axi rresp[1:0]Outs axi aclkRead Responses axi rvalidOuts axi aclkRead Data Valids axi rreadyIns axi aclkRead Data ReadyOuts axi aclkInterrupt outputirqDescriptionMulti-Tile Synchronization PortsTable 2: Multi-Tile Synchronization PortsPort NameDescription1I/OClocksysref in pInN/AExternal analog SYSREF inputsysref in nInN/AExternal analog SYSREF inputuser sysref adcInm0 axis aclkRF-ADC SYSREF input from programmable logic(PL)/ user design; synchronous to RF-ADC tile 0 PLclockuser sysref dacIns0 axis aclkRF-DAC SYSREF input from programmable logic(PL)/user design; synchronous to RF-DAC tile 0 PLclockNotes:1.See the Multi-Tile Synchronization section in the Applications sub-section for more information.Related InformationMulti-Tile SynchronizationClock Ports Common to RF-DAC TileTable 3: Clock Ports Common to RF-DAC TilePort Name1I/OClockdacX clk pInN/ARF-DAC on-chip PLL reference clock or samplingclock inputdacX clk nInN/ARF-DAC on-chip PLL reference clock or samplingclock inputOutN/AOutput clock to user logicclk dacXDescriptionNotes:1.X refers to the location of the tile in the converter column.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com19
Chapter 3: Product SpecificationAXI4-Stream Related Ports for RF-DACsTable 4: AXI4-Stream Related Ports for RF-DACsPort Name1I/OClockDescriptionsX axis aclkInN/AClock input for RF-DAC data inputsX axis aresetnInN/ASynchronous reset for the sX axis aclk domain.This should be held low until sX axis aclk is stable.sXY axis tdata[M:0]InsX axis aclkAXI4-Stream data inputsXY axis tvalidInsX axis aclkAXI4-Stream validsXY axis treadyOutsX axis aclkAXI4-Stream readyvoutXZ pOutN/AAnalog outputvoutXZ nOutN/AAnalog outputNotes:1.X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).Z refers to the location of the RF-DAC in the tile (0 to 3). M is the number of samples per AXI4-Stream word * 16 forconverter XY.Real-Time Signal Interface Ports for RF-DACsTable 5: Real-Time Signal Interface Ports for RF-DACsPort Name1I/OClockDescriptionRF-DAC fast shutdown001 - Scale output data by 0.5dacXZ fast shutdown[2:0]InN/A011 - Scale output data by 0.25111 - Scale output data by 0Others - Normal operationdacXY pl eventInclk dacXRF-DAC PL eventAssert to update RF-DAC settings from the PLNotes:1.X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).Z refers to the location of the RF-DAC in the tile (0 to 3).Real-Time NCO Signal Interface Ports for RF-DACsTable 6: Real Time NCO Signal Interface Ports for RF-DACsPort Name1I/OClockDescriptiondacXY nco freq[47:0]Ins axi aclkRequested NCO frequency setting. This is a 48 bitsigned input representing the NCO frequency. Thevalue ranges from -Fs/2 to Fs/2, where Fs is thesampling rate.dacXY nco phase[17:0]Ins axi aclkRequested NCO Phase setting. This is a 18 bitsigned number representing the NCO phase. Thevalue ranges from -180 to 180 degrees.PG269 (v2.2) October 30, 2019Zynq UltraScale RFSoC RF Data ConverterSend Feedbackwww.xilinx.com20
Chapter 3: Product SpecificationTable 6: Real Time NCO Signal Interface Ports for RF-DACs (cont'd)Port Name1I/OClockIns axi aclkdacXY nco phase rstDescriptionNCO phase reset. Used to align the NCO phasesacross the converter.Enable register writesdacXY update enable[5:0]IndacX update requestIns axi aclks axi aclk Bit 5: Enable write to phase resetBit 4: Enable write to NCO phase bits 17:16Bit 3: Enable write to NCO phase bits 15:0Bit 2: Enable write to NCO frequency bits 47:32Bit 1: Enable write to NCO frequency bits 31:16Bit 0: Enable write to NCO frequency bits 15:0Asserted High to request an update of the NCOsettings.Update busy registerdacX nco update busy[1:0]Outs axi aclk dac0 sysref int gatingIndac0 sysref int reenableInBit 1: High while SYSREF is disabled. Applicablefor RF-DAC tile 228 when multi-tilesynchronization has been selectedBit 0: High when the NCO update is in progress.s axi aclkApplicable for RF-DAC tile 228 when multi-tilesynchronization is enabled. When asserted thedisabling of the SYSREF is carried out by the IPcore.s axi aclkApplicable for RF-DAC tile 228 when multi-tilesynchronization is enabled. When asserted the IPcore re-enables the SYSREF after the NCO updateprocess has completed. In multi-device systems alldevices should be re-enabled at the same time.Notes:1.X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).Clock Ports Common to RF-ADC TileTable 7: Clock Ports Common to RF-ADC TilePort Name1I/OClockadcX clk pInN/ARF-ADC on-chip PLL reference clock or samplingclock inputadcX clk nInN/ARF-ADC on-chip PLL reference clock or samplingclock inputOutN/AOutput clock to user logicclk adcXD
DAC DAC ADC ADC. X19532-062819. Figur e 2: RF-ADC Tile Structure. mX0_axis Data Path ADC VinX0 mX1_axis Data Path ADC VinX1 mX2_axisData Path ADC VinX2 mX3_axis Data Path ADCVinX3 mX3_axis mX1_axis ADC mX0_axis Data Path ADC Data Path ADC VinX_23 VinX_01 Data Path Data Path Dual RF-ADC Tile Quad RF-ADC Tile. X23275-100919. Chapter 2: Overview
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
Zynq Migration Guide 6 UG1213 (v3.0) November 22, 2019 www.xilinx.com Chapter 1:Introduction Video codec unit (VCU): Simultaneous Encode and Decode through separate cores H.264 high profile level 5.2 (4Kx2K-60) H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate 8-bit and 10-bit encoding 4:2:0 and 4:2:2 chroma sampling
Digilent PYNQ-Z1 Vitis and VIVADO Design Suite-2020.1 August 13, 2020 . PYNQ is an open-source project which allow to use Python language and libraries on the FPGA . Zynq UltraScale , Zynq RFSoC, Alveo accelerator boards and AWS-F1 to create high performance applications with: hi
U72 ECS-TXO-5032-122.8 12.288 MHz Clock Jitter Cleaner Reference (ADC/DAC) U1 ABLNO-V-122.88MHZ 122.88 MHz Clock Jitter Cleaner Reference (ADC/DAC) ZQ1 FA-238 25.0000MB 25 MHz USB3 HUB Controller ZQ2 FA-238 25.0000MB 25 MHz Etherne
UltraScale Architecture CLB User Guide www.xilinx.com 5 UG574 (v1.5) February 28, 2017 Chapter 1 Overview Introduction to UltraScale Architecture The Xilinx UltraScale architecture is a revo lutionary approach to creating programmable devices capable of addressing the massive I/O and memory bandwidth requirements of
UltraScale Architecture Memory Resources 7 UG573 (v1.12) March 17, 2021 www.xilinx.com Chapter 1: Block RAM Resources Zynq UltraScale MPSoC devices provide 64-bit processor scalability while combining real-
Zrunners-repeaters-strangers-aliens [ (RRSA) (Parnaby, 1988; Aitken et al., 2003). This model segments inputs of demand from customers (in this case, the requests from researchers for data cleared for publication) and uses the different characteristics of those segments to develop optimal operational responses. Using this framework, we contrast how the rules-based and principles-based .
