Zynq UltraScale RFSoC RF Data Converter V2.6 Gen 1/2/3 LogiCORE IP .
Zynq UltraScale RFSoC RFData Converter v2.6 Gen1/2/3/DFELogiCORE IP Product GuidePG269 (v2.6) April 20, 2022Xilinx is creating an environment where employees, customers, andpartners feel welcome and included. To that end, we’re removing noninclusive language from our products and related collateral. We’velaunched an internal initiative to remove language that could excludepeople or reinforce historical biases, including terms embedded in oursoftware and IPs. You may still find examples of non-inclusivelanguage in our older products as we work to make these changes andalign with evolving industry standards. Follow this link for moreinformation.
Table of ContentsChapter 1: Introduction. 5Features. 5IP Facts.6Chapter 2: Overview.7Navigating Content by Design Process. 8Conventions. 9RF-ADC. 13RF-DAC. 19Applications.23Licensing and Ordering. 23Chapter 3: Product Specification. 24Performance. 27Resource Use. 27Port Descriptions.27Register Space. 38Chapter 4: Designing with the Core. 51IP Core Configuration in the Vivado Design Suite.51Software Driver.51RF-ADC. 52RF-DAC. 109Quadrature Modulator Correction .158Coarse Delay. 160Dynamic Update Events. 161PLL.163Interrupt Handling. 165Clocking. 170Resets.181Power-up Sequence. 182TDD Mode (Gen 3/DFE). 185PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com2
Bitstream Reconfiguration.188Interfacing to the AXI4-Stream Interface. 189Applications Overview. 190Chapter 5: Design Flow Steps.213Customizing and Generating the Core. 213Simulation. 233Synthesis and Implementation. 234Chapter 6: Example Design. 235RF-ADC Data Capture Block. 236RF-DAC Data Stimulus Block. 238Digital Data Format.240Chapter 7: Test Bench.242Analog Signaling. 244Appendix A: Upgrading. 247Changes from V2.5 to V2.6. 247Changes from V2.4 to V2.5. 248Changes from V2.3 to V2.4. 249Changes from V2.2 to V2.3. 249Changes from V2.1 to V2.2. 250Changes from V2.0 to V2.1. 250Changes from V1.2 to V2.0. 251Changes from V1.1 to V1.2. 252Appendix B: Debugging.254Finding Help on Xilinx.com. 254Debug Tools. 255Hardware Debug. 256Interface Debug. 256Appendix C: Zynq UltraScale RFSoC RF Data Converter Baremetal/Linux Driver. 258Overview.258Data Structures.259User API Functions. 281Interrupt Handling. 355PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com3
Appendix D: RF Analyzer.362Clocking. 364Address Space.366User Interface. 366Hardware Trigger. 367Appendix E: Additional Resources and Legal Notices.369Xilinx Resources.369Documentation Navigator and Design Hubs. 369References.369Revision History. 370Please Read: Important Legal Notices. 377PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com4
Chapter 1: IntroductionChapter 1IntroductionThe Xilinx LogiCORE IP Zynq UltraScale RFSoC RF Data Converter IP core provides aconfigurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integratordesigns.IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for theactual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC SwitchingCharacteristics (DS926). Note that Dual and Quad refers to the tile configuration and not the number ofconverters.Features Up to 16 14-bit RF-DACs Gen 1/Gen 2: Four 12-bit Dual RF-ADC tiles, or four 12-bit Quad RF-ADC tiles Gen 3: One, two, or four 14-bit Dual RF-ADC tiles, and/or two or four 14-bit Quad RF-ADCtiles DFE: One or three 14-bit Dual RF-ADC tiles, and/or two 14-bit Quad RF-ADC tiles Supports alignment between multiple converters (Multi-Tile Synchronization (MTS)) Pre-programs RF-DAC and RF-ADC with key user-defined parameters Multiple AXI4-Stream data interfaces for RF-ADCs and RF-DACs Single AXI4-Lite configuration interface Gen 1/Gen 2: 1x (bypass), 2x, 4x, 8x decimation and interpolation Gen 3/DFE: 1x (bypass), 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x decimation andinterpolation with additional 2x interpolation after mixer Digital complex mixers and Numerical Controlled Oscillator (NCO) Quadrature Modulation Correction (QMC) Gen 3/DFE: Embedded Digital Step Attenuator (DSA) for each RF-ADC, and Variable OutputPower (VOP) control for each RF-DAC On-chip clocking system including PLL for each tile Gen 3/DFE: On-chip clock distribution networkPG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com5
Chapter 1: Introduction Gen 3/DFE: TDD mode support power saving mode and RX/Obs sharing modeIP FactsLogiCORE IP Facts TableCore SpecificsSupported DeviceFamily1Zynq UltraScale RFSoCSupported User InterfacesAXI4-Stream, AXI4-Lite Control/StatusResourcesPerformance and Resource Use web pageProvided with CoreDesign FilesRTLExample DesignVerilogTest BenchVerilogConstraints FileXilinx Design Constraints (XDC)Simulation ModelSupported S/WDriver2VerilogStandalone and LinuxTested Design Flows3Design EntryVivado IP integratorSimulationFor supported simulators, see the Xilinx Design Tools: Release Notes Guide.SynthesisVivado SynthesisSupportRelease Notes and Known IssuesMaster Answer Record: 69907All Vivado IP Change LogsMaster Vivado IP Change Logs: 72775Xilinx Support web pageNotes:1.For a complete list of supported devices, see the Vivado IP catalog.2.Standalone driver details can be found in the software development kit Install Directory /Vitis/ Release /data/embeddedsw/doc/Xilinx drivers.htm.Bare-metal/Linux documentation is available in Appendix C: Zynq UltraScale RFSoC RF Data Converter Bare-metal/Linux Driver.3.For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com6
Chapter 2: OverviewChapter 2OverviewThe Xilinx Zynq UltraScale RFSoC family integrates the key subsystems required toimplement a complete software-defined radio including direct RF sampling data converters,enabling eCPRI and Gigabit Ethernet-to-RF on a single, highly programmable SoC.Each RFSoC offers multiple RF-sampling analog-to-digital (RF-ADC) and RF-sampling digital-toanalog (RF-DAC) data converters. The data converters are high-precision, high-speed and powerefficient. Both are highly configurable and tightly integrated with the programmable logic (PL)resources of the Zynq UltraScale RFSoC.The RF-ADC supports device-dependent sample rates and input signal frequencies listed in theZynq UltraScale RFSoC Data Sheet: Overview (DS889), with excellent dynamic range performance.The RF-DAC generates output carrier frequencies at rates defined in the Zynq UltraScale RFSoCData Sheet: DC and AC Switching Characteristics (DS926), depending on the device (see the ZynqUltraScale RFSoC Data Sheet: Overview (DS889) for device information.The RF data converters also include power efficient digital down converters (DDCs) and digital upconverters (DUCs) that include programmable interpolation and decimation rates, a numericallycontrolled oscillator (NCO), and a complex mixer. The DDCs and DUCs can also support multiband operation. The following figure shows the block diagram of the Zynq UltraScale RFSoCRF Data Converter.The RF-ADCs and RF-DACs are organized into tiles, each containing one, two, or four RF-ADCsor one, two, or four RF-DACs. Multiple tiles are available in each Zynq UltraScale RFSoC (seethe specific device data sheet for the number of tiles and converters per device). Each tile alsoincludes a block with a PLL and all the necessary clock handling logic and distribution routing forthe analog and digital logic.This guide describes the Zynq UltraScale RFSoC RF Data Converter IP core and softwaredrivers that are used to configure the data converters and instantiate them for use in a design.In this guide, reference is made to the Dual and Quad RF-ADCs, and the Dual (Gen 3/DFE) andQuad RF-DACs; for the actual sampling rate specifications see the Zynq UltraScale RFSoC DataSheet: DC and AC Switching Characteristics (DS926).For device specifications and additional information, see: Zynq UltraScale RFSoC Data Sheet: Overview (DS889) Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com7
Chapter 2: Overview Zynq UltraScale Device Technical Reference Manual (UG1085).Figure 1: Zynq UltraScale RFSoC RF Data Converter IP Core in Zynq UltraScale RFSoC(Gen 1/Gen 2/Gen 3/DFE)Zynq UltraScale RFSoCData Converter IP CoreDUCProcessing SystemQuad Arm Cortex-A53Dual Arm Cortex-R5AXI4-StreamDAC4 to 16 TX cControl andConfigurationDDCAXI4-StreamADCGTY SerialTransceivers4 to 16 RX ChannelsDDCAXI4-StreamADCX19532-043021Navigating Content by Design ProcessXilinx documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. All Versal ACAP design process DesignHubs and the Design Flow Assistant materials can be found on the Xilinx.com website. Thisdocument covers the following design processes: Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, functional simulation, and evaluating the Vivado timing,resource use, and power closure. Also involves developing the hardware platform for systemintegration. Topics in this document that apply to this design process include: Port DescriptionsPG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com8
Chapter 2: Overview Register Space Customizing and Generating the Core Appendix C: Zynq UltraScale RFSoC RF Data Converter Bare-metal/Linux DriverConventionsThis document covers different aspects of the Zynq UltraScale RF Data Converter hardware,IP, software driver, and covers Gen 3/DFE devices. The following naming conventions are usedfor convenience, conciseness, and clear information delivery.GenerationsThis document uses Gen x to distinguish different generations of the Zynq UltraScale RFData Converter family as below: Gen 1: XCZU2xDR Gen 2: XCZU39DR Gen 3: XCZU4xDR DFE: XCZU6xDRIn this document, items that are specific to Gen 3 and DFE are clearly identified as Gen 3/DFE.Dual and Quad RF-ADC/RF-DAC TilesThere are two types of converter tiles for the RF-ADCs, called Dual and Quad tiles. For RF-ADCs,the converters in the Dual tiles have different maximum sampling rates and different interleavingfactors to the Quad tiles. Gen 1/Gen 3/DFE devices have both type of tiles, while Gen 2 devicesconsist of Quad RF-ADC tiles only.Quad RF-DAC tiles are available in Gen 1/Gen 2 devices and Dual RF-DAC tiles are additionallyavailable in Gen 3/DFE devices; the Dual RF-DAC tiles have two dedicated DUCs for eachchannel to support dual-band applications. There is no performance difference betweenconverters in both types of RF-DAC tile.Note: In this document, colored table rows call attention to specific Gen 3/DFE device information.PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com9
Chapter 2: OverviewTable 1: Tile ConfigurationNumber ofConvertersDevice TypeQuad RF-ADC4Gen 1/Gen 2/Gen3/DFEEach RF-ADC has an interleaving factor of four.Dual RF-ADC2Gen 1/Gen 3/DFEEach RF-ADC has an interleaving factor of eight, hence doublethe sampling rate of the converters in the Quad RF-ADC tiles.Quad RF-DAC4Gen 1/Gen 2/Gen3/DFEEach RF-DAC has one dedicated DUC.Dual RF-DAC2Gen 3/DFETile TypeNotesEach RF-DAC has two dedicated DUCs. For Gen 3/DFE devicesfeaturing Quad RF-DACs or a combination of Quad and DualRF-DACs, all tiles have external clock inputs.Notes:1.Gen 3/DFE devices with one RF-ADC per tile are considered as Dual RF-ADCs with the upper ADC (input VinX 23)unavailable. All data paths are available for use on these devices. These devices do not support I/Q input signals.2.Gen 3/DFE devices with one RF-DAC per tile are considered as Dual RF-DACs with the upper DAC (output VoutX2)unavailable. All data paths are available for use on these devices. These devices do not support I/Q output signals.See the Zynq UltraScale RFSoC Data Sheet: Overview (DS889) for an overview of the maximumsampling rates and the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics(DS926) for the exact specifications.The following figures illustrate the tile structures. Dashed lines indicate multiple bands cases.Figure 2: RF-ADC Tile StructuremX3 axisData PathADCVinX3mX3 axismX2 axisData PathADCVinX2mX2 axismX1 axisData PathADCVinX1mX1 axismX0 axisData PathADCVinX0mX0 axisQuad RF-ADC TileQData PathADCVinX 23ADCVinX 01QData PathDual RF-ADC TileX23275-051821Note: Dual RF-ADC tile applies to Gen 1/3/DFE.PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com10
Chapter 2: OverviewFigure 3: RF-DAC Tile StructuresX3 axisData PathDACVoutX3sX3 axisData PathsX2 axisData PathDACVoutX2sX2 axisData PathsX1 axisData PathDACVoutX1sX1 axisData PathsX0 axisData PathDACVoutX0sX0 axisData PathQuad RF-DAC TileDACVoutX2DACVoutX0Dual RF-DAC TileX23273-051821Note: Dual RF-DAC tile applies to Gen 3/DFE.Figure 4: Single Converter Tile Structure (Gen 3)sX3 axisData PathmX3 axissX2 axisData PathmX2 axissX1 axisData PathmX1 axissX0 axisData PathDACVoutX0mX0 axisSingle RF-DAC TileQData PathQData PathADCVinX 01Single RF-ADC TileX24772-051821Note: Single RF-DAC and RF-ADC tiles apply to Gen 3.Sub-ADC and Interleaving FactorsXilinx uses interleaving technology to build the RF-ADCs. Each RF-ADC in a Dual RF-ADC tileconsists of eight sub-ADCs, and each RF-ADC in a Quad RF-ADC tile consists of four sub-ADCs.In this document, the number of sub-ADCs mentioned as the interleaving factor is either four forthe Quad RF-ADC tile or eight for the Dual RF-ADC tile. The higher the interleaving factor thehigher the maximum sampling rate that the RF-ADC can support.PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com11
Chapter 2: OverviewTile Mapping (Gen 1/Gen 2/Gen 3)Physically and for IP references, the RF-ADC tiles are named, following package bank allocation,Tile 224/225/226/227, and the RF-DAC tiles are named, Tile 228/229/230/231. In thesoftware driver API documents, ADC Tile0/1/2/3 and DAC Tile0/1/2/3 are used forprogramming convenience.Table 2: Tile Name MappingRF-ADCTile 224RF-DACADC Tile0Tile 228DAC Tile0Tile 225ADC Tile1Tile 229DAC Tile1Tile 226ADC Tile2Tile 230DAC Tile2Tile 227ADC Tile3Tile 231DAC Tile3Tile Mapping (DFE)Physically and for IP references, the RF-ADC tiles are named, following package bank allocation,Tile 224/225/226, and the RF-DAC tiles are named, Tile 227/228. In the software driver APIdocuments, ADC Tile0/1/2 and DAC Tile0/1 are used for programming convenience.Note: For details on the type of tiles available on each device, see the Zynq UltraScale RFSoC Data Sheet:Overview (DS889).Table 3: Tile Name Mapping (DFE)RF-ADCTile 224RF-DACADC Tile0Tile 227DAC Tile0Tile 225ADC Tile1Tile 228DAC Tile1Tile 226ADC Tile2––External Clock InputsIn some devices not all tiles have an external clock input. In Gen 1/Gen 2 devices, all tiles have an external clock input. In Gen 3 devices, all RF-ADC tiles have an external clock input. In tiles featuring Quad RFDACs, all RF-DAC tiles have an external clock input. If only Dual RF-DAC tiles are present, theodd RF-DAC tiles (RF-DAC Tile 1 and 3) do not have an external clock input. In DFE and XCZU42DR devices, the bottom RF-ADC tile (RF-ADC Tile 0) does not have anexternal clock input. All other tiles have an external clock input.PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com12
Chapter 2: OverviewEnabled tiles without an external clock input should be configured to receive their clock fromanother tile on the device. In Gen3/DFE, any tile without an external clock input needs to get itsclock from the internal distributionRelated InformationOn-chip Clock Distribution (Gen 3/DFE)Channel, Block, and SliceEach RF-ADC or RF-DAC in the tile is called a channel. The terms, block and slice are also used inthe driver API. In this document, channel, block, and slice have the same meaning.Tn ClockIn some parts of this document Tn (where n can be 1, 2, 4, 8, etc.) is used to represent a clock. T1indicates a root clock, while Tn clock indicates the T1 clock divided by n. For example, T1 dividedby eight is called T8, its period is eight times T1, and its frequency is T1/8.In most places, the T1 clock indicates the sampling clock, regardless of whether it comes from anexternal or on-chip PLL.API and Registers AccessThe way to access the Zynq UltraScale RF Data Converter for status and configuration at runtime is using the RFdc driver API. Direct register access is not supported unless clearly indicatedin this document.RF-ADCThere are two types of RF-ADC tile, the Dual RF-ADC and the Quad RF-ADC tile. The type oftile available is device dependent (see the Zynq UltraScale RFSoC Data Sheet: Overview (DS889)).Each tile includes a PLL and clocking circuit. All RF-ADCs within a tile share this commonclocking infrastructure.The Quad RF-ADC tile consists of four RF-ADCs, arranged in two pairs. Each of these converterscan be configured individually for real input signals or, as a pair, for I/Q input signals. Thefollowing figures show an overview of the Quad RF-ADC tile for Gen 1/Gen 2 and Gen 3/DFE.PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com13
Chapter 2: OverviewFigure 5: Quad RF-ADC Tile Overview (Gen 1/Gen 2)VCMVIN PVIN NIADCBUFChannel0 I90 Q0 90 VIN PVIN NADCBUFChannelQNCONCOSampling Clock/PLL Reference ClockSampling ClockADC CLK PADC CLK NDDCPLLVIN PVIN NBUFIADCChannel0 I90 0 90 VIN PVIN NBUFADCChannelQQNCONCOVCMX18282-060220PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com14
Chapter 2: OverviewFIFOFigure 6: Quad RF-ADC Tile Overview (Gen 3/DFE)50 ΩADC50 ΩDSAFIFOVcm50 ΩADC50 ΩDSAFIFOPLLADC50 Ω50 ΩDSAFIFOVcm50 ΩADC50 ΩDSAX23158-093019PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com15
Chapter 2: OverviewThe Dual RF-ADC tile consists of two RF-ADCs. These converters can be configured individuallyfor real input signals or, as a pair, for I/Q input signals. The following figures show an overview ofthe Dual RF-ADC tile for Gen 1/Gen 2 and Gen 3/DFE.Figure 7: Dual RF-ADC Tile Overview (Gen 1/Gen 2)VCMIVIN P100 ΩVIN NRFADCADCBUFChannel4GS/s12-bits0 90 QNCOSampling Clock/PLL Reference ClockSampling ClockADC CLK PDDC100 ΩADC CLK NPLLIVIN P100 ΩVIN NBUFRFADCADCChannel4GS/s12-bits0 90 QVCMNCOX18283-060220PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com16
Chapter 2: OverviewFIFOFigure 8: Dual RF-ADC Tile Overview (Gen 3/DFE)50 ΩADCFIFO50 ΩDSAVcmFIFOPLLFIFOADC50 Ω50 ΩDSAVcmX23156-082820RF-ADC Features Tile configuration Four or two RF-ADCs and one PLL per tileGen 1/Gen 2: 12-bit RF-ADC resolution, with 16-bit digital signal processing datapath;each 12-bit data stream is MSB-aligned to 16-bit samples at the output of the RF-ADCcore before passing to the DDC blockGen 3/DFE: 14-bit RF-ADC resolution, with 16-bit digital signal processing datapath; each14-bit data stream is MSB-aligned to 16-bit samples at the output of the RF-ADC corebefore passing to the DDC blockImplemented as either four channels (Quad) or two channels (Dual) (the sampling rate isdevice dependent; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926))PG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com17
Chapter 2: Overview Decimation filters Gen 1/Gen 2: 1x (bypass filter), 2x, 4x, 8x Gen 3/DFE: 1x (bypass filter), 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x 80% of Nyquist bandwidth, 89 dB stop-band attenuation Digital Complex Mixers Full complex mixers support real or I/Q inputs from the RF-ADC 48-bit Numeric Controlled Oscillator (NCO) per RF-ADC Fixed Fs/4, Fs/2 low power frequency mixing mode, where Fs is the sample frequencyI/Q and real input signals supported Single/multi-band flexibility 2x bands per RF-ADC pair 4x bands per Quad RF-ADC tile Can be configured for real or I/Q inputs Full bandwidth of the RF-ADC can be accessed in bypass mode Input signal amplitude threshold: Two programmable threshold flags per RF-ADC Built-in digital correction for external analog quadrature modulators: Supports gain, phase, and offset correction for an I/Q input pair (two RF-ADCs) SYSREF input signal for multi-channel synchronization Flexible AXI4-Stream interface supports a wide range of programmable logic clock rates andconverter sample rates Per tile current-mode logic (CML) clock input buffer with on-chip calibrated 100Ωtermination; supplies the RF-ADC sampling clocks or provides a reference clock for the onchip PLL Dedicated high-speed, high-performance, differential input buffer per RF-ADC with on-chipcalibrated 100Ω termination (on-die termination) Output common mode reference voltage for DC-coupling RF-ADC inputs Gen 3/DFE: Digital Step Attenuator (DSA) Gen 3/DFE: Power saving mode in Time Division Duplexing (TDD) application Gen 3/DFE: Different decimation factors and FIFO data rates for RX and Observation channelin the Time Division Duplexing (TDD) applicationPG269 (v2.6) April 20, 2022Zynq UltraScale RFSoC RF Data Converter Gen 1/2/3/DFESend Feedbackwww.xilinx.com18
Chapter 2: OverviewRF-DACIn Gen 1/Gen 2 devices each RF-DAC tile consists of four RF-DACs that can be configuredindividually for real output signals or, as a pair, for I/Q output signal generation. In Gen 3/DFEdevices each RF-DAC tile consists of two or four RF-DACs that can be similarly configured. EachRF-DAC
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
Zynq Migration Guide 6 UG1213 (v3.0) November 22, 2019 www.xilinx.com Chapter 1:Introduction Video codec unit (VCU): Simultaneous Encode and Decode through separate cores H.264 high profile level 5.2 (4Kx2K-60) H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate 8-bit and 10-bit encoding 4:2:0 and 4:2:2 chroma sampling
Digilent PYNQ-Z1 Vitis and VIVADO Design Suite-2020.1 August 13, 2020 . PYNQ is an open-source project which allow to use Python language and libraries on the FPGA . Zynq UltraScale , Zynq RFSoC, Alveo accelerator boards and AWS-F1 to create high performance applications with: hi
U72 ECS-TXO-5032-122.8 12.288 MHz Clock Jitter Cleaner Reference (ADC/DAC) U1 ABLNO-V-122.88MHZ 122.88 MHz Clock Jitter Cleaner Reference (ADC/DAC) ZQ1 FA-238 25.0000MB 25 MHz USB3 HUB Controller ZQ2 FA-238 25.0000MB 25 MHz Etherne
UltraScale Architecture CLB User Guide www.xilinx.com 5 UG574 (v1.5) February 28, 2017 Chapter 1 Overview Introduction to UltraScale Architecture The Xilinx UltraScale architecture is a revo lutionary approach to creating programmable devices capable of addressing the massive I/O and memory bandwidth requirements of
DAC DAC ADC ADC. X19532-062819. Figur e 2: RF-ADC Tile Structure. mX0_axis Data Path ADC VinX0 mX1_axis Data Path ADC VinX1 mX2_axisData Path ADC VinX2 mX3_axis Data Path ADCVinX3 mX3_axis mX1_axis ADC mX0_axis Data Path ADC Data Path ADC VinX_23 VinX_01 Data Path Data Path Dual RF-ADC Tile Quad RF-ADC Tile. X23275-100919. Chapter 2: Overview
UltraScale Architecture Memory Resources 7 UG573 (v1.12) March 17, 2021 www.xilinx.com Chapter 1: Block RAM Resources Zynq UltraScale MPSoC devices provide 64-bit processor scalability while combining real-
The external evaluation of the National Plan on Drugs and Drug Addiction 2005-2012 is taking place now and the final report will be presented in December 2012, which will include recommendations for the next policy cycle. The final report of the internal evaluation of both Plans (Drugs and Alcohol) will be presented by the end of 2012 for approval of the Inter-ministerial Council. Drug use in .
