Through Silicon Via Technology Status - NASA

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Through Silicon Via (TSV)Technology StatusJerry Mulder, JPLR. Peter Dillon, JPLJune 12, 2012To be presented by Jerry Mulder at the 3rd NASA Electronic Parts and Packaging (NEPP) Electronics Technology Workshop (ETW),NASA Goddard Space Flight Center in Greenbelt, MD, June 11-13, 2012 and published on nepp.nasa.gov

Through Silicon Via (TSV) TechnologyStatus Outline Task Overview TSV Technology Overview Application Examples–––– Imager CSPMemory CubeLogic and Memory2.5D/Xilinx Virtex 72.5D and 3D TSV CommercializationTSV Processing: Many ChoicesOther enabling technologiesPotential reliability issuesFuture of technologyCoexisting with 3D TSVConclusions and Future WorkAcknowledgements

Through Silicon Via (TSV) TechnologyTask Overview Our goal is to review the technology readiness andcurrent state-of-the-art of through silicon viatechnology as it relates to NASA missions, applications,and environments. Examine industry trends, applications, manufacturingmethods and concerns, cost considerations, vendors,reliability issues and potential show stoppers, and thefuture of TSV technology. Approach in this phase: Literature review of TSVindustry, services, methods and processes,applications, issues and reliability, and forecasts.Directly engage TSV service providers and users.

TSV Technology Overview Through silicon vias (TSVs): electrical interconnectsthrough a silicon die or wafer. Alternative to wire bonding and printed electricalinterconnects in 2.5D and 3D packaging. Technology Driver: Reduced interconnect length forincreased performance. Commercial applications continue to emerge forsensors, memory, and FPGAs.a.Motoyoshi, M., “Through-Silicon Via (TSV)” inProceedings of the IEEE, vol. 97, 2009, pp. 43-48b.From earch/Post/2/616.html)Fig. 1 Commercial applications emerging for TSV technology include(a) sensors, (b) memory, and FPGA (not shown).Motoyoshi, M., “Through-Silicon Via (TSV)” inProceedings of the IEEE, vol. 97, 2009, pp. 43-48

Application Example: Imager CSPSource: Motoyoshi, M., “Through-Silicon Via (TSV)” inProceedings of the IEEE, vol. 97, 2009, pp. 43-4820012008TSVLeti Early adopters Interconnects do notinterfere with top sideimaging sensor. Direct attach can bemade to processingchip, reducinginterconnect length,and increasingperformance.Source: Jerray A., “From 3D technology to 3D-IC demonstratorsand associated design flow”, GSA EDA Interest Group, 2011 Feb. 25th

Application Example: Memory cube The Hybrid Memory Cube (HMC)Consortium– Memory industry leaders including Micron andSamsung. Recent Micron demonstration:– Peak throughput of 128GB/s compared to the12.8GB/s. commercial-grade DDR3 modules created on aplanar process.– Micron's prototype modules showing a 70 percent reduction in power draw during datatransfer in a module one-tenth the size ofcurrent-generation technologies. The Hybrid Memory Cube Consortium andindustry leaders (e.g. Altera, IBM, OpenSilicon, Xilinx and Microsoft) readying draftinterface specification for HMC memory. Drivers: improved memory bandwidth andperformance; decreased energy and latencyfor moving data between memory arraysand processor cores.Source: crosofthmc-tech/1

Application Example:Logic and Memory Improved processor/memory performance.Source: CTILeti/ST Micro 3D appears to be a cost effectiveapproach to manage increasingmemory needs and shrinkingshare of logic area.– Fewer packages, improveddevice yield from chippartitioning, lowerpower fewer extras needed Enables integration of additionaltechnology.– Analog, RF, Sensors/MEMSSource: Global Semiconductor Alliance (GSA) EDA Interest Group Meeting April 20, 2011

Application Example: 2.5D– Low area impact (no keep outareas required).– No impact to IC performance.– Less disruptive process.– Layout techniques similar toPWBs. Xilinx Virtex 7– Die partitioning improves yieldSource: S. Cheramy, EMPC 2009 Vias in passive Si interposer Alternative to 3D. Supports integration of multipletechnologies including passives. Potential advantages over 3D(at this time):45nm technology on 130nm interposer1056 inter-chip connections588 TSVs482 bumps

Xilinx Virtex 7Rahman, A, “Stacked-Silicon Interconnect Technology” Xilinx, Inc. GSA-EDA Forum, December 8 2010

2.5D and 3D TSV CommercializationSource: Dr. Phil Garrou, YOLE; http://www.i-micronews.com/lectureArticle.asp?id 6351

TSV Processing:Many Choices FEOL: Front end ofline BEOL: Back end of line Via First (polysiliconfilled via): TSVsfabricated beforetransistors. Via Middle (copperfilled via): TSVfabricated beforecopper interconnects. Via Last (copperliner): TSVs fabricatedafter bonding thestack.Via FirstVia MiddleP. Garrou, “Wafer Level 3D Integration,” presented at Peaks in Packaging WhitefishMontana, Sept. 5–7, 2007.Emerging as leading candidates

TSV Processing: More Choices Via Processing– Deep reactive-ion etching– Laser– Other (e.g. wet chemical etch) Via Metallization–––––Copper electroplating (fill and conformal)TungstenPolysilicon10μm / 160μm deep viaCopper paste printingDRIE Etch rate: 9 μm/minOther (doped silicon, Au plating)Source: Puech, M. from “DRIE for Through Silicon Via” Interconnects––––Alcatel Micro Machining Systems; EMC3DFlip chip ball or stud bump ( 100 µm)SnAg and Cu pillars and solder-free µinserts (e.g. Ni) (100-30 µm)µtubes (30-10 µm)Cu-Cu direct bonding ( 5 µm)

TSV Processing: Still more choicesSource: Barth, J., “3D Design using 2D tools” GSA EDA Interest Group Meeting, February 25, SAEDAInterest-Barth-20110225-IBMrelease.pdf

Other Enabling Technologies 3D Electronic Design Automation(EDA) Tools Input IC Testing (i.e. known good die) Planarization Wafer Thinning/Handling Alignment Bonding TestingSource: CL Young 2011web.mst.edu/ yshi/3D clock DAC11 2011-03-30-4DAC.pdf

Potential Reliability Issues Design challenges:– Present variety of vias and processes muddy the reliability water– Stress management Via fabrication may induce tensile stresses in siliconVias may experience compressive 'hoop' stresses which could lead to via buckling.Quantity and spacing of vias may result in undesirable stress fieldsThermally induced stresses due to CTE mismatch may lead to cracking of the silicon wafer.– Thermal management: Potentially large and non-uniform heat flow.– Redundancy (or the lack of, particularly for space applications) Process challenges:––––Metal voiding during fillingUniform via wall material depositionActive IC surface connectivityWafer handling Performance challenges:–––––Available reliability data is limitedThermal cyclingElectromigrationSi depletion at/around viaShock/vibrationSource: CL Young 2011web.mst.edu/ yshi/3D clock DAC11 2011-03-30-4DAC.pdf

Future of Technology A variety of 3D IC standards programs underway– Sematch and SEMI driving manufacturing standards– GSA, 3D SiG, and Si2 driving design standards– Also, JEDEC, IEEE, 3D-IC Alliance, and SRC 2015 Largest market share will likely be Logic and Memory SiPmodules– (Source:Yole Development, GSA EDA Interest Group meeting, September 2010)Thinning and handling thin ( 15 µm) thick die/waferVia densities to 105/chipNew materials for thermal management, via fill, and underfillIntegrated and/or embedded passivesVia in glassHeterogeneous integration (Sensor, processor, memory,communication SiP)

Coexisting with 3D TSVSource: CadenceWire bonding is the predominant3D interconnect technology.Vertical Circuits, Inc.’sVertical Interconnect Pillar(VIP) technologyinterconnecting an 8 diememory stackSource: Vertical Circuits, Inc.

Conclusions and Future Work TSV technology is going mainstream with large diepartitioning, logic memory, and stacked memoryhitting the market. The applications are really performance driven. TSVjust happens to provide the most cost effectivesolution to satisfy performance requirements. NASA engineers will want to use these devices (FPGA)in NASA environments (LEO and beyond) but theexisting ground based reliability data is still limited. Testing standards are still being developed. Attending Semicon West 2012 in July. Will continue to drill down on potential reliabilityconcerns, failure mechanisms, and avenues for riskmitigation.

Acknowledgements The investigators gratefully acknowledge the fundingprovided for this work by the NASA Electronic Parts andPackaging program under NASA WBS 724297.40.49.11 The investigators wish to thank NEPP co-managersMike Sampson and Ken LaBel for their support. The investigators also wish to recognize Drs. Charles“Chuck” Barnes, Doug Sheldon, Reza Ghaffarian,Rajeshuni “Ram” Ramesham, and Jong-ook Suh fortheir support, guidance, and valuable discussions.

Through Silicon Via (TSV) Technology Task Overview Our goal is to review the technology readiness and current state-of-the-art of through silicon via technology as it relates to NASA missions, applications, and environments. Examine industry trends, applications, manufacturing methods and concerns, cost considerations, vendors,

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