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Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group (JTAG) and in-system programmability (ISP) information, DC operating conditions, AC timing parameters, and ordering information for MAX II devices. This section includes the following chapters: Chapter 1, Introduction Chapter 2, MAX II Architecture Chapter 3, JTAG and In-System Programmability Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices Chapter 5, DC and Switching Characteristics Chapter 6, Reference and Ordering Information Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. August 2009 Altera Corporation MAX II Device Handbook

I–2 MAX II Device Handbook Section I: MAX II Device Family Data Sheet Revision History August 2009 Altera Corporation

1. Introduction MII51001-1.9 Introduction The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control. Features The MAX II CPLD has the following features: August 2009 Low-cost, low-power CPLD Instant-on, non-volatile architecture Standby current as low as 25 µA Provides fast propagation delay and clock-to-output times Provides four global clocks with two clocks available per logic array block (LAB) UFM block up to 8 Kbits for non-volatile storage MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors Schmitt triggers enabling noise tolerant inputs (programmable per pin) I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz Supports hot-socketing Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ISP circuitry compliant with IEEE Std. 1532 Altera Corporation MAX II Device Handbook

1–2 Chapter 1: Introduction Features Table 1–1 shows the MAX II family features. Table 1–1. MAX II Family Features Feature EPM240 EPM240G EPM570 EPM570G EPM1270 EPM1270G EPM2210 EPM2210G EPM240Z EPM570Z 240 570 1,270 2,210 240 570 LEs Typical Equivalent Macrocells 192 440 980 1,700 192 440 128 to 240 240 to 570 570 to 1,270 1,270 to 2,210 128 to 240 240 to 570 8,192 8,192 8,192 8,192 8,192 8,192 Maximum User I/O pins 80 160 212 272 80 160 tPD1 (ns) (1) 4.7 5.4 6.2 7.0 7.5 9.0 fCNT (MHz) (2) 304 304 304 304 152 152 tSU (ns) 1.7 1.2 1.2 1.2 2.3 2.2 tCO (ns) 4.3 4.5 4.6 4.6 6.5 6.7 Equivalent Macrocell Range UFM Size (bits) Notes to Table 1–1: (1) tP D1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic implemented in a single LUT and LAB that is adjacent to the output pin. (2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number. f For more information about equivalent macrocells, refer to the MAX II Logic Element to Macrocell Conversion Methodology white paper. MAX II and MAX IIG devices are available in three speed grades: –3, –4, and –5, with –3 being the fastest. Similarly, MAX IIZ devices are available in three speed grades: –6, –7, and –8, with –6 being the fastest. These speed grades represent the overall relative performance, not any specific timing parameter. For propagation delay timing numbers within each speed grade and density, refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook. Table 1–2 shows MAX II device speed-grade offerings. Table 1–2. MAX II Speed Grades Speed Grade Device EPM240 –3 –4 –5 –6 –7 –8 v v v — — — v v v — — — v v v — — — v v v — — — EPM240G EPM570 EPM570G EPM1270 EPM1270G EPM2210 EPM2210G MAX II Device Handbook EPM240Z — — — v v v EPM570Z — — — v v v August 2009 Altera Corporation

Chapter 1: Introduction Features 1–3 MAX II devices are available in space-saving FineLine BGA, Micro FineLine BGA, and thin quad flat pack (TQFP) packages (refer to Table 1–3 and Table 1–4). MAX II devices support vertical migration within the same package (for example, you can migrate between the EPM570, EPM1270, and EPM2210 devices in the 256-pin FineLine BGA package). Vertical migration means that you can migrate to devices whose dedicated pins and JTAG pins are the same and power pins are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must lay out for the largest planned density in a package to provide the necessary power pins for migration. For I/O pin migration across densities, cross reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus II software can automatically cross-reference and place all pins for you when given a device migration list. Table 1–3. MAX II Packages and User I/O Pins 144-Pin TQFP 144-Pin Micro FineLine BGA (1) 256-Pin Micro FineLine BGA (1) 256-Pin FineLine BGA 324-Pin FineLine BGA 80 — — — — — 76 76 116 — 160 160 — — — — 116 — 212 212 — — — — — — — — 204 272 EPM240Z 54 80 — — — — — — — EPM570Z — 76 — — — 116 160 — — 256-Pin Micro FineLine BGA 256-Pin FineLine BGA 324-Pin FineLine BGA Device 68-Pin Micro FineLine BGA (1) 100-Pin Micro FineLine BGA (1) 100-Pin FineLine BGA 100-Pin TQFP — 80 80 — 76 — EPM240 EPM240G EPM570 EPM570G EPM1270 EPM1270G EPM2210 EPM2210G Note to Table 1–3: (1) Packages available in lead-free versions only. Table 1–4. MAX II TQFP, FineLine BGA, and Micro FineLine BGA Package Sizes 68-Pin Micro FineLine BGA 100-Pin Micro FineLine BGA 100-Pin FineLine BGA 100-Pin TQFP 144-Pin TQFP 144-Pin Micro FineLine BGA Pitch (mm) 0.5 0.5 1 0.5 0.5 0.5 0.5 1 1 Area (mm2) 25 36 121 256 484 49 121 289 361 5 5 6 6 11 11 16 16 22 22 7 7 11 11 17 17 19 19 Package Length width (mm mm) August 2009 Altera Corporation MAX II Device Handbook

1–4 Chapter 1: Introduction Referenced Documents MAX II devices have an internal linear voltage regulator which supports external supply voltages of 3.3 V or 2.5 V, regulating the supply down to the internal operating voltage of 1.8 V. MAX IIG and MAX IIZ devices only accept 1.8 V as the external supply voltage. MAX IIZ devices are pin-compatible with MAX IIG devices in the 100-pin Micro FineLine BGA and 256-pin Micro FineLine BGA packages. Except for external supply voltage requirements, MAX II and MAX II G devices have identical pin-outs and timing specifications. Table 1–5 shows the external supply voltages supported by the MAX II family. Table 1–5. MAX II External Supply Voltages EPM240 EPM570 EPM1270 EPM2210 EPM240G EPM570G EPM1270G EPM2210G EPM240Z EPM570Z (1) 3.3 V, 2.5 V 1.8 V 1.5 V, 1.8 V, 2.5 V, 3.3 V 1.5 V, 1.8 V, 2.5 V, 3.3 V Devices MultiVolt core external supply voltage (VC CINT) (2) MultiVolt I/O interface voltage levels (VC CIO) Notes to Table 1–5: (1) MAX IIG and MAX IIZ devices only accept 1.8 V on their VCCINT pins. The 1.8-V VCC INT external supply powers the device core directly. (2) MAX II devices operate internally at 1.8 V. Referenced Documents This chapter references the following documents: DC and Switching Characteristics chapter in the MAX II Device Handbook MAX II Logic Element to Macrocell Conversion Methodology white paper Document Revision History Table 1–6 shows the revision history for this chapter. Table 1–6. Document Revision History Date and Revision Changes Made Summary of Changes August 2009, version 1.9 Updated Table 1–2. October 2008, version 1.8 Updated “Introduction” section. Updated new Document Format. December 2007, version1.7 Updated Table 1–1 through Table 1–5. Added “Referenced Documents” section. December 2006, version 1.6 Added document revision history. — August 2006, version 1.5 Minor update to features list. — July 2006, version 1.4 Minor updates to tables. — MAX II Device Handbook Added information for speed grade –8 — Updated document with MAX IIZ information. August 2009 Altera Corporation

Chapter 1: Introduction Document Revision History 1–5 Table 1–6. Document Revision History Date and Revision Changes Made Summary of Changes June 2005, version 1.3 Updated timing numbers in Table 1-1. — December 2004, version 1.2 Updated timing numbers in Table 1-1. — June 2004, version 1.1 Updated timing numbers in Table 1-1. — August 2009 Altera Corporation MAX II Device Handbook

1–6 MAX II Device Handbook Chapter 1: Introduction Document Revision History August 2009 Altera Corporation

2. MAX II Architecture MII51002-2.2 Introduction This chapter describes the architecture of the MAX II device and contains the following sections: “Functional Description” on page 2–1 “Logic Array Blocks” on page 2–4 “Logic Elements” on page 2–6 “MultiTrack Interconnect” on page 2–12 “Global Signals” on page 2–16 “User Flash Memory Block” on page 2–18 “MultiVolt Core” on page 2–22 “I/O Structure” on page 2–23 Functional Description MAX II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs). The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs. The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures. The MAX II device I/O pins are fed by I/O elements (IOE) located at the ends of LAB rows and columns around the periphery of the device. Each IOE contains a bidirectional I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, and LVTTL. MAX II devices provide a global clock network. The global clock network consists of four global clock lines that drive throughout the entire device, providing clocks for all resources within the device. The global clock lines can also be used for control signals such as clear, preset, or output enable. October 2008 Altera Corporation MAX II Device Handbook

2–2 Chapter 2: MAX II Architecture Functional Description Figure 2–1 shows a functional block diagram of the MAX II device. Figure 2–1. MAX II Device Block Diagram IOE IOE IOE IOE IOE IOE IOE Logic Element Logic Element Logic Element IOE Logic Element Logic Element Logic Element IOE Logic Element Logic Element Logic Element IOE Logic Element Logic Element Logic Element Logic Array BLock (LAB) MultiTrack Interconnect MultiTrack Interconnect Each MAX II device contains a flash memory block within its floorplan. On the EPM240 device, this block is located on the left side of the device. On the EPM570, EPM1270, and EPM2210 devices, the flash memory block is located on the bottom-left area of the device. The majority of this flash memory storage is partitioned as the dedicated configuration flash memory (CFM) block. The CFM block provides the nonvolatile storage for all of the SRAM configuration information. The CFM automatically downloads and configures the logic and I/O at power-up, providing instant-on operation. f For more information about configuration upon power-up, refer to the Hot Socketing and Power-On Reset in MAX II Devices chapter in the MAX II Device Handbook. A portion of the flash memory within the MAX II device is partitioned into a small block for user data. This user flash memory (UFM) block provides 8,192 bits of general-purpose user storage. The UFM provides programmable port connections to the logic array for reading and writing. There are three LAB rows adjacent to this block, with column numbers varying by device. Table 2–1 shows the number of LAB rows and columns in each device, as well as the number of LAB rows and columns adjacent to the flash memory area in the EPM570, EPM1270, and EPM2210 devices. The long LAB rows are full LAB rows that extend from one side of row I/O blocks to the other. The short LAB rows are adjacent to the UFM block; their length is shown as width in LAB columns. MAX II Device Handbook October 2008 Altera Corporation

Chapter 2: MAX II Architecture Functional Description 2–3 Table 2–1. MAX II Device Resources LAB Rows UFM Blocks LAB Columns Long LAB Rows Short LAB Rows (Width) (1) Total LABs EPM240 1 6 4 — 24 EPM570 1 12 4 3 (3) 57 EPM1270 1 16 7 3 (5) 127 EPM2210 1 20 10 3 (7) 221 Devices Note to Table 2–1: (1) The width is the number of LAB columns in length. Figure 2–2 shows a floorplan of a MAX II device. Figure 2–2. MAX II Device Floorplan (Note 1) I/O Blocks I/O Blocks Logic Array Blocks Logic Array Blocks 2 GCLK Inputs 2 GCLK Inputs I/O Blocks UFM Block CFM Block Note to Figure 2–2: (1) The device shown is an EPM570 device. EPM1270 and EPM2210 devices have a similar floorplan with more LABs. For EPM240 devices, the CFM and UFM blocks are located on the left side of the device. October 2008 Altera Corporation MAX II Device Handbook

2–4 Chapter 2: MAX II Architecture Logic Array Blocks Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, a look-up table (LUT) chain, and register chain connection lines. There are 26 possible unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE outputs in the same LAB. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE’s LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE’s register to the adjacent LE’s register within an LAB. The Quartus II software places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–3 shows the MAX II LAB. Figure 2–3. MAX II LAB Structure Row Interconnect Column Interconnect LE0 Fast I/O connection to IOE (1) Fast I/O connection to IOE (1) LE1 DirectLink interconnect from adjacent LAB or IOE LE2 DirectLink interconnect from adjacent LAB or IOE LE3 LE4 LE5 LE6 DirectLink interconnect to adjacent LAB or IOE DirectLink interconnect to adjacent LAB or IOE LE7 LE8 LE9 Logic Element LAB Local Interconnect Note to Figure 2–3: (1) Only from LABs adjacent to IOEs. LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, from the left and right, can also drive an LAB’s local interconnect through the DirectLink connection. The DirectLink connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and DirectLink interconnects. Figure 2–4 shows the DirectLink connection. MAX II Device Handbook October 2008 Altera Corporation

Chapter 2: MAX II Architecture Logic Array Blocks 2–5 Figure 2–4. DirectLink Connection DirectLink interconnect from right LAB or IOE output DirectLink interconnect from left LAB or IOE output LE0 LE1 LE2 LE3 LE4 LE5 DirectLink interconnect to left LE6 DirectLink interconnect to right LE7 Local Interconnect LE8 LE9 Logic Element LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, a synchronous clear, an asynchronous preset/load, a synchronous load, and add/subtract control signals, providing a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal also uses labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable signal turns off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. By default, the Quartus II software uses a NOT gate push-back technique to achieve preset. If you disable the NOT gate push-back option or assign a given register to power-up high using the Quartus II software, the preset is then achieved using the asynchronous load signal with asynchronous load data input tied high. With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB column clocks [3.0], driven by the global clock network, and LAB local interconnect generate the LAB-wide control signals. The MultiTrack interconnect structure drives the LAB local interconnect for non-global control signal generation. The MultiTrack interconnect’s inherent low skew allows clock and control signal distribution in addition to data. Figure 2–5 shows the LAB control signal generation circuit. October 2008 Altera Corporation MAX II Device Handbook

2–6 Chapter 2: MAX II Architecture Logic Elements Figure 2–5. LAB-Wide Control Signals Dedicated LAB Column Clocks 4 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclkena2 labclkena1 Local Interconnect labclk1 labclk2 labclr2 syncload asyncload or labpre labclr1 addnsub synclr Logic Elements The smallest unit of logic in the MAX II architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry-select capability. A single LE also supports dynamic single-bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and DirectLink interconnects. See Figure 2–6. MAX II Device Handbook October 2008 Altera Corporation

Chapter 2: MAX II Architecture Logic Elements 2–7 Figure 2–6. MAX II LE Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear LAB Carry-In addnsub Carry-In1 Carry-In0 Programmable Register LUT chain routing to next LE data1 data2 data3 Look-Up Table (LUT) Carry Chain Synchronous Load and Clear Logic PRN/ALD D Q ADATA Row, column, and DirectLink routing data4 ENA CLRN labclr1 labclr2 labpre/aload Chip-Wide Reset (DEV CLRn) Asynchronous Clear/Preset/ Load Logic Row, column, and DirectLink routing Local routing Register Feedback Clock and Clock Enable Select Register chain output labclk1 labclk2 labclkena1 labclkena2 Carry-Out0 Carry-Out1 LAB Carry-Out Each LE’s programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any LE can drive the register’s clock and clear control signals. Either general-purpose I/O pins or LEs can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinational functions, the LUT output bypasses the register and drives directly to the LE outputs. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and DirectLink routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This register packing feature improves device utilization because the device can use the register and the LUT for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. October 2008 Altera Corporation MAX II Device Handbook

2–8 Chapter 2: MAX II Architecture Logic Elements LUT Chain and Register Chain In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. Refer to “MultiTrack Interconnect” on page 2–12 for more information about LUT chain and register chain connections. addnsub Signal The LE’s dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A B or A – B. The LUT computes addition; subtraction is computed by adding the two’s complement of the intended subtractor. The LAB-wide signal converts to two’s complement by inverting the B bits within the LAB and setting carry-in to 1, which adds one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions. LE Operating Modes The MAX II LE can operate in one of the following modes: “Normal Mode” “Dynamic Arithmetic Mode” Each mode uses LE resources differently. In each mode, eight available inputs to the LE, the four data inputs from the LAB local interconnect, carry-in0 and carryin1 from the previous LE, the LAB carry-in from the previous carry-chain LAB, and the register chain connection are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. MAX II Device Handbook October 2008 Altera Corporation

Chapter 2: MAX II Architecture Logic Elements 2–9 Normal Mode The normal mode is suitable for general logic applications and combinational functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 2–7). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinational output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 2–7. LE in Normal Mode sload sclear (LAB Wide) (LAB Wide) aload (LAB Wide) Register chain connection addnsub (LAB Wide) (1) data1 data2 data3 cin (from cout of previous LE) 4-Input LUT ALD/PRE ADATA Q D Row, column, and DirectLink routing ENA CLRN Row, column, and DirectLink routing clock (LAB Wide) ena (LAB Wide) data4 aclr (LAB Wide) Register Feedback Local routing LUT chain connection Register chain output Note to Figure 2–7: (1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain. Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry-select circuitry. As shown in Figure 2–8, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain’s logic level in turn determines which parallel sum is generated as a combinational or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 data2 carry in0 or data1 data2 carry-in1 October 2008 Altera Corporation MAX II Device Handbook

2–10 Chapter 2: MAX II Architecture Logic Elements The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals: one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry-select for the carry-out0 output and carry-in1 acts as the carryselect for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Figure 2–8. LE in Dynamic Arithmetic Mode LAB Carry-In sload sclear (LAB Wide) (LAB Wide) Register chain connection Carry-In0 Carry-In1 addnsub (LAB Wide) (1) data1 data2 data3 LUT LUT LUT aload (LAB Wide) ALD/PRE ADATA Q D Row, column, and direct link routing ENA CLRN Row, column, and direct link routing clock (LAB Wide) ena (LAB Wide) Local routing aclr (LAB Wide) LUT chain connection LUT Register chain output Register Feedback Carry-Out0 Carry-Out1 Note to Figure 2–8: (1) The addnsub signal is tied to the carry input for the first LE of a carry chain only. Carry-Select Chain The carry-select chain provides a very fast carry-select function between LEs in dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 0 and carry-in of 1 in parallel. The carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carryselect chains can begin in any LE within an LAB. MAX II Device Handbook October 2008 Altera Corporation

Chapter 2: MAX II Architecture Logic Elements 2–11 The speed advantage of the carry-select chain is in the parallel precomputation of carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delays between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the MAX II architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. Figure 2–9 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the nexthigher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. Figure 2–9. Carry-Select Chain LAB Carry-In 0 1 A1 B1 LE0 A2 B2 LE1 LAB Carry-In Sum1 Ca

MAX II devices are available in space-saving FineLine BGA, Micro FineLine BGA, and thin quad flat pack (TQFP) packages (refer to Table 1-3 and Table 1-4). MAX II devices support vertical migration within the same package (for example, you can migrate between the EPM570, EPM1270, and EPM2210 devices in the 256-pin FineLine BGA package).

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