B T3 14-15 Xilinx MIPI CSI-2 For Multi Camera - MIPI Alliance
Kondalarao Polisetti Senior Design Engineer , Xilinx MIPI CSI-2SM for Multi-camera, Long Range Use Cases and Implementation Methods Using FPGAs
Agenda MIPI CSI-2 Introduction & Features Camera Market & Projections Multi-camera & Long Distance Use Case(s) System Requirements Value of FPGA for MIPI CSI-2 Q&A Xilinx 2017 MIPI Alliance, Inc. 2
mipi.org MIPI Alliance: Developing the world’s most comprehensive set of interface specifications for mobile and mobile-influenced products. Source: mipi.org 2017 MIPI Alliance, Inc. Xilinx 3
MIPI CSI-2 Features Note: MIPI CSI-2SM 1.1, MIPI D-PHYSM 1.1 considered in this presentation. Multi-lane support (1.5Gbps/Lane) Multiple data types (RAW,RGB,YUV) Interleaving (VC , Data type) Xilinx 2017 MIPI Alliance, Inc. 4
MIPI CSI-2 Features Xilinx 2017 MIPI Alliance, Inc. 5
MIPI CSI-2 Features Xilinx 2017 MIPI Alliance, Inc. 6
Camera Projections Camera market by application Source: grandviewresearch.com 2017 MIPI Alliance, Inc. Xilinx 7
Automotive-ADAS Projections Source: IHS 2017 MIPI Alliance, Inc. Xilinx 8
Video Surveillance Projections Source: IHS 2017 MIPI Alliance, Inc. Xilinx 9
Multi-camera Systems CSI-2Rx Multiple channels, multiple instances CSI-2Rx Video Processing CSI-2Rx Visualization How many cam’s can be supported? System level aspects in such designs Single channel, single instance CSI-2Rx ü Bandwidth ü Protocol support ü Mux Chip support Video Processing Visualization Type-1 2017 MIPI Alliance, Inc. Visualization How many cam’s can be supported? System level aspects in such designs Mux Chip Mux Chip Video Processing Xilinx Mux Chip CSI-2Rx CSI-2Rx ü ü ü ü Bandwidth Protocol support Mux Chip support IO Support Video Processing Visualization Type-2 10
System aspects-Type1 How many cam’s can be supported? System level aspects in such designs Mux Chip CSI-2Rx Video Processing Visualization VC 0,RAW12 VC 0,RAW10 VC 0,RAW8 VC 1,RAW12 VC 1,RAW10 VC 1,RAW8 VC 2,RAW12 VC 2,RAW10 VC 2,RAW8 VC 3,RAW12 VC 3,RAW10 MIPI CSI-2 Mux Chip MIPI Single Channel VC 3,RAW8 üTotal bandwidth available üInterleaving as supported MIPI CSI-2 Specification üMaximum input channels supported by mux chip Xilinx 2017 MIPI Alliance, Inc. 11
System aspects-Type2 How many cam’s can be supported? System level aspects in such designs Mux Chip Mux Chip CSI-2Rx CSI-2Rx ü Protocol support ü Mux Chip support ü IO Support Video Processing Visualization VC 0,RAW12 VC 0,RAW10 VC 0,RAW8 VC 0,RAW12 VC 0,RAW10 VC 0,RAW8 VC 1,RAW12 VC 1,RAW10 VC 1,RAW8 VC 1,RAW12 VC 1,RAW10 VC 1,RAW8 VC 2,RAW12 VC 2,RAW10 VC 2,RAW8 VC 2,RAW12 VC 2,RAW10 VC 2,RAW8 VC 3,RAW12 VC 3,RAW10 VC 3,RAW8 VC 3,RAW12 VC 3,RAW10 VC 3,RAW8 MIPI CSI-2 Mux CSI-2 Chip MIPI Mux Chip MIPI CSI-2 Rx Instances üTotal bandwidth available üInterleaving as supported MIPI CSI-2 Specification üMaximum input channels supported by mux chip üMaximum CSI-2 Instances that can be implemented on the chip Xilinx 2017 MIPI Alliance, Inc. 12
System Requirements-Type1 1920x1080 @ 30fps, RAW8 - Requires 0.74Gbps 1.5Gbps, 4L 6 VC 4 DT 1(RAW8) Based on Chip Bandwidth Interleaving Mux Chip 6/0.74 8 4*1 4 Lets say ‘4’ min(8,4,4) 4 Xilinx 2017 MIPI Alliance, Inc. 13
System Requirements-Type2 1920x1080 @ 30fps, RAW8 - Requires 0.74Gbps 1.5Gbps, 4L 6 VC 4 DT 1(RAW8) Based on Chip Based on FPGA IO Bandwidth Interleaving Mux Chip IO Support 6/0.74 8 4*1 4 Lets say ‘4’ min(8,4,4) 4 CSI-2 Instances 8 Max Cam’s 4*8 32 AutoGrade US supports 8 Instances with Native IO’s Xilinx 2017 MIPI Alliance, Inc. 14
Multi-camera & Long Distance Use Case(s) Surround View Traffic Sign Park Assistance Lane Departure Source: mipi.org 2017 MIPI Alliance, Inc. Xilinx Surround View 15
Long Distance Using Bridge IC’s MIPI Interfaces may be converted to/from these high speed transports in bridge chips when length exceed MIPI Specification lengths Mux Chip Bridge CSI-2Rx IC Supported cable Bridge length,data rate Video IC etc., determined Processing by Bridge IC Visualization Converts MIPI D-PHYSM to LVDS Converts LVDS to MIPI D-PHYSM Xilinx 2017 MIPI Alliance, Inc. 16
Value of FPGA for MIPI CSI-2 Most flexible & scalable platform for maximum reuse and best TTM ü Implement End-to-End systems with ease Latest FPGAs can speak MIPI D-PHY ü Single Chip(PHY Controller), reduces BOM. More D-PHY interfaces per chip ( 16) ü Flexible interfaces: Lanes (1,2,3,4), Data rates, VC filtering etc. Latest FPGAs built on a common real-time processor and programmable logic equipped platform enables unlimited possibilities for next generation ADAS applications ü Innovative ARM FPGA architecture for differentiation, analytics & control Xilinx 2017 MIPI Alliance, Inc. 17
Q&A Xilinx 2017 MIPI Alliance, Inc. 18
VC 2,RAW8 VC 3,RAW8 MIPI CSI-2 Mux Chip MIPI Single Channel VC 0,RAW10 VC 1,RAW10 VC 2,RAW10 VC 3,RAW10 VC 0,RAW12 VC 1,RAW12 VC 2,RAW12 VC 3,RAW12 üTotal bandwidth available üInterleaving as supported MIPI CSI-2 Specification üMaximum input channels supported by mux chip CSI-2Rx Video Processing Visualization Mux Chip How many cam's can .
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