A DRAM Backend For The Impulse Memory System - University Of Utah

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A DRAM Backend for The Impulse Memory System Lixin Zhang U U C S -00-002 D ep artm en t o f C o m p u te r S c ie n c e U n iv e rsity o f U ta h S a lt L a k e C ity , U T 84112 , U S A D e c e m b e r 16 , 1998 Abstract T h e Im p u lse A d a p ta b le M e m o ry S y s te m e x p o se s D R A M a c c e ss patterns n ot seen in co n v en tio n al m em o ry sy stem s. F o r in stan ce, it can gen era te 32 D R A M a c c e ss e s e a c h o f w h ic h req u ests a fo u r-b y te w o rd in 32 c y c le s . C o n v en tio n a l D R A M b a c k en d s are o p tim ize d fo r a c c e ss e s that req u est fu ll c a c h e lin es. T h e y m a y n ot b e a b le to h a n d le sm a lle r a c c e ss e s e ffe ctiv e ly . In this d ocu m en t, w e d escrib e and ev alu a te a D R A M b a c k e n d that red u ces the a v era g e D R A M a cc e ss la te n cy b y e x p lo itin g the p o ten tial p a ra lle lism o f D R A M a c c e ss e s in the Im p u lse system . W e d e sig n the D R A M b a c k e n d b y stu d y in g e a c h o f its im portan t d e sig n option s: D R A M o rga n iza tio n , h o t r o w p o lic y , d y n a m ic re ord erin g o f D R A M a cc e s s e s, and in terle a v in g o f D R A M b an ks. T h e ex p erim en ta l resu lts o b tain ed fro m the e x ecu tio n -d riv en sim u lator P ain t [ 10 ] sh o w that, co m p a re d to a co n v en tio n al D R A M b ack en d , the p ro p o sed b a c k e n d can red u ce the a v era g e D R A M a c c e ss la te n c y b y u p to 9 8 % , the a v e ra g e m e m o ry c y c le s b y up to 9 0 % , and the ex ec u tio n tim e b y u p to 80 % . This effort was sponsored in part by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL) under agreement number F 30602-98- 1-0101 and DARPA Order Numbers F393/00-01 and F376/00. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official polices or endorsements, either express or implied, of DARPA, AFRL, or the US Government.

C o n te n ts 1 I n tr o d u c t io n 3 2 O v e r v ie w o f T h e I m p u ls e M e m o r y S y s te m 3 2.1 H a rd w a re O r g a n i z a t i o n . 4 2.2 R e m a p p in g A l g o r i t h m s . 6 3 4 5 D R A M B a s ic s 7 3.1 S y n c h ro n o u s D R A M . 7 3.2 D ire c t R a m b u s D R A M 8 . 10 D e s ig n 4.1 D R A M D isp a tc h er . 11 4.2 S la v e M e m o ry C o n t r o l l e r . 12 4.3 O th ers . 12 4 .3.1 H o t r o w p o l i c y . 12 4 .3.2 A c c e s s reo rd erin g . 13 4 .3.3 In terlea vin g . 14 15 E x p e r im e n t a l F r a m e w o r k 5.1 S im u la tio n E n v iro n m en t . 15 5.2 B e n c h m a rk s . 15 5.3 M e th o d o lo g y 16 . 1

6 7 17 P e rfo rm a n c e 6.1 T h e Im p acts o f D R A M O r g a n i z a t i o n . . 18 6.2 T h e Im p acts o f S la v e B u s s e s . . 20 6.3 T h e Im p acts o f H o t R o w P o lic y 6.4 T h e Im p acts o f A c c e s s R e o rd e rin g 6.5 T h e Im p acts o f I n t e r le a v in g . . 26 6.6 P u ttin g It A l l T o g e t h e r . 28 . 22 . . 24 30 C o n c lu s io n a n d F u t u r e W o r k 2

1 I n tr o d u c tio n T h e Im p u lse m e m o ry sy ste m adds tw o im p ortan t fea tu res to a trad itional m e m o ry system . F irst, it supports a p p lic a tio n -sp e c ific o p tim izatio n s th rou gh co n fig u ra b le p h y sic a l ad dress rem ap p in g. B y rem ap p in g p h y sic a l a d d resses at the m e m o ry co n tro ller, a p p licatio n s can co n tro l h o w th eir d ata is a c c e s s e d and c a c h e d , th ereb y im p ro v in g c a c h e p e rfo rm a n ce and bus u tilizatio n . S e c o n d , it can p refetch data fro m D R A M to an S R A M b u ffe r in the m e m o ry controller. F o r a c c e ss e s that h it in the S R A M b u ffer, Im p u lse e ffe c tiv e ly h id es D R A M a cc e ss la te n c y fro m the processor. A s a resu lt, Im p u lse ex h ib its D R A M a cc e ss patterns d ifferen t w ith w h a t a co n v en tio n al m e m o ry system d oes. F o r e x a m p le , it m a y gath er a 128 -b y te c a c h e lin e b y gen era tin g 32 fo u r-b y te D R A M a c c e ss e s d irected to 32 d ifferen t m e m o ry lo ca tio n s. S in c e co n v en tio n al D R A M b ack en d s are d esig n e d to h a n d le a c c e ss e s that fe tch c a c h e lin e s , th ey m a y not w o r k w e ll w ith sm a ller D R A M a cc e sse s. T o fu rth er im p ro v e the p e rfo rm a n ce o f the Im p u lse m e m o ry s y ste m , w e ex p lo re the p o ten tial o f red esig n in g the D R A M b a c k e n d fo r Im p u lse. T o h a n d le the la rg e n u m ber o f sm a ll D R A M a c c e ss e s in the Im p u lse m e m o ry sy ste m , a D R A M b a ck en d fo r Im p u lse m u st b e a b le to e x p lo it the in h eren t p a ra llelism o f th o se D R A M a cc e sse s. T h e d esig n op tion s that can sig n ifica n tly a ffe c t the e ffic ie n c y o f su ch a b a ck en d in c lu d e D R A M o rg a n iza tio n , h o t r o w p o lic y , a cc e ss sc h e d u lin g , and b an k in terle av in g . D R A M o rga n iza tio n d eterm in es h o w the D R A M b an k s are co n n ecte d togeth er, h o w the D R A M b a ck en d c o m m u n ica tes w ith the m e m o ry co n tro ller, and h o w the fu n ctio n a lity lik e a cc e ss sc h e d u lin g , b a n k in te rle a v in g , and D R A M re fre sh in g , is d istributed in sid e the D R A M b ack en d . H ot ro w p o lic y tries to red u ce the a v e ra g e D R A M a c c e s s la te n c y b y ju d ic io u s ly op en in g/clo sin g the h ot r o w s o f D R A M s . A c c e s s sch ed u lin g reord ers D R A M a c c e ss e s to e x p lo re p a rallelism . T h e in te rle a v in g o f m em o ry b an ks m a y a ffe c t the p e rfo rm a n ce d ra m a tica lly b e c a u se it d ire ctly d eterm in es the p o ten tial p a ra llelism that a seq u en ce o f D R A M a c c e ss e s m ig h t have. T h e rem ain d er o f this d o cu m en t is o rg a n ize d as fo llo w s . S e c tio n 2 p ro v id e s the o v e r v ie w o f the Im p u lse m e m o ry sy ste m , fo c u s in g on the m aster m e m o ry controller. S e c tio n 3 p ro v id e s so m e b a ck g ro u n d in fo r m ation a b o u t tw o c o m m o n ty p e s o f D R A M s : S y n c h ro n o u s D R A M and D ire c t R a m b u s D R A M . S e c tio n 4 d escrib es the p ro p o sed D R A M b ack en d . S ectio n 5 d escrib es the sim u lation en viron m en t and the b e n c h m ark s u se d in ou r exp erim en ts. S e c tio n 6 presents the p e rfo rm a n ce resu lts. S ectio n 7 d iscu sses future w o r k and c o n c lu d e s this d ocu m en t. 2 Overview of The Impulse Memory System T h e m o st d istin g u ish a b le featu re o f Im p u lse is the ad dition o f another le v e l o f ad d ress tran slation at the m e m o ry controller. T h e k e y in s ig h t e x p lo ite d b y this fea tu re is that “ u n u sed ” p h y s ic a l ad dresses can un d ergo a tran slation to “ r e a l” p h y sic a l ad d resses at the m e m o ry controller. F o r e x a m p le, in a co n v en tio n al system w ith 3 2 -b it p h y sic a l ad d ressin g and o n ly on e g ig a b y te s o f in sta lle d D R A M , the oth er three g ig a b y te s o f p h y sic a l ad dress sp ace are n ot d ire c tly b a c k e d up b y D R A M and w ill gen erate errors i f presen ted to a 3

co n v en tio n al m e m o ry controller. W e c a ll th ese o th erw ise-u n u sed p h y sic a l ad dresses shadow a d d resses, and th e y con stitu te a shadow a d d ress sp a ce. In an Im p u lse sy stem , a p p licatio n s can reo rg a n ize their data structures in the sh a d o w ad dress sp ace to e x p lic itly co n tro l h o w their d ata is a c c e ss e d and cach ed . W h e n the Im p u lse m e m o ry c o n tro ller re c e iv e s a sh a d o w ad dress, it w ill translate the sh a d o w ad dress to a set o f “ r e a l” p h y sic a l ad dresses (a .k .a p h y sic a l D R A M ad dresses) in stead o f gen era tin g an error as a co n ven tio n al m e m o ry c o n tro ller d oes. In the cu rren t Im p u lse d esig n , the m a p p in g fro m the sh a d o w ad dress sp ace to the rea l p h y s ic a l ad dress sp ace can b e in a n y p o w e r-o f-tw o g ra n u la rity fro m w o rd -s iz e to p a g e size. D a ta item s w h o se virtu a l ad dresses are not co n tig u o u s can b e m ap p ed to co n tig u o u s sh a d o w ad dresses, so that sparse d ata item s in virtu a l m e m o ry can b e co m p a c te d into d en se c a c h e lin e s in sh a d o w m em o ry b e fo re b e in g tran sferred to the processo r. T o m ap data item s in th ese co m p a c te d c a c h e lin e s b a c k to p h y sic a l m em ory, Im p u lse m u st re c o v e r their o ffse ts w ith in the virtu a l la y o u t o f the o rig in a l d ata structures. W e c a ll these o ffse ts p se u d o -v irtu a l ad d resses. P seu d o -v irtu a l m e m o ry m irrors real virtu a l m e m o ry and is n ecessa ry to m ap d ata structures larger than a p a g e. T h e m e m o ry co n tro ller translates p se u d o -v irtu a l a d d resses to p h y sic a l D R A M a d d resses in p a g e -le v e l. T h e sha dow p s e u d o -v ir tu a l — p h y s ic a l m a p p in gs a ll take p la c e w ith in the Im p u lse m e m o ry controller. T h e shadow — p s e u d o -v ir tu a l m a p p in g in v o lv e s so m e sim p le arith m etic op eratio n s and is im p lem e n te d b y A L U units. T h e p s e u d o -v ir tu a l p h y s ic a l m a p p in g in v o lv e s p a g e tab le lo o k u p s and is im p lem e n te d b y a sm a ll ta b le lo o k a sid e b u ffer ( T L B ) at the m e m o ry controller. T h e seco n d im portan t featu re o f Im p u lse is that it supports p refe tc h in g — M e m o ry -C o n tro lle r-b a se d p re fe tc h in g (M C -b a s e d p refe tch in g ). A sm a ll am ou n t o f S R A M - so -c a lle d M e m o ry C o n tro lle r c a c h e or M C a c h e - in tegrated at the m e m o ry c o n tro ller stores d ata p refe tch ed fro m D R A M . F o r this d ocu m en t, w e a s sum e a sim p le n ex t-lin e seq u en tial p refe tc h sch em e fo r M C -b a s e d p refetch in g : w h e n an a c c e ss m isses in the M C a c h e , fe tc h the req u ested c a c h e lin e and p re fe tc h the n ex t on e; w h en an a cc e ss hits in the M C a c h e , p refe tc h the n e x t one. F o r n orm al data, p refe tc h in g is u se fu l fo r red u cin g the m e m o ry la te n cy o f se q u e n tia lly -a c c e sse d data. F o r sh a d o w data, p refe tc h in g en a b les the co n tro ller to h id e the c o st o f rem a p p in g sh a d o w ad d resses and issu in g m u ltip le D R A M a ccess es. T h e sh a d o w ad dress sp ace is m a n a g e d b y the op eratin g sy ste m in a w a y sim ila r to real p h y sic a l address sp ace. T h e o p eratin g sy ste m gu aran tees the sh a d o w ad dress sp ace im a g e o f a n y rem ap p ed sh a d o w reg io n to b e co n tig u o u s e v en it spans m u ltip le p a g es. T h is gu aran tee n ot o n ly sim p lifies the tran slation h ard w are at the m e m o ry co n troller, b u t a ls o a llo w s the C P U to u se su p erp a ge T L B en tries to tran slate rem ap p ed data. T h e o p eratin g sy ste m p ro v id e s an in terfa ce fo r a p p licatio n s to s p e c ify o p tim izatio n s fo r their p articu lar data structures and c o n fig u re the Im p u lse m e m o ry c o n tro ller to reinterp ret the sh a d o w ad dresses p resen ted to it. T h e p ro g ra m m er (or the co m p iler, in the fu ture) inserts d ire ctiv es into the a p p licatio n s to c o n fig u re the Im p u lse m e m o ry controller. T o k eep the m e m o ry co n tro ller sim p le and fast, Im p u lse restricts rem ap p in g in tw o w a y s . F irst, a n y d ata item b e in g rem ap p ed m u st b e a p o w e r o f tw o in size. S eco n d , an a p p licatio n that u se s rem ap p in g m u st en su re d ata c o n s is te n cy th rou gh approp riate flu sh in g o f the cach es. 2.1 Hardware Organization F ig u re 1 sh o w s the b lo c k d iag ra m o f the Im p u lse m e m o ry sy stem , w h ic h in c lu d e s the fo llo w in g com p o n en ts: 4

Impulse memory controller I y) .Q CPU O E CD E L1 SDescs Registers Buffer me a PQ J H AddrCalc MMU b ; l ’' L2 H-----DRAM H-----DRAM -T DRAM backend F ig u re 1 : T he Im pulse m em ory architecture. T he arrows indicate how data flows within an Impulse m em ory system. a sm a ll n u m ber o f c o n tro l registers, w h ic h are sp lit in to a set o f S hadow D esc r ip to r s (S D e sc s) and store co n fig u ra tio n in fo rm a tio n fo r rem ap p ed sh a d o w regio n s, a sim p le A L U unit (A d d r C a lc ), w h ic h tran slates sh a d o w a d d resses to p seu d o -virtu a l ad dresses; a M em ory C o n tro lle r T L B (M T L B ), w h ic h is b a c k e d u p b y m ain m e m o ry and m aps p seu d o -virtu a l ad d resses to p h y sic a l D R A M a d d resses, a lo n g w ith a sm a ll D R A M b u ffe r to h o ld p refe tch ed p a g e tab le entries; a M em ory C o n tro ller C a c h e (M C a c h e ), w h ic h h o ld s d ata p refe tch ed fro m D R A M ; a D R A M S ch e d u ler, w h ic h con tain s circ u itry that ord ers and issu es D R A M a ccesses; D R A M ch ip s, w h ic h con stitu te m ain m em o ry . T h e ex tra le v e l o f a d d ress tran slation a t the m e m o ry co n tro ller is o p tio n al, so an a d d ress a p p e arin g on the sy ste m m e m o ry bus m a y b e a rea l p h y sic a l o r a sh a d o w a d d ress ( a ) . A rea l p h y sic a l ad dress passes un tran slated to the M C a c h e / D R A M sch ed u ler ( b ) . A sh a d o w a d d ress has to g o throu gh the m a tch in g sh a d o w d escrip to r ( d ) . T h e A d d r C a lc u n it tran slates the sh a d o w a d d ress into a set o f p seu d o -virtu a l ad d resses u sin g 5

the rem ap p in g in fo rm a tio n stored in the m a tch in g sh a d o w d escrip tor (e). T h e s e p seu d o -virtu a l ad dresses are tran slated into real p h y sic a l ad dresses b y the M T L B (f). T h e rea l p h y s ic a l ad d resses pass to the D R A M sch ed u ler (g). T h e D R A M sch ed u ler orders and issu e s the D R A M a c c e ss e s (h ) and sends d ata b a c k to the m e m o ry c o n tro ller (i). F in a lly , w h en a fu ll c a c h e lin e h as b een gath ered , the M M C sends it to the sy ste m m e m o ry bus (j). 2.2 Rem apping Algorithm s C u rren tly, the ad dress tran slation at the Im p u lse m e m o ry c o n tro ller can take fo u r fo rm s, d ep en d in g on h o w the M M C is u se d to a c c e s s a particu la r d ata structure: d irect rem apping, strid ed rem apping, transp ose rem apping, or rem apping through an in d irectio n vector. D ir e c t m apping m aps o n e co n tig u o u s c a c h e lin e in sh a d o w m e m o ry to o n e c o n tig u o u s c a c h e lin e in rea l p h y sic a l m em ory. T h e p seu d o -virtu a l ad d ress fo r the sh a d o w ad dress sa d d r is (sa d d r — ssaddr), w h ere ssa d d r is the starting ad dress (a ssign ed b y the O S ) o f the d ata stru ctu re’s shadow address sp a ce im age. E x a m p le s o f u sin g this m a p p in g in c lu d e r e c o lo rin g p h y sic a l p a g e s w ith o u t c o p y in g [2 ] and co n stru ctin g su p erp ages fro m n o n -co n tigu o u s p h y s ic a l p a g e s w ith o u t c o p y in g [ 1 1 ] . S trid ed m apping creates d en se c a c h e lin e s fro m d ata item s that are n ot co n tig u o u s bu t strid ed ly d is tributed in virtu al m em ory. T h e M M C m aps a c a c h e lin e a d d ressed b y the sh a d o w ad dress sa d d r to m u ltip le p seu d o -virtu a l ad dresses: (strid e x (sa d d r — ssaddr) / size jo f-d a ta J tem stride x i), w h ere i ran ges fro m 0 to (c a c h e -lin e s i z e / size -o f-d a ta J te m — 1). T h is m a p p in g can b e u sed to create tiles o f a d en se m a trix w ith o u t c o p y in g o r to c o m p a c t strided a rray elem en ts [2]. T ran spose m apping creates the tran spose o f a tw o -d im en sio n a l m a trix b y m a p p in g the elem e n t [j] [i] o f the tran spo sed m a trix to the elem e n t o f the o rig in a l m atrix. T h is m a p p in g can b e u se d w h erev er a m a trix is a cc e s s e d in a m a jo r d ifferen t w ith w h a t it is stored [ 14 ]. R em a p p in g through an in d irectio n v e cto r p a c k s d en se c a c h e lin e s fro m a rray elem en ts a cc o rd in g to an in d irectio n vector. T o rem ap the sh a d o w ad dress saddr, the M M C first co m p u tes its o ffs e t in sh a d o w m e m o ry as so ffset (sa d d r — ssaddr) / size -of-array -elem ent, then u se s the in d irectio n v e cto r ve cto r to m ap the c a c h e lin e ad d ressed b y the sh a d o w ad dress sa d d r to several p seu d o -virtu a l ad dresses ( v e c t o r [ s o f f s e t « ]), w h ere i ran ges fro m 0 to (c a c h e -lin e s i z e / size .o f-a rra y -elem en t — 1 ). T h e O S m o v e s the in d irectio n v e cto r in to co n tig u o u s p h y sic a l m e m o ry so that the ad dress tran slation fo r the in d irectio n v e cto r is n ot n eed ed . O n e e x a m p le o f u sin g this m a p p in g is to u se it to o p tim ize the sparse m a trix -v e cto r p ro d u ct a lg o rith m [2]. In d ire ct m a p p in g, e a c h sh a d o w ad dress gen era tes e x a c tly on e D R A M a cc e ss. In oth er three m ap p in gs, e a c h sh a d o w ad dress gen erates (c a c h e -lin e s i z e / siz e jo f-d a ta J tem ) D R A M a c c e ss e s i f (c a c h e J in e s i z e size -o f-d a ta J te m ), or on e D R A M a c c e s s i f (c a c h e -lin e s i z e size -o f-d a ta Jtem ). 6

3 DRAM Basics T h is sectio n d escrib es the b a sic s o f D R A M (D y n a m ic R a n d o m A c c e s s M e m o ry ) and tw o co m m o n ty p e s o f D R A M s : S y n ch ro n o u s D R A M and D ire c t R a m b u s D R A M . D R A M is arran ged as a m a trix o f “ m e m o ry c e lls ” la id ou t in r o w s and co lu m n s, and thus a d ata a cc e ss seq u en ce co n sists o f a row a c c e s s strobe sig n a l ( R A S ) fo llo w e d b y on e or m o re co lu m n a c c e s s strobe sig n als ( C A S ) . D u rin g R A S , d ata in the sto ra ge c e lls o f the d ec o d ed ro w is m o v e d in to a b an k o f sen se a m p lifier ( a .k .a p a g e bu ffer or h o t row), w h ic h serves as a ro w cach e. D u rin g C A S , the co lu m n a d d resses are d eco d ed and the sele cted d ata is read fro m the p a g e buffer. C o n se c u tiv e a c c e ss e s to the cu rren t p a g e b u ffe r - c a lle d p a g e hits - o n ly n eed co lu m n a d d resses, sa v in g the R A S sig n a ls. H o w eve r, the h o t ro w m u st first b e c lo se d b e fo re another ro w can b e op en ed . In ad dition , D R A M has to b e refresh ed a b o u t hun dreds o f tim es ea c h seco n d in ord er to retain d ata in its m e m o ry c e lls. 3.1 Synchronous DRAM S D R A M sy n ch ro n ize s a ll inp u t and ou tpu t sig n a ls to a sy ste m c lo c k , th e re fo re m a k in g the m e m o ry retrieval p ro cess m u c h m o re efficien t. In S D R A M , R A S and C A S sig n a ls share the sam e bus. S D R A M supports burst tran sfer to p ro v id e a co n stan t flo w o f data. T h e p ro g ra m m a b le b u rst le n g th can b e tw o , four, e ig h t c y c le s o r a fu ll-p a g e . It has b o th “ a u to m a tic” and “ c o n tro lle d ” p rech a rg e co m m an d s, w h ic h a llo w a read or a w rite co m m an d to s p e c ify w h eth er or n ot to le a v e the ro w open. F ig u re 2 sh o w s the seq u en ces o f so m e S D R A M tran sactions, assu m in g a ll tran sactions a cc e ss the sam e b an k. P a r t 1 o f F ig u re 2 d isp la y s the in terle a v in g o f tw o read tran sactions d irected to the sam e ro w w ith o u t a u to m a tic p rech a rg e com m an d s. T h e seco n d read hits the h o t row , so it d o es n ot n eed a R A S sign al. P a r t 2 o f F ig u r e 2 sh o w s the in terle a v in g o f tw o read tran sactions d irected to tw o d ifferen t r o w s w ith o u t autom atic p rech a rg e co m m an d s. S in c e the seco n d read n eed s a d ifferen t row , the p rev io u s h o t r o w has to b e c lo se d (i.e., a p rech a rg e co m m an d m u st b e d on e) b e fo re the seco n d read can o p en a n ew row . P a r t 3 o f F ig u re 2 sh o w s tw o read tran sactions w ith au to m a tic p rech a rg e co m m an d s (i.e., the ro w is a u to m a tica lly c lo se d at the en d o f an a cc e ss). W h e n the a u tom atic p rech a rg e is en a b led , the seq u en ce o f tw o read tran saction s w ill b e sam e n o m atter w h eth er th ey a cc e ss the sam e r o w o r not. P a r t 4 o f F ig u re 2 d isp la y s a w rite tran saction fo llo w e d b y a read tran saction w h ic h a c c e ss e s a n e w row . A n e x p lic it p rech a rg e co m m a n d m u st b e in serted b e fo re the seco n d tran saction starts. T h e w rite tran saction in trod u ces tw o restrictio n s. F irst, a d e la y ( t D P L ) m u st b e satisfied fro m the start o f the last w rite c y c le to the start o f the p rech a rg e com m an d . S e c o n d , the d e la y b e tw e e n the p rech a rg e co m m a n d and the n ex t activate co m m an d ( R A S ) m u st b e greater than or eq u al to the p rech a rg e tim e ( t R P ) . F ig u r e 2 a ls o sh o w s the k e y tim in g param eters o f S D R A M [7 ]. T h e ir m ean in gs and ty p ic a l v a lu es in S D R A M c lo c k c y c le s are p resen ted in T a b le 1 , w h ic h assu m es a 147 M H z c lo c k rate. 7

tRCD -tCCD- RAS A CAS A tAA - CAS B DOUTA DOUTA DOUTB DOUT B Part1: Tworeadstothesamerow,withoutautomaticprecharge Part2: ge Beginautoprecharge Beginautoprecharge Part3: Tworeadtransactions,withautomaticprecharge Part4: A icprecharge F ig u re 2 : E x a m p le s o f S D R A M tran sactions M e a n in g Sym bol V a lu e tR A S m in im u m b a n k a ctiv e tim e 7 tR C D R A S to C A S d e la y tim e 3 tA A C A S la te n cy 3 tC C D C A S to C A S d e la y tim e 1 tR P p rech a rg e tim e 3 tD P L data in to p rech a rg e tim e 2 tD A L data in to a ctive/refresh tim e (eq u a ls to t R P t D P L ) 5 T a b le 1 : Im p ortan t tim in g param eters o f S y n c h ro n o u s D R A M . 3.2 D irect Ram bus DRAM D ire c t R a m b u s D R A M is a h ig h sp eed D R A M d e v e lo p e d b y R a m b u s, In c [3 ]. R D R A M h as in d ep en d en t pin s fo r r o w ad d ress, co lu m n ad d ress, and d ata. E a c h b a n k can b e in d e p en d en tly o p en ed , a cc e ss e d , and 8

p rech arged . D a ta and co n tro l in fo rm a tio n are tran sferred to and fro m R D R A M in a p a ck e t-o rie n ted p ro to co l. E a c h o f the p a ck e ts co n sists o f a b u rst o f e ig h t b its o v er the co rresp o n d in g sig n al lin e s o f the chan nel. tRC ROW PRER ACTa ACTb tRAS COL tRP R D a 1 R D a2 DQ — fOFFP - Q ( a 1) Q (a 2 ) tCAC Part ROW 1: A read transaction with precharge followed by another read. ACT a COL R D a 1 R D a2 R D b 1 R D b 2 DQ ROW )2 P art Q (a 2 ) Q ( b 1) ( Q Q ( a 1) 2 : Two read transactions to the same row. PRER ACTa ACTb -----tRP ------- COL R D a 1 R D a2 DQ Q ( a 1) Part ROW Q (a 2 ) 3 : A read transaction without precharge followed by an explicit precharge command ACT a COL ACT b ACT c ACT d ACT e ACT f R D a 1 R D a2 R D b 1 R D b 2 R D c 1 R D c 2 R D d 1 R D d2 R D e 1 DQ 2 ) ( Q Part Q (a 2 ) ( Q Q ( a 1) Q (c 1) Q(c 2 ) 4 : Ideal interleaving o f transactions directed to non-adjacent banks F ig u re 3 : E x a m p le s o f R D R A M op eratio n s F ig u re 3 sh o w s so m e R D R A M tran saction s that a ll a cc e ss the sam e ch ip. P a r t 1 o f F ig u re 3 sh o w s a read tran saction w ith a p rech a rg e co m m an d , fo llo w e d b y another tran sactio n to the sam e b an k. P art 2 o f F ig u re 3 sh o w s the o v erla p p in g o f tw o read tran saction s d irected to the sam e row . P a r t 3 o f F ig u re 3 sh o w s a read tran sactio n w ith o u t a p rech a rg e c o m m an d fo llo w e d b y a tran saction to a d ifferen t row . In this c ase , the h o t r o w m u st b e e x p lic itly p rech a rg ed b e fo re the seco n d tran sactio n starts. P a r t 4 o f F ig u r e 3 d isp la y s an id e a l stead y-state seq u en ce o f d u al-d ata read tran saction s d irected to n on -a d ja cen t b an ks o f a sin g le R D R A M ch ip . T h e k e y tim in g param eters o f R D R A M and their ty p ic a l v a lu es in c lo c k c y c le s are p resen ted in T a b le 2 , w h ic h assu m es a 40 0 M H z c lo c k rate [6]. 9

M e a n in g V a lu e m e the m in im u m d e la y fro m the first A C T c o m m an d to the seco n d A C T c o m m an d 28 tR A S the m in im u m d e la y fro m an A C T co m m a n d to a P R E R co m m an d 20 tn c D d e la y fro m an A C T co m m a n d to its first R D co m m an d 7 tR P the m in im u m d e la y fro m a P R E R co m m an d to an A C T co m m an d tC A C d e la y fro m a R D co m m an d to its a sso cia ted d ata ou t 8 8 tc c d e la y fro m a R D co m m an d to n ex t R D co m m an d 4 Sym bol tO F F P the m in im u m d e la y fro m the la s t R D co m m an d to a P R E R co m m an d 3 tB U B l b u b b le b e tw e e n a R D and W R co m m an d 4 tn u m b u b b le b e tw e e n a W R and R D c o m m an d to the sam e d e v ic e 8 T a b le 2 : Im portan t tim in g param eters o f R a m b u s D R A M . 4 Design T h e p ro p o sed Im p u lse D R A M b a c k e n d 1 con tain s three m a jo r com p o n en ts: the D R A M D isp atch er, S la v e M e m o ry C o n tro lle rs ( S M C s ) , and p lu g -in m e m o ry m o d u les — D R A M ch ip s. T h e D R A M dispatcher, S M C s , and R A M A d d re ss b u sses ( R A b u sses) c o n n ec tin g them con stitu te the D R A M sch ed u ler sh o w n in F ig u re 1 . A D R A M b a c k e n d con tain s on e D R A M d ispatcher, bu t can h a v e m u ltip le S M C s , m u ltip le R A b u sses, and m u ltip le p lu g -in m e m o ry m od u les. F ig u re 4 sh o w s a co n fig u ra tio n that h as fo u r S M C s , fo u r D R A M ch ip s, e ig h t b an ks, and tw o R A b u sses. N o te that the D R A M d isp a tch er and S M C s do n ot h a v e to b e in d ifferen t ch ip s. F ig u r e 4 ju s t sh o w s them in a w a y e a s y to understand. W h e th er o r n ot to im p lem e n t the D R A M sch ed u ler in a sin g le ch ip is an o p en q uestion . T h e M a ste r M e m o ry C o n tro lle r [ 13 ] ( M M C ) is the c o re o f the Im p u lse m e m o ry system . It co m m u n ica tes w ith the p ro cesso rs and I/O adapters o v e r the sy ste m m e m o ry bus, tran slates sh a d o w a d d resses in to p h y sic a l D R A M ad d resses, and gen erates D R A M a cc e sse s. A D R A M a cc e ss can b e a sh a d o w a c c e ss o r a norm al a cc e ss. T h e M M C sends a D R A M req u e st to the b a c k e n d v ia S la v e A d d re ss b u sses ( S A b u sses) and passes d ata fro m o r to the D R A M b a c k e n d v ia S la v e D a ta b u sses (S D b u sses). D u rin g ou r ex p erim en ts, w e v a ry the n u m ber o f S A b u sses/S D b u sses fro m on e to o n e p lu s the n u m ber o f sh a d o w d escrip tors. I f there is o n ly o n e S A o r S D bus, n orm al a c c e ss

The Impulse Adaptable Memory System exposes DRAM access patterns not seen in conventional memory systems. For instance, it can generate 32 DRAM accesses each of which requests a four-byte word in 32 cycles. Conventional DRAM backends are optimized for accesses that request full cache lines. They may

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