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IEEE Std 1364-2001IEEE Standards(Revision ofIEEE Std 1364-1995) IEEE Standard Verilog HardwareDescription LanguageIEEE Computer SocietySponsored by theDesign Automation Standards CommitteePublished byThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USA28 September 2001Print: SH94921PDF: SS94921

IEEE Std 1364-2001(Revision ofIEEE Std 1364-1995)IEEE Standard Verilog HardwareDescription LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyApproved 17 March 2001IEEE-SA Standards BoardAbstract: The Verilog Hardware Description Language (HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification,synthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the language.Keywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, VerilogHDL, Verilog PLI, Verilog The Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2001 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 28 September 2001. Printed in the United States of America.Print:PDF:ISBN 0-7381-2826-0ISBN 0-7381-2827-9SH94921SS94921No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.

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Introduction(This introduction is not part of IEEE Std 1364-2001, IEEE Standard Verilog Hardware Description Language.)The Verilog Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timing analysis, testanalysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the languageof choice by an overwhelming number of IC designers.Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. A design consists of a set of modules, each of which has an I/O interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets.The Verilog language is extensible via the Programming Language Interface (PLI) and the Verilog Procedural Interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to accessinformation contained in a Verilog HDL description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand CAD systems, customized debugging tasks, delay calculators, and annotators.The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of Defense.HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generation.In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent OpenVerilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE WorkingGroup was formed and after 18 months of focused efforts Verilog became an IEEE standard as IEEE Std1364-1995.After the standardization process was complete the 1364 Working Group started looking for feedback from1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five yeareffort to get a much better Verilog standard in IEEE Std 1364-2001.Objective of the IEEE Std 1364-2001 effortThe starting point for the IEEE 1364 Working Group for this standard was the feedback received from theIEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in allaspects of the language. Users at the higher levels wanted to expand and improve the language at the RTLand behavioral levels, while users at the lower levels wanted improved capability for ASIC designs andsignoff. It was for this reason that the 1364 Working Group was organized into three task forces: Behavioral,ASIC, and PLI.Copyright 2001 IEEE. All rights reserved.iii

The clear directive from the users for these three task forces was to start by solving some of the followingproblems:Consolidate existing IEEE Std 1364-1995Verilog Generate statementMulti-dimensional arraysEnhanced Verilog file I/ORe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the VPI routinesAchievementsOver a period of four years the 1364 Verilog Standards Group (VSG) has produced five drafts of the LRM.The three task forces went through the IEEE Std 1364-1995 LRM very thoroughly and in the process of consolidating the existing LRM have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the VSG has also been able to agree on all the enhancements that were requested (including the ones stated above).Three new sections have been added. Clause 13, Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of Verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session. Clause 15,Timing checks, has been broken out of Clause 17, System tasks and functions, and details more fullyhow timing checks are used in specify blocks. Clause 16, Backannotation using the Standard Delay Format(SDF), addresses using back annotation (IEEE Std 1497-1999) within IEEE Std 1364-2001.Extreme care has been taken to enhance the VPI routines to handle all the enhancements in the Behavioraland other areas of the LRM. Minimum work has been done on the PLI routines and most of the work hasbeen concentrated on the VPI routines. Some of the enhancements in the VPI are the save and restart, simulation control, work area access, error handling, assign/deassign and support for array of instances, generate,and file I/O.Work on this standard would not have been possible without funding from the CAS society of the IEEE andOpen Verilog International.The IEEE Std 1364-2001 Verilog Standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the IEEE Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL).The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented. The three task forces focused on their specific areas and theirrecommendations were eventually voted on by the IEEE Std 1364-2001 working group.ivCopyright 2001 IEEE. All rights reserved.

At the time this document was approved, the IEEE Std 1364-2001 working group had the followingmembership:Maqsoodul (Maq) Mannan, ChairKasumi Hamaguchi, Vice Chair (Japan)Alec G. Stanculescu, Vice Chair (USA)Lynn A. Horobin, SecretaryYatin Trivedi, Technical EditorThe Behavioral Task Force consisted of the following members:Clifford E. Cummings, LeaderKurt BatyStefen BoydShalom BrestickerTom FitzpatrickAdam KrolnikJames A. MarkevitchMichael McNamaraAnders NordstromKaren PieperSteven SharpChris SpearStuart SutherlandThe ASIC Task Force consisted of the following members:Steve Wadsworth, LeaderLeigh BradyPaul ColwillTom DeweyTed ElkindNaveen GuptaPrabhakaran KrishnamurthyMarek RyniejskiLukasz SenatorThe PLI Task Force consisted of the following members:Andrew T. Lynch, LeaderStuart Sutherland, Co-Leader and EditorDeborah J. DalioCharles DawsonSteve MeyerGirish S. RaoDavid RobertsThe IEEE 1364 Japan subgroup (EIAJ/1364HDL) consisted of the following members:Kasumi Hamaguchi, Vice Chair (Japan)Yokozeki AtsushiYasuaki HattaCopyright 2001 IEEE. All rights reserved.Makoto MakinoTakashima MitsuyaTatsuro NakamuraHiroaki NishiTsutomu Someyav

The following members of the balloting committee voted on this standard:Guy AdamShigehiro AsanoPeter J. AshendenVictor BermanJ BhaskerStefan BoydDennis B. BrophyKeith ChowClifford E. CummingsBrian A. DalioTimothy R. DavisCharles DawsonDouglas D. DunlopTed ElkindJoerg-Oliver Fischer-BinderPeter FlakeRobert A. FlattMasahiro FukuiKenji GotoNaveen GuptaAndrew GuylerYoshiaki HagiwaraAnne C. HarrisLynn A. HorobinChiLai HuangTakahiro IchinomiyaMasato IkedaMitsuaki IshikawaNeil G. JacobsonRichard O. JonesOsamu KaratsuJake KarrfaltMasayuki KatakuraKaoru KawamuraMasamichi KawarabayashiSatoshi KojimaMasuyoshi KurokawaGunther LehmannAndrew T. LynchSerge MaginotMaqsoodul MannanJames A. MarkevitchFrancoise MartinolleYoshio MasubuchiPaul J. MenchiniHiroshi MizunoEgbert MolenkampJohn T. MontagueAkira MotoharaHiroaki NishiAnders NordstromRyosuke OkudaYoichi OnishiUma P. ParvathyWilliam R. PaulsenKaren L. PieperGirish S. RaoJaideep RoyFrancesco SforzaCharles F. ShelorChris SpearAlec G. StanculescuSteve StartStuart SutherlandMasahiko ToyonagaYatin K. TrivediCary UsserySteven D. WadsworthSui-Ki WanRonald WaxmanJohn M. WilliamsJohn WillisTakashi YamadaLun YeHirokazu YonezawaTetsuo YutaniMark ZwolinskiWhen the IEEE-SA Standards Board approved this standard on 17 March 2001, it had the followingmembership:Donald N. Heirman, ChairJames T. Carlo, Vice ChairJudith Gorman, SecretarySatish K. AggarwalMark D. BowmanGary R. EngmannHarold E. EpsteinH. Landis FloydJay Forster*Howard M. FrazierRuben D. GarzonJames W. MooreRobert F. MunznerRonald C. PetersenGerald H. PetersonJohn B. PoseyGary S. RobinsonAkio TojoDonald W. ZipseJames H. GurneyRichard J. HollemanLowell G. JohnsonRobert J. KennellyJoseph L. Koepfinger*Peter H. LipsL. Bruce McClungDaleep C. Mohla*Member EmeritusAlso included is the following nonvoting IEEE-SA Standards Board liaison:Alan Cookson, NIST RepresentativeDonald R. Volzka, TAB RepresentativeAndrew D. IckowiczIEEE Standards Project EditorVerilog is a registered trademark of Cadence Design Systems, Inc.viCopyright 2001 IEEE. All rights reserved.

Contents1.Overview. 11.11.21.31.41.51.61.72.Lexical conventions . 62.12.22.32.42.52.62.72.83.Objectives of this standard. 1Conventions used in this standard. 1Syntactic description. 2Contents of this standard. 2Header file listings . 4Examples. 5Prerequisites. 5Lexical tokens . 6White space. 6Comments . 6Operators. 6Numbers. 6Strings . 10Identifiers, keywords, and system names . 12Attributes. 14Data types. 203.1 Value set. 203.2 Nets and variables . 203.3 Vectors . 233.4 Strengths . 243.5 Implicit declarations. 253.6 Net initialization. 253.7 Net types .

effort to get a much better Verilog standard in IEEE Std 1364-2001. Objective of the IEEE Std 1364-2001 effort The starting point for the IEEE 1364 Working Group for this standard was the feedback received from the IEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all aspects of the language.File Size: 2MBPage Count: 791Explore furtherIEEE Standard for Verilog Hardware Description Languagestaff.ustc.edu.cn/ songch/download/I IEEE Std 1800 -2012 (Revision of IEEE Std 1800-2009 .www.ece.uah.edu/ gaede/cpe526/20 IEEE Standard for SystemVerilog— Unified Hardware Design .www.fis.agh.edu.pl/ skoczen/hdl/iee Recommended to you b

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