DESIGN OF PULSE TRIGGERED FLIP-FLOP USING DYNAMIC .

ISSN 2278-3091International Journal of Advanced Trends in Computer Science and Engineering, Vol.2 , No.2, Pages : 171-176 (2013)Special Issue of NCRTECE 2013 - Held during 8-9 February, 2013 in SMK Fomra Institute of Technology, OMR, Thaiyur, Kelambakkam, ChennaiDESIGN OF PULSE TRIGGERED FLIP-FLOP USINGDYNAMIC CONTROLLING CIRCUITM.Suresh,D.Dolphin Kiruba,Asst.Professor,SMK Fomra Institute of Tech.,Chennai.nm suresh85@yahoo.inPG/VLSI DESIGN,SMK Fomra Institute of Tech.,Chennai.dolphinkiruba@gmail.comwidth, the latch acts like an edge-triggeredFF. The circuit complexity of a P-FF issimplified since only one latch, as opposedto two used in conventional master–slaveconfiguration, is needed. P-FFs also allowtime borrowing across clock cycleboundaries and feature a zero or evennegative time. P-FFs are thus less sensitiveto clock jitter. Despite these advantages,pulse generation circuitry requires delicatepulse width control in the face of processvariation and the configuration of pulseclock distribution network [4].ABSTRACTThe choice of flip-flop topologies is an essentialimportance in design of VLSI integratedcircuits for high speed and high performanceCMOS circuits. In this paper, a novel pulsetriggered flip-flop design is presented whichhas small delay and low power consumption.Two transistor AND gate is eliminated fromthe design and a transmission gate is usedwhich in turn reduces the circuit complexity.In this paper we present a comparison ofimplicit type flip-flops in terms of its transistorcount , delay and power consumption. Thecomparison includes the elucidation of circuitoperation, simulation and power estimation.The operation of each flip-flop is estimatedand it is simulated using microwind and TSPICE simulator. The analysis of the variousparameters are carried out at 0.12µmtechnology.Depending on the method of pulsegeneration, P-FF designs can be classified asimplicit or explicit [6]. In an implicit-type PFF, the pulse generator is a built-in logic ofthe latch design, and no explicit pulsesignals are generated. In an explicit-type PFF, the designs of pulse generator and latchare separate. Implicit pulse generation isoften considered to be more power efficientthan explicit pulse generation. This isbecause the former merely controls thedischarging path while the latter needs tophysically generate a pulse train. Implicittype designs, however, face a lengtheneddischarging path in latch design, which leadsto inferior timing characteristics. Thesituation deteriorates further when lowpower techniques such as conditionalcapture, conditional pre-charge, conditionaldischarge, or conditional data mapping areKeywords:Pulse triggered, low power, flip-flop1. INTRODUCTION:Flip-flops (FFs) are the basic storageelements used extensively in all kinds ofdigital designs. In particular, digital designsnowadays often adopt intensive pipeliningtechniques and employ many FF-richmodules. A P-FF consists of a pulsegenerator for generating strobe signals and alatch for data storage. Since triggeringpulses generated on the transition edges ofthe clock signal are very narrow in pulse171

ISSN 2278-3091International Journal of Advanced Trends in Computer Science and Engineering, Vol.2 , No.2, Pages : 171-176 (2013)Special Issue of NCRTECE 2013 - Held during 8-9 February, 2013 in SMK Fomra Institute of Technology, OMR, Thaiyur, Kelambakkam, Chennaiapplied [7]–[10]. As a consequence, thetransistors of pulse generation logic areoften enlarged to assure that the generatedpulses are sufficiently wide to trigger thedata capturing of the latch. Explicit-type PFF designs face a similar pulse width controlissue, but the problem is further complicatedin the presence of a large capacitive load,e.g., when one pulse generator is sharedamong several latches.takes complementary and delay skewedclock signals to generate a transparentwindow equal in size to the delay byinverters I1-I3. Two practical problems existin this design. First, during the rising edge,nMOS transistors N2 and N3 are turned on.In this paper, we will present anovel low-power implicit-type P-FF designfeaturing a conditional pulse-enhancementscheme. Three additional transistors areemployed to support this feature. In spite ofa slight increase in total transistor count,transistors of the pulse generation logicbenefit from significant size reductions andthe overall layout area is even slightlyreduced. This gives rise to nces against other P-FF designs. Inspite of a slight increase in total transistorcount, transistors of the pulse generationlogic benefit from significant size reductionsand the overall layout area is even slightlyreduced.Figure 1(a). ip-DCO2.2 MHLLF(Modified Hybrid Latch Flipflop)An improved P-FF design, namedMHLLF Fig.1 (b) MHLLF, by employing astatic latch structure presented in [10]. Nodeis no longer pre charged periodically by theclock signal. A weak pull-up transistor P1controlled by the FF output signal Q is usedto maintain the node level at high when Q iszero. This design eliminates the unnecessarydischarging problem at node. However, itencounters a longer Data-to-Q (D-to-Q)delay during “0” to “1” transitions becausenode is not pre-discharged. Largertransistors N3 and N4 are required toenhance the discharging capability. Anotherdrawback of this design is that nodebecomes floating when output Q and input2. IMPLICIT TYPE P-FF:2.1 ip-DCO(implicit pulsed-Data Close toOutput)Some conventional implicit-type PFF designs, which are used as the referencedesigns in later performance comparisons,are first reviewed. A state-of-the-art P-FFdesign, named ip-DCO, is given in Fig 1(a)[6]. It contains an AND logic-based pulsegenerator and a semi-dynamic structuredlatch design. Inverters I5 and I6 are used tolatch data and inverters I7 and I8 are used tohold the internal node. The pulse generator172

ISSN 2278-3091International Journal of Advanced Trends in Computer Science and Engineering, Vol.2 , No.2, Pages : 171-176 (2013)Special Issue of NCRTECE 2013 - Held during 8-9 February, 2013 in SMK Fomra Institute of Technology, OMR, Thaiyur, Kelambakkam, ChennaiData both equal to “1 ”. Extra DC poweremerges if node X is drifted from an intact“1”.circuitry is thus needed to ensure nodecan be properly discharged. This implieswider N1 and N2 transistors and alonger delay from the delay inverter I1to widen the discharge pulse width.Figure 1 (b). MHLLF2.3. SCCER(Single Ended ConditionalCapture Energy Recovery)Figure 1( c ). SCCERA refined low power P-FFdesign named SCCER using a conditionaldischarged technique [9], [8]. In this design,the keeper logic (back-to-back inverters I7and I8 in Fig. 1(a) is replaced by a weak pullup transistor P1 in conjunction with aninverter I2 to reduce the load capacitanceof node [8]. The discharge path containsnMOS transistors N2 and N1 connected inseries. In order to eliminate superfluousswitching at node, an extra nMOStransistor N3 is employed. Since N3 iscontrolled by Q fdbk, no discharge occursif input data remains high. The worst casetiming of this design occurs when inputdata is “1” and node is discharged throughfour transistors in series, i.e., N1 throughN4, while combating with the pull uptransistor P1. A powerful pull-down2.4. P-FF Design with conditional pulseenhancement schemeThe design, as shown in Fig. 1(d), adoptstwo measures to overcome the problemsassociated with existing P-FF designs. Thefirst one is reducing the number of nMOStransistors stacked in the discharging path.The second one is supporting a mechanismto conditionally enhance the pull downstrength when input data is “1.” Refer to Fig.1(d), the upper part latch design is similar tothe one employed in SCCER design [12]. Asopposed to the transistor stacking design inFig. 1(a) and (c), transistor N2 is removedfrom the discharging path.Transistor N2, inconjunction with an additional transistor N3,forms a two-input pass transistor logic173

ISSN 2278-3091International Journal of Advanced Trends in Computer Science and Engineering, Vol.2 , No.2, Pages : 171-176 (2013)Special Issue of NCRTECE 2013 - Held during 8-9 February, 2013 in SMK Fomra Institute of Technology, OMR, Thaiyur, Kelambakkam, Chennai(PTL)-based AND gate [13], [14] to controlthe discharge of transistor N1. Since the twoinputs to the AND logic are mostlycomplementary (except during the transitionedges of the clock), the output node is keptat zero most of the time. At the rising edgesof the clock, both transistors N2 and N3 areturned on and collaborate to pass a weaklogic high to node , which then turns ontransistor N1 by a time span defined by thedelay inverter I1. The switching power atnode can be reduced due to a diminishedvoltage swing.removed from the design. nMOS passtransistor logic passes only strong 0 whereastransmission gate passes strong 0 and strong1. By doing so we get reduced transistorcount and hence area gets reduced which isan important criteria in this modern era withthe improved VLSI technology. Use oftransmission gate reduces the voltage dropacross the pass transistor and hence powerdissipation gets reduced. It also doubles thearea and interconnects but the overall size ofthe circuit gets reduced. At rising edge ofthe clock N1 turns on and at falling edge ofthe clock N2 gets turns on. If both clock andData are high transistors N1, N5, N4 and P2turns on while N2 and N6 turns off. If datais low transistor N6 turns on and transistorN5 turns off. Hence output occurs with lowswitching activity.Figure 1(d). P-FF Design with conditional pulseenhancement schemeFigure 2 .Proposed design3. PROPOSED DESIGNThe design is shown in figure 2. Itovercomes the problem of the abovedescribed flip-flop. Referring figure 1 , theproposed design is similar to it in case oflatching circuit and it differs only in thepulse generation circuit. It replaces twoinput pass transistor logic (PTL)-based ANDgate by a transmission gate and N1 and P3 is4.RESULTA simulation window appears with inputsand output. The power consumption isalso shown on the right bottom portionof the window. If you are unable tomeet the specifications of the circuitchange the transistor sizes. Generate the174

ISSN 2278-3091International Journal of Advanced Trends in Computer Science and Engineering, Vol.2 , No.2, Pages : 171-176 (2013)Special Issue of NCRTECE 2013 - Held during 8-9 February, 2013 in SMK Fomra Institute of Technology, OMR, Thaiyur, Kelambakkam, Chennailayout again and run the simulations tillyou achieveyourtargetdelays.Depending on the input sequencesassigned at the input the output is observedin the simulation.To demonstrate thesuperiority of the proposed design, postlayout simulations on various P-FF designswere conducted toobtaintheirperformance figures. These designsinclude the three P-FF designs shown inFig. 1 (ip-DCO [6], MHLLF [9], SCCER[10]), another P-FF design calledconditional capture FF (CCFF) [7], and twoother non-pulse-triggered FF designs, i.e.,a sense-amplifier-based FF (SAFF) [2],and a conventional transmission gate-basedFF (TGFF). The operating condition usedin simulations is 500 MHz/1.0 COUNT5.CONCLUSIONIn this paper, the various Flip-flopdesignlike,ip-DCO, MHLLFandSCCER are discussed. These were beenalso designed in Microwind tool and thoseresult waveforms are also discussed. Thecomparison table also added to verify thedesigned methods. With these all resultsproposed design is better than ip-DCO andMHLLF designs.6. REFERENCE[1] H. Kawaguchi and T. Sakurai, “A reducedclock-swingflip-flop (RCSFF) for 63%power reduction,” IEEE J. Solid-State Circuits,vol.33, no. 5, pp. 807-811, May 1998.[2] A. G. M. Strollo, D. De Caro, E. Napoli, andN. Petra, “A novel high speed sense-amplifierbased flip-flop,”IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 13, no. 11, pp. 12661274, Nov. 2005.Figure 3. Output WaveformTable 1.Comparions of ff175