EEC 116 Lecture #5: CMOS Logic

3y ago
106 Views
8 Downloads
872.83 KB
51 Pages
Last View : 13d ago
Last Download : 2m ago
Upload by : Baylee Stein
Transcription

EEC 116 Lecture #5:CMOS LogicRajeevan Amirtharajah Bevan BaasUniversity of California, DavisJeff ParkhurstIntel Corporation

Announcements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 2 due this Wednesday at 4 PM in box,Kemper 2131Amirtharajah, EEC 116 Fall 20112

Outline Review: CMOS Inverter Transient Characteristics Review: Inverter Power Consumption Combinational MOS Logic Circuits: Rabaey 6.16.2 (Kang & Leblebici, 7.1-7.4) Combinational MOS Logic Transient Response– AC Characteristics, Switch ModelAmirtharajah, EEC 116 Fall 20113

Review: CMOS Inverter VTCP linearN cutoffP cutoffN linearP linearN satP satN satP satN linearAmirtharajah, EEC 116 Fall 20114

Review: Logic Circuit Delay For CMOS (or almost all logic circuit families), onlyone fundamental equation necessary to determinedelay:dVI CdtΔV Consider the discretized version:I CΔtΔV Rewrite to solve for delay:Δt CI Only three ways to make faster logic: C, ΔV, IAmirtharajah, EEC 116 Fall 20115

Review: Inverter Delays High-to-low and low-to-high transitions (exact):t PHLt PLH 2VT 0,n 4(VOH VT 0,n ) CL 1 ln k n (VOH VT 0,n ) VOH VT 0,n VOH VOL k p (VOH 4(VOH VOL VT 0, p ) 2 VT 0, pCL ln 1 VV VOL VT 0, p ) VOH VOL VT 0, pOHOL Similar exact method to find rise and fall times Note: to balance rise and fall delays (assuming VOH VDD, VOL 0V, and VT0,n VT0,p) requireskpkn 1Amirtharajah, EEC 116 Fall 2011 W L pμn W 2.5 L n μ p6

Review: Inverter Power Consumption Static power consumption (ideal) 0– Actually DIBL (Drain-Induced Barrier Lowering),gate leakage, junction leakage are still present Dynamic power consumptionTPavg1 v(t )i(t )dtT0PavgT /2TdVout dVout 1 Vout Cload dt dt (VDD Vout ) CloadT 0dtdt T /2PavgT /2T 2 Vout 1 1 Cload VDDVout Cload CloadVout 2 T 2 2 T /2 0 Pavg122 CloadVDD CloadVDD fTAmirtharajah, EEC 116 Fall 20117

Static CMOS Complementary pullupnetwork (PUN) and pulldownnetwork (PDN) Only one network is on at atime PUN: PMOS devices– Why? PDN: NMOS devices– Why?ABCPUNFABCPDN PUN and PDN are dualnetworksAmirtharajah, EEC 116 Fall 20118

Dual Networks Dual networks: parallelconnection in PDN seriesconnection in PUN, viceversaExample: NAND gateparallelA If CMOS gate implementsBlogic function F:– PUN implements function FFseries– PDN implements function G FAmirtharajah, EEC 116 Fall 20119

NAND Gate NAND function: F A B PUN function: F A B A B– “Or” function ( ) parallel connection– Inverted inputs A, B PMOS transistors PDN function: G F A B– “And” function ( ) series connection– Non-inverted inputs NMOS transistorsAmirtharajah, EEC 116 Fall 201110

NOR Gate NOR gate operation: F A BA PUN: F A B A BB PDN: G F A BAmirtharajah, EEC 116 Fall 2011AB11

Analysis of CMOS Gates Represent “on” transistors as resistors1WR1WR1WR Transistors in series resistances in series Effective resistance 2R Effective length 2LAmirtharajah, EEC 116 Fall 201112

Analysis of CMOS Gates (cont.) Represent “on” transistors as resistors0WRWWRR00 Transistors in parallel resistances in parallel Effective resistance ½ R Effective width 2WAmirtharajah, EEC 116 Fall 201113

CMOS Gates: Equivalent Inverter Represent complex gate as inverter for delayestimation Typically use worst-case delays Example: NAND gate– Worst-case (slowest) pull-up: only 1 PMOS “on”– Pull-down: both NMOS “on”WPWPWNWP½ WNWNAmirtharajah, EEC 116 Fall 201114

Example: Complex GateDesign CMOS gate for this truth table:ABCF00010011010101111001101011001110F A (B C)Amirtharajah, EEC 116 Fall 201115

Example: Complex GateDesign CMOS gate for this logic function:F A (B C) A B C1. Find NMOS pulldown network diagram:G F A (B C)ABCNot a unique solution: can exchange order ofseries connectionAmirtharajah, EEC 116 Fall 201116

Example: Complex Gate2. Find PMOS pullup network diagram: F A (B C)BACFNot a unique solution: can exchange order ofseries connection (B and C inputs)Amirtharajah, EEC 116 Fall 201117

Example: Complex GateCompleted gate:AWPABWNBWPCWP What is worse-case pulldown delay?F Effective inverter for delay calculation:WNC What is worse-case pullup delay?WNAmirtharajah, EEC 116 Fall 2011½ WP½ WN18

CMOS Gate Design Designing a CMOS gate:– Find pulldown NMOS network from logic functionor by inspection– Find pullup PMOS network By inspection Using logic function Using dual network approach– Size transistors using equivalent inverter Find worst-case pullup and pulldown paths Size to meet rise/fall or threshold requirementsAmirtharajah, EEC 116 Fall 201119

Analysis of CMOS gates Represent “on” transistors as resistors1WR1WR1WR Transistors in series resistances in series Effective resistance 2R Effective width ½ W (equivalent to 2L) Typically use minimum length devices (L Lmin)Amirtharajah, EEC 116 Fall 201120

Analysis of CMOS Gates (cont.) Represent “on” transistors as resistors0WRWWRR00 Transistors in parallel resistances in parallel Effective resistance ½ R Effective width 2W Typically use minimum length devices (L Lmin)Amirtharajah, EEC 116 Fall 201121

Equivalent Inverter CMOS gates: many paths to Vdd and Gnd– Multiple values for VM, VIL, VIH, etc– Different delays for each input combination Equivalent inverter– Represent each gate as an inverter withappropriate device width– Include only transistors which are on or switching– Calculate VM, delays, etc using inverter equationsAmirtharajah, EEC 116 Fall 201122

Static CMOS Logic Characteristics For VM, the VM of the equivalent inverter is used(assumes all inputs are tied together)– For specific input patterns, VM will be different For VIL and VIH, only the worst case is interestingsince circuits must be designed for worst-casenoise margin For delays, both the maximum and minimummust be accounted for in race analysisAmirtharajah, EEC 116 Fall 201123

Equivalent Inverter: VM Example: NAND gate threshold VMThree possibilities:– A & B switch together– A switches alone– B switches alone What is equivalent inverter for each case?Amirtharajah, EEC 116 Fall 201124

Equivalent Inverter: Delay Represent complex gate as inverter for delayestimation Use worse-case delays Example: NAND gate– Worse-case (slowest) pull-up: only 1 PMOS “on”– Pull-down: both NMOS “on”WPWPWNWP½ WNWNAmirtharajah, EEC 116 Fall 201125

Example: NOR gate Find threshold voltage VM whenboth inputs switchsimultaneouslyAWPBWPAWNB Two methods:– Transistor equations (complex)FWNAmirtharajah, EEC 116 Fall 2011– Equivalent inverter– Should get same answer26

Example: Complex GateCompleted gate:AWPAB What is worse-case pullup delay?BWPCWPF Effective inverter for delay calculation:WNWNC What is worse-case pulldown delay?WN½ WP½ WNAmirtharajah, EEC 116 Fall 201127

Transistor Sizing Sizing for switching threshold– All inputs switch together Sizing for delay– Find worst-case input combination Find equivalent inverter, use inverter analysis toset device sizesAmirtharajah, EEC 116 Fall 201128

Common CMOS Gate Topologies And-Or-Invert (AOI)– Sum of products boolean function– Parallel branches of series connected NMOS Or-And-Invert (OAI)– Product of sums boolean function– Series connection of sets of parallel NMOSAmirtharajah, EEC 116 Fall 201129

Stick Diagrams Dimensionless layout sketches Only topology is important Two primary uses– Useful intermediate step Transistor schematic is the first step Layout is the last step– Final layout generated automatically by “compaction”program Not widely used; a topic of research Use colored pencils or pens whosecolors match Cadence layer colorsAmirtharajah, EEC 116 Fall 201130

Inverter Stick Diagram Diagram here uses magicstandard color scheme Label all nodesVdd Transistor widths (W) oftenshown—with varying units– Often in λ in this classW 9λinout– Also nm or µm– Sometimes as a unit-lessratio—this stick diagram couldalso say the PMOS is 1.5xwider than the NMOS (saying“1” and “1.5” instead of “6λ” and“9λ”Amirtharajah, EEC 116 Fall 2011W 6λGnd31

Stick Diagrams Can also draw contactswith an “X” Do not confuse this “X”with the chip I/O and powerpads on the edge of chip(shown with a box with an“X”) or any other markerschipcoreAmirtharajah, EEC 116 Fall 2011VddW 9λinoutW 6λGnd32

Layout for the Inverter in the Stick DiagramAmirtharajah, EEC 116 Fall 2011Source: Omar Sattari33

Graph-Based Dual Network Use graph theory to help design gates– Mostly implemented in CAD tools Draw network for PUN or PDN– Circuit nodes are vertices– Transistors are edgesFFAABBgndAmirtharajah, EEC 116 Fall 201134

Graph-Based Dual Network (2) To derive dual network:– Create new node in each enclosed region of graph– Draw new edge intersecting each original edge– Edge is controlled by inverted inputFvddAn1BBAgndFABn1F– Convert to layout using consistent Euler pathsAmirtharajah, EEC 116 Fall 201135

Propagation Delay Analysis - The Switch ModelRON VDDVDDRpRpAVDDRpRpBABFRnFBRnCLCLRnAA(b) 2-input NAND(a) InverterRpAFRnRnABCL(c) 2-input NORtp 0.69 Ron CL(assuming that CL dominates!)Amirtharajah, EEC 116 Fall 201136

Switch Level Model Model transistors as switches withseries resistance Resistance Ron average resistancefor a transitionA Capacitance CL average loadcapacitance for a transition (same asRNwe analyzed for transient inverterdelays)AAmirtharajah, EEC 116 Fall 2011RPCL37

What is the Value of Ron?Amirtharajah, EEC 116 Fall 201138

Switch Level Model DelaysDelay estimation using switch-levelmodel (for general RC circuit):RNdVCI Cdt dV IdtCLVRCI dt dV RVV1RCt1 t0 t p dVVV0 V1 t p RC [ln(V1 ) ln(V0 )] RC ln V0 Amirtharajah, EEC 116 Fall 201139

Switch Level Model RC Delays For fall delay tphl, V0 VDD, V1 VDD/2 V1 12 VDD t p RC ln RC ln VDD V0 t p RC ln(0.5)t phl 0.69 RnC Lt plh 0.69 R p C LAmirtharajah, EEC 116 Fall 2011Standard RC-delayequations from literature40

Numerical Examples Example resistances for 1.2 μm CMOSAmirtharajah, EEC 116 Fall 201141

Analysis of Propagation DelayVDDRpA1. Assume Rn Rp resistance of minimumsized NMOS inverterRpBFRnCLBRnA2. Determine “Worst Case Input” transition(Delay depends on input values)3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pullsup the output node- For 2 PMOS devices in parallel, theresistance is lowertpLH 0.69Rp CL2-input NAND4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in seriestpHL 0.69(2Rn)CLAmirtharajah, EEC 116 Fall 201142

Design for Worst CaseV DDVDD1AB4C412ABF2CL2A2DBADAmirtharajah, EEC 116 Fall 201121BNAND GateF2C2Complex GateHere it is assumed that Rp Rn43

Fan-In and Fan-OutVADDCBABCDDFan-OutNumber of logic gatesconnected to output(2 FET gate capacitancesper fan-out)Fan-InNumber of logical inputsQuadratic delay term due to:1. Resistance increasing2. Capacitance increasingfor tpHL (series NMOS)tp proportional to a1FI a2FI2 a3FOAmirtharajah, EEC 116 Fall 201144

Fast Complex Gates - Design Techniques Increase Transistor Sizing:Works as long as Fan-out capacitancedominates self capacitance (S/D cap increaseswith increased width) Progressive Sizing:OutInNMNCLM 1 M 2 M 3 MNIn3In2In1M3M2M1C3C2C1Amirtharajah, EEC 116 Fall 2011Distributed RC-lineCan Reduce Delay by morethan 30%!45

Fast Complex Gates - Design Techniques (2) Transistor OrderingPlace last arriving input closest to output nodecritical pathcritical pathCLIn3M3In2M2C2In1M1C1(a)Amirtharajah, EEC 116 Fall 2011CLIn1M1In2M2C2In3M3C3(b)46

Fast Complex Gates - Design Techniques (3) Improved Logic DesignNote Fan-Out capacitance is the same, but Fan-Inresistance lower for input gates (fewer series FETs)Amirtharajah, EEC 116 Fall 201147

Fast Complex Gates - Design Techniques (4) Buffering: Isolate Fan-in from Fan-outCLCLKeeps high fan-in resistance isolated from largecapacitive load CLAmirtharajah, EEC 116 Fall 201148

4 Input NAND GateVDDVDDIn1In2In3In4OutIn1In2OutIn3In4GNDIn1 In2 In3 In4Amirtharajah, EEC 116 Fall 201149

Capacitances in a 4 input NAND db6Cgs7In3Cgd7Csb7 Cgs8In4Cdb Cgd8Csb8Cdb87VoutCgdIn1Cgs6In2Cgd6Csb4Note that the value of Cload for calculatingpropagation delay depends on which capacitancesneed to be discharged or charged when the criticalsignal arrives.Example: In1 In3 In4 1. In2 0. In2 switches from lowto high. Hence, Nodes 3 and 4 are already discharged toground. In order for Vout to go from high to low Voutnode and node 2 must be discharged.CL Cgd5 Cgd7 Cgd8 2Cgd6(Miller) Cdb5 Cdb6 Cdb7 Cdb8 Cgd1 Cdb1 Cgs1 Csb1 2Cgd2 Cdb2 CwAmirtharajah, EEC 116 Fall 201150

Next Topic: Arithmetic Computing arithmetic functions with CMOS logic– Half adder and full adder circuits– Circuit architectures for addition– Array multipliersAmirtharajah, EEC 116 Fall 201151

Amirtharajah, EEC 116 Fall 2011 3 Outline Review: CMOS Inverter Transient Characteristics Review: Inverter Power Consumption Combinational MOS Logic Circuits: Rabaey 6.1- 6.2 (Kang & Leblebici, 7.1-7.4) Combinational MOS Logic Transient Response – AC Characteristics, Switch Model

Related Documents:

Jun 30, 2003 · which could become explosive under certain conditions (the danger is a potential one). . though the latter could be self certified. Standards Standards must be current. This may mean, as with dust, entirely new standards. In the . 73/23/EEC 93/68/EEC 89/336/EEC 92/31/EEC 93/68/EEC 89/392/EEC 91/368/EEC 93/44/EEC 93/68/EEC 94/9/EC Ref Nos

Introduction of Chemical Reaction Engineering Introduction about Chemical Engineering 0:31:15 0:31:09. Lecture 14 Lecture 15 Lecture 16 Lecture 17 Lecture 18 Lecture 19 Lecture 20 Lecture 21 Lecture 22 Lecture 23 Lecture 24 Lecture 25 Lecture 26 Lecture 27 Lecture 28 Lecture

Circuits-A CMOS VLSI Design Slide 2 Outline: Circuits Lecture A – Physics 101 – Semiconductors for Dummies – CMOS Transistors for logic designers Lecture B – NMOS Logic – CMOS Inverter and NAND Gate Operation – CMOS Gate Design – Adders – Multipliers Lecture C – P

Installation OCTOPUS 8TX-EEC Release 07 01/2021 2.3.3 Pin assignment OCTOPUS 8TX PoE-EEC 33 2.3.4 Pin assignment OCTOPUS 8TX-EEC-M 33 2.4 Operating the device 33 2.5 Connecting data cables 34 2.6 Configuration (optional) 35 2.6.1 Configuration readout 41 3 Making basic settings 42 3.1 First login (Password change) 43

Apr 16, 2009 · Regulations EECIS Concentration State Regulations . Preschool Education and Care EEC –Preschool lead teacher EEC - Family Child Care Family Support and Engagement EEC - Family Child Care Youth and Community Outreach EEC –Out-of-school time leader Administration and Supervision EEC –Director II DPH –Department of Public Health

Low Voltage Directive: 73/23/EEC Machinery Directives: 89/392/EEC, 91/368/EEC, 93/C 133/04, 93/68/EEC Electromagnetic Capability Directives: 89/336, 92/31/EEC Standards Safety Requirements for Arc Welding Equipment part 1: EN 60974-1: 1990 Arc Welding Equipment Part 1: Welding

CMOS Digital Circuits Types of Digital Circuits Combinational . – Parallel Series – Series Parallel. 15 CMOS Logic NAND. 16 CMOS Logic NOR. 17 CMOS logic gates (a.k.a. Static CMOS) . nMOS and pMOS are not ideal switches – pMOS passes strong 1 , but degraded (weak) 0

The principle of archaeological illustration outlined above remains the same, and digital technology has not changed this: What it has done has provided different tools, in the form of graphics software and scanning hardware to enable a more efficient execution of illustrations. This guide addresses how to illustrate small finds using existing principles within a digital environment which is .