ECE2274 NAND Logic Gate, NOR Logic Gate, And CMOS

3y ago
146 Views
5 Downloads
691.86 KB
6 Pages
Last View : 4d ago
Last Download : 1m ago
Upload by : Jerry Bolanos
Transcription

ECE2274Pre-Lab for MOSFET logic LTspiceNAND Logic Gate, NOR Logic Gate, and CMOS InverterInclude CRN # and schematics.1. NMOS NAND Logic GateUse Vdd 10Vdc. For the NMOS NAND LOGIC GATE shown below, use the 2N7000MOSFET LTspice model that has a gate to source voltage Vgs threshold of 2V (Vto 2.0).The input logic “1” 10 volt and ground as a logic “0”. Make a truth table showing the fourpossible combinations of Vin1 and Vin2 and the outputs. Choose Rd (drain current limitresistor) such that the drain currents of the NMOS devices will be about 30mA when the Voutis in a low state. Then run a DC .OP Bias Point simulation (use the added 2N7000 model inLTspice) on your design with the four possible input combinations for Vin1 and Vin2 to verifyyour gate. Observe the output voltage value for each input combination. Print your circuitschematic showing voltages for all four input S NAND Logic GatePage 1 of 6MOSFET Logic Revised: March 22, 2020

2. NMOS NOR Logic GateUse Vdd 10Vdc. Design an NMOS NOR logic gate using the 2N7000 MOSFET the modelhas Vto 2.0 . Limit the drain current total to 30mA with a drain resistor (Rd). Show all workfor your design and drawing. Then simulate your design in LTspice with DC .OP Bias Pointsimulations as you did for the NAND logic gate. Print out your circuit schematic showingvoltages for all four input combination add from the view menu node voltage and drian currentto display on the schematic. Also, fill in the truth table with all of the DC .OP Bias Pointsimulation voltage values.3. CMOS InverterUse VDD 10Vdc. Design a CMOS inverter using a NMOS and PMOS FET. The drain currentwill be limited by the two external 100Ω source resistors (RSnmos, RSpmos). The MOSFETsthat we use in the lab both have a VGS threshold voltage of about 2.0V and internalresistance is RS 0.2Ω. Assume that there is a input voltage level 2.0V Vin VDD – 2.0Vthat will turn on both FETs at the same time. This will cause a large current flow that coulddamage the two devices. Because there is period of time when both devices on we will use a1kHz triangle waveform as input so the time the devise send in a high current state will short inLTspice.(Triangle Wave) Use LTspice to plot the input triangle waveform (PULSE) 0 to 10v, outputvoltage waveform, and the current thru the devices.(DC sweep) Plot CMOS Transfer characteristic curve use DC sweep Vin from 0V to 10V. PlotVout vs Vin mark on plot VOH , VOL , VIL and VIH.VDDVin (Triangle Wave) set PULSEVin (DC Sweep)Q1 PMOSQ2 NMOS9Vdc1kHz amplitude 0v to 10v Triangle wavePULSE 0V, 10V Tr 0.5ms Tf 0.5msTper 1ms, Td 0, Ton 1ns0V to 10V 200mv stepLTspice (TP0606) Lab (TP0606)LTspice (2N7000) Lab (2N7000)LTspice TP0606 PMOSInternal resistanceVto -2 voltsRS 0.2 ohmsLTspice 2N7000 NMOSInternal resistanceVto 2 voltsRS 0.2 ohmsPage 2 of 6MOSFET Logic Revised: March 22, 2020

.include 2N7000.sub.include TP0606.subRSpmos100TP0606VddVout.dc Vin 0 10 0.110VVinM1Rin10kM2Vin2N70000Rser 50Rload10kRSnmos100CMOS inverter for LTspiceCmos Transfer characteristic curve.Required Attachments:1. NAND Truth table.2. Four schematics with voltages and currents of nodes and branches3. NOR Truth table4. Four schematics with voltages and currents of nodes and branches5. Cmos Transfer characteristic curve (Triangle Wave), (DC sweep) 2 plots schematic.Page 3 of 6MOSFET Logic Revised: March 22, 2020

Laboratory ExerciseMOSFET logicNAND GATE, NOR GATE, and CMOS inverter1. Build the NAND gate circuit from prelab on LTspice. Connect Vin1 and Vdd to 10V.a. Run a DC Sweep of the NAND circuit by sweeping Vin2 from 0V to 10V with increments of1V. Include the plot. Answer the question on the datasheet.b. Change the voltage Vin2 to a pulse with Vinitial 0V, Von 10V, Trise Tfall 10u, Ton 0.5m and Tperiod 1m. This will produce a square wave from 0V to 10V. Run a transientsimulation, plot the output voltage Vout from the NAND circuit, and answer the questions onthe datasheet. Include the plot.2. Build the NOR gate circuit from prelab on LTspice. Connect Vin1 and Vdd to 10V.a. Run a DC Sweep of the NOR circuit by sweeping Vin2 from 0V to 9V with increments of 1V.Include the plot. Answer the question on the datasheet.b. Change the voltage Vin2 to a pulse with Vinitial 0V, Von 10V, Trise Tfall 10u, Ton 0.5m and Tperiod 1m. Run a transient simulation and plot the output voltage Vout from theNOR circuit and answer the questions on the datasheet. Include the plot.3. Build CMOS Inverter circuit on LTspice with both the external 100Ω source resistorsto limit the current.a. Run a DC sweep with the input from 0V to 10V in 200mv steps. Plot the Vout voltage and fillout the table in the datasheet. Include the plot.b. Change the voltage Vin to a pulse with Vinitial 0V, Von 10V, Trise Tfall 10u, Ton 0.5m and Tperiod 1m. Run a transient simulation and plot the output voltage Vout from theInverter circuit and answer the questions on the datasheet. Include the plot.Page 4 of 6MOSFET Logic Revised: March 22, 2020

DATA SHEET MOSFET logicName: CRN:NAND GATE, NOR GATE, and COMS Inverter1. NAND GATEa. From the DC Sweep what is the input voltage at which the Vout starts to change?b. i) What is the rise time? (time taken for the output to rise to 90% of the maximum value)ii) What is the fall time? (time taken for the output to fall to 10% of the maximum value)2. NOR GATEa. From the DC Sweep what is the input voltage at which the Vout starts to change?b. i) What is the rise time? (time taken for the output to rise to 90% of the maximum value)ii) What is the fall time? (time taken for the output to fall to 10% of the maximum value)3. CMOS DNMOSGS10KRload100currentlimitPage 5 of 6MOSFET Logic Revised: March 22, 2020

a. i) Table CMOS inverter static test. Vdd 10VdcVin0v10vVoutii) Which device is on when the voltage is 0V?iii) Which device is on when the voltage is 10V?From DC sweep of CMOS inverter fill out the following table:NameVoltageVOHVOLVILVIHb. i) What is the rise time of the inverter?ii) What is the fall time of the inverter?Required Attachments:1. DC Sweep of NAND gate2. Transient Simulation of NAND Gate3. DC Sweep of NOR Gate4. Transient Simulation of NOR Gate5. DC Sweep of Inverter6. Transient Simulation of InverterPage 6 of 6MOSFET Logic Revised: March 22, 2020

MOSFET Logic Revised: March 22, 2020 ECE2274 Pre-Lab for MOSFET logic LTspice NAND Logic Gate, NOR Logic Gate, and CMOS Inverter Include CRN # and schematics. 1. NMOS NMOSNAND Logic Gate Use Vdd 10Vdc. For the NMOS NAND LOGIC GATE shown below, use the 2N7000 MOSFET LTspice model that has a gate to source voltage Vgs threshold of 2V (Vto 2.0).File Size: 586KB

Related Documents:

Universal Gate -NAND I will demonstrate The basic function of the NAND gate. How a NAND gate can be used to replace an AND gate, an OR gate, or an INVERTER gate. How a logic circuit implemented with AOI logic gates can be re-implemented using only NAND gates. That using a single gate type, in this case NAND, will reduce the number of integrated circuits (IC) required to implement a

Context: NAND and NAND driver I Provide an abstraction layer for raw NAND devices I Take care of registering NAND chips to the MTD layer I Expose an interface for NAND controllers to register their NAND chips: struct nand_chip I Implement the glue between NAND and MTD logics I Provide a lot of interfaces for other NAND related stu

CS 150 - Sringp 0012 - Combinational Implementionta - 1 Combinational Logic Implementation z Two-level logic y Implementations of two-level logic y NAND/NOR z Multi-level logic y Factored forms y And-or-invert gates z Time behavior y Gate delays y Hazards z Regular logic y Multiplexers

NAND universal gates. Fig.3 Half adder circuit design using CMOS NAND gates on cadence virtuoso [1]. NAND gates were used to create a half adder. To design, any type of digital circuit used a universal gate. Here NAND gate used to design for half adder circuit because NAND gate is a universal gate. It is always simple and

7 -21 Two-Level NAND-NAND Circuits Procedure for designing a minimum two-level NAND-NAND network: 1. Find a minimum SOP expression

An XOR built from four NAND gates.MODEL P PMOS.MODEL N NMOS.SUBCKT NAND A B Y Vdd Vss M1 Y A Vdd Vdd P M2 Y B Vdd Vdd P M3 Y A X Vss N M4 X B Vss Vss N.ENDS X1 A B I1 Vdd 0 NAND X2 A I1 I2 Vdd 0 NAND X3 B I1 I3 Vdd 0 NAND X4 I2 I3 Y Vdd 0 NAND

For I am convinced that neither death nor life, nor angels, nor rulers, nor things present, nor things to come, nor powers, nor height, nor depth, nor anything else in all creation, will be able to separate us from the love of God in Christ Jesus our Lord. (Romans 8:38) Do not fear, for I am with y

3/15/2021 6105636 lopez richard 3/15/2021 5944787 padilla elizabeth 3/15/2021 6122354 rodriguez alfredo 3/16/2021 6074310 aldan francisco 3/16/2021 6060380 bradley vincent 3/16/2021 6133841 camacho victor 3/16/2021 6100845 cardenas cesar 3/16/2021 6133891 castaneda jesse .