Implementation Of FPGA Based PID Controller For DC
International Journal of Engineering Trends and Technology- Volume4Issue3- 2013Implementation of FPGA based PID Controller forDC Motor Speed Control SystemPrashant Kumar#1, Ravi Mishra*21#M.E.(Student), Electronics and Telecommunication Engineering DepartmentSSCET, CSVTU, Bhilai, India*2Associate Professor, Electrical & Electronics Engineering DepartmentSSCET, CSVTU, Bhilai, IndiaAbstract— In this paper, the implementation ofsoftware module using 'VHDL' for Xilinx FPGA(XC2S30) based PID controller for DC motor speedcontrol system is presented. The tools used forbuilding and testing the software modules are XilinxISE 9.1i and ModelSim XE III 6.3c. Before verifyingthe design on FPGA the complete design is simulatedusing Modelsim Simulation tool. A test bench iswritten where, the set speed can be changed for themotor. It is observed that the motor speed graduallychanges to the set speed and locks to the set speed.IndexTerms— Field Programmable Gate Array(FPGA), Proportional-Integral-Derivative (PID)controller, Very High Speed Integrated CircuitHardware Description Language (VHDL), PulseWidth Modulation (PWM).I. INTRODUCTIONHardware Description Languages (HDLs) areused to describe hardware for the purpose ofSimulation, Modeling, Testing, Design, andDocumentation of digital systems. The most popularHDLs are VHDL [(Very High Speed IntegratedCircuit) Hardware Description Language], andVerilog. VHDL is used to describe hardware from theabstract to the concrete level. Many of the ElectronicDesign Automation (EDA) vendors are standardizingon VHDL as input and output from their tools. Thesetools include simulation tools, synthesis tools, layouttools and testing tools.The Proportional-Integral-Derivative (PID)controllers have been widely used over the past fivedecades due to their simplicity, robustness,effectiveness and applicability for a broad class ofsystems. Despite the numerous control designapproaches that have appeared in the literature, it isestimated that, now a day’s PID controllers are stillemployed in more than 95% of industrial processes[1]. For many decades, the digital PID controller hasbeen used extensively in real time digital control. ThePID is used extensively in the field of servo motorcontrol, robotics, temperature control and powerelectronics. It has a long history of development andvery mature tuning rules. overall, the PID is animportant tool for the embedded real time digitalISSN: 2231-5381control designer. They are usually implementedeither in hardware using analog components or insoftware using computer-based systems.The emergence of field programmable gatearrays and hardware description languages allows foradded dimensions of digital PID controllers,Parallelism, Programmable bit widths and absolutedeterminism. Building PID controllers on FieldProgrammable Gate Arrays (FPGAs) improvesspeed, accuracy, power-efficiency, compactness andcost effectiveness.With the growing complexity of motor andmotion control applications, it becomes apparent thata Field Programmable Gate Array (FPGA) offerssignificant advantage over the off shelf ApplicationSpecific Standard Product (ASSP) solutions in theareas of performance, flexibility and inventorycontrol [2]. Custom motor drive interfaces such asPulse Width Modulation (PWM) can be developedeasily, quickly and at low cost. Additionally, becauseof full configurability, the same FPGA can be used invarious product ranges, reducing the need to maintaininventory for multiple devices [3].The Spartan2 family of Field-Programmable GateArrays is specifically designed to meet the needs ofhigh volume, cost-sensitive consumer electronicapplications. The six-member family offers densitiesranging from 15,000 to two million system gates.Because of their exceptionally low cost, Spartan2FPGAs are ideally suited to a wide range daccess,homenetworking,display/projection and digital television equipment.Modern FPGAs and their distinguishable capabilitieshave been advertised extensively by FPGA vendors[4]. Moreover, some refereed articles addressed theadvantages of utilizing these powerful chips [5][6].In the past two years, Spartan II and III FPGAfamilies from Xilinx have been successfully utilizedin a variety of applications, which include essors [11], and image processing [12]. ors and Digital Signal Processor (DSP)http://www.internationaljournalssrg.orgPage 471
International Journal of Engineering Trends and Technology- Volume4Issue3- 2013chips is old and well known [13][14], whereas verylittle work can be found in the literature on how toimplement PID controllers using FPGAs. A PWMgenerator is introduced in [15]. However, onlysimulation results are presented. The contributions ofthe authors in [16][17] are considered complementaryto the present work as they provide tools for buildingthe current application. The software developedprovides the user interface through on boardperipherals like Pushbuttons and Seven SegmentDisplays, so that the user can change the set speed ofthe motor as well view the data display on SevenSegment Display. The organization of this paper isgiven as follows: In section II, an overview of thecomplete system, In section III, functional modulesof a FPGA based PID controller for DC motor speedcontrol system are explained. In section IV, theimplementation results of the system are discussed.Conclusions are discussed in section V.Table 1 shows the set value of the PID controller forthe DC motor speed control system for various setspeeds.III. OVERVIEW OF FUNCTIONAL MODULESThe target FPGA device used in the present workis Spartan2 family XC2S30 manufactured by Xilinx.Design development and debugging is carried on alow-cost, FPGA ISP kit. This board provides all thetools required to design and verify Spartan2 platformdesigns. Designs are based on 8 MHz clock. Figure 2shows the Hierarchical Diagram of FPGA Based PIDController Implementation for DC motor speedcontrol system. The software tools used for buildingand testing these modules are Xilinx ISE 9.1i andModelSim XE III 6.3c.COMBINE HARDWAREII. OVERVIEW OF COMPLETE SYSTEMThe set speed is assigned to switches according to therequirement and the capture control switch isenabled. Once this is done the generated set valueand previous calculated value of speed will be readand sent to the PID controller as an error value. Tocalculate the current speed optical sensor and pulsecounter module is used in the feedback system. ThePID controller module will calculate the equivalentPID value and send to the PWM generator moduleand it is fed to the motor through DAC and once thecurrent speed equals the set speed, the motor startsrunning at the set speed. Again to change the setspeed, the above procedure is repeated by pressinganother push button switch.COMBINE PIDMOTOR INPID XILPWM2Fig. 2 Hierarchical Diagram of FPGA Based PIDControllerA. Combine hardware moduleFig. 1 Block diagram of the complete systemFigure 1 shows the overall view of the systemalong with the implemented modules on FPGA. Asthe set speed is varied, the PWM waveform alsovaries. It is observed that the current speed, which isdisplayed, on the seven segment display equals theset speed value. Also the change in the motor speedfor different switch can be observed accordingly.ISSN: 2231-5381The Combine hardware Top module is the Main Toplevel VHDL module in the hierarchy. It instantiatesthe combine– pid sub module. It interconnects all thesignals and interacts with the external world.The top module, combine-hardware moduleprovides the user interface where user can give thedesired set speed for the DC Motor. It instantiates theCombine-PID sub module. It interconnects all thesignals and interacts with the external world. Herefour push button switches, s1, s2, s3 & s4 are used toget the set speed of 1000 rpm, 800 rpm, 600 rpm, &200 rpm respectively. Same switches can also beassigned to get the other speed like 400rpm, 300 rpm,& 200 rpm by assigning the different set value to theswitches which will be one of the input for the orgPage 472
International Journal of Engineering Trends and Technology- Volume4Issue3- 2013B. PID controller moduleFigure 3 shows the Combine-pid sub module havingown sub modules with main internal and externalsignal flow. The PID Controller Top module is theMain Top level module of combine hardware modulein the hierarchy. It instantiates the sub modulesmotor in, pid xil and pwm2modules. Itinterconnects all the signals and interacts with theexternal world.Controller is calculated. After calculation of error &PID value, actual output of the module is calculated,to be sent to the next module pwm2. Calculatedoutput value is written to the dac-data port. The valueof constants Kp, Ki and Kd are initialized for motorapplication.STATE FLOW DIAGRAMThe state flow diagrams are so drawn that, theyare self explanatory and gives the complete idea ofsoftware development for FPGA based PIDcontroller for DC motor speed control system. Figure4 shows State flow diagram for PID controllerFig.3 PID Controller Submodules1.Motor-in moduleThe Motor-in module receives the currentspeed data (rpm) of motor, which is latched into themodule using sensor control signal from the opticalsensor. Once the optical sensor data is latched intothe module it calculates the current speed, which issampled to the PID controller as one of the input,after every 4 micro second. This is done to get thecalculated digital value for current speed of the DCMotor.2.Pid-xil moduleOnce the current speed is calculated, this value issubtracted with the set speed value, which is set usingthe push button switches connected to s1, s2,s3 & s4,in combine hadware top module. It has several PID, DivideKg, Write2DAC, SOverloadand ConvDac. In this module amount of error &proportional, integral and derivative value of the PIDFig 4 State flow diagram for PID state machineISSN: ge 473
International Journal of Engineering Trends and Technology- Volume4Issue3- 20133.Pwm2 moduleThe last sub module of the combine-pid modulecommunicates with the pid-xil module using dac-datasignal. Here two independent increment & decrementcounters are used to generate the PWM waveform.Both the counter decides either low logic level orhigh logic level for the PWM output waveform. Theoutput value of the pid-xil module is the input valuefor these counters.The output pwm value generated by themodule is converted to the equivalent analog value tobe sent to the DC motor.IV. RESULTSmotor. In the test bench, the Top module of thedesign combine-hardware is instantiated. The inputslike Clock, Reset, Switch data and sensor are definedand the output [motor-run, speed on seven segmentdisplay {d1, d2, d3 & d4}] is observed in thesimulation window.As many sub modules are instantiated in Topmodule and as this is a hierarchical design, internalsub module signals are also observed in thewaveform window of the simulator. Once all thesignals are taken into the waveform window, thesimulation is run for 250 us (is and the changes in thesignals are observed in the waveform window. It isobserved that the motor speed gradually changes tothe set speed and locks to the set speed.A. Simulation ResultsLogic simulation in FPGA design environmentplays a very vital role in verifying the functionality ofthe designs. Simulation is a powerful way to test thesystem on a computer, before it is turned intohardware. Simulators let designer to check the valuesof signals inside the system.In the present study, for functional verification,before verifying the performance of proposedcontroller design on FPGA, the complete design issimulated using Modelsim Simulation tool (Xilinxversion ModelSim XE III 6.3c), which has precompiled libraries for all Xilinx FPGAs. A test benchis written where, the set speed can be changed for theFigure 5 shows the simulation results for the setspeed of 1000, 800, 600 & 200 rpm. It is seen thatafter certain transitions, when the error value iscalculated, the current speed becomes equals to setspeed. When the optimal values for Kp, Ki and Kdare used to calculate the current speed, the currentspeed will equal the set speed when error becomezero, hence motor starts running at the set speed.Figure 6 shows the Design Summary, Xilinxtool device utilization summary and reports thepercentage of available resources that have been usedfor the current FPGA design. The performancesummary summarizes the timing requirement andalso the proper routing of the signals.Fig. 5 Simulation result of each set speed of 1000, 800, 600 & 200 rpm for 50 micro second.ISSN: ge 474
International Journal of Engineering Trends and Technology- Volume4Issue3- 20134.S4200B. Hardware Test ResultsThe experimental studies are carried out toevaluate the performance of the controller.Configuration is the Process by which the bit streamsof a design, as generated by the developmentsoftware are loaded into the internal configurationmemory of the FPGA. To verify the performance ofthe controller design on Hardware, the VHDL code(Bit file) is downloaded into the Target FPGA device(Spartan2 family XC2S30) and the complete systemis reset. The set speed is assigned to switches s1,s2,s3& s4 according to the requirement and the capturecontrol switch is enabled. Once this is done the ADCdata will be read and PID equation implemented willcalculate the equivalent PID value and it is fed backto the motor through DAC and once the current speedFig. 7 RTL View of module Combine-hardwareAs the set speed is varied, the ADC voltage alsovaries. It is observed that the current speed, which isdisplayed, on the seven segment display is equal tothe set speed value. Also the change in the motorspeed for different switch combinations can beobserved accordingly. Table 1 shows the results ofthe DC motor speed control system for various setspeeds.v. ConclusionsFig. 6 Experimental setup of FPGA based PIDcontroller for DC motor speed control.equals the set speed, the motor starts running at theset speed. Again to change the set speed, the aboveprocedure is repeated by changing the push buttonswitch position. Figure 6 shows the experimentalsetup for DC motor speed control system. Fig 7shows RTL View of module Combine-hardware.Table 1 Push button switches for given set speed.Sl.NoPush buttonSwitchSet Speed (rpm)1.2.3.S1S2S31000800600ISSN: 2231-5381A digital PID controller is successfullyimplemented using the FPGA and its performance isverified and tested on a DC motor speed controlsystem for real-time control. The test results showedthat with PID controller added, the steady-state erroris eliminated and the desired output speed isobtained. The implementation of controller hasreduced the total hardware complexity and cost.According to the experiment done it is observed that,in the simulation, when the set speed is changed, themotor speed locks to the set speed, when the currenterror becomes zero. In brief, the role of FPGA, inmeasurement and control point of view, is to acquirethe data from sensor through analog to digitalconverter, do the processing on the acquired data andthen generate control signals to the actuator, whichintern controls the parameter being measured. FPGAsensure ease of design, lower development costs, moreproduct revenue, and the opportunity to speedproducts to market. Building PID controllers onFPGAs improves speed, accuracy, g.orgPage 475
International Journal of Engineering Trends and Technology- Volume4Issue3- 2013compactness and cost effectiveness over other digitalimplementation techniques.References[1] K.J. Astrom and T. H. Hagglund, “New TuningMethods for PID Controllers,” Proc. of 3rd EuropeanConference, pp. 2456-2462, 1995.[2]ShoulingHeandXupingXu,“Hardware/Software Co design Approach for anADALINE Based Adaptive Control System,”Journal of Computers, vol. 3, no. 2, pp. 29-36,Academy publisher, February 2008.[3] Craig Hackney, “PGA Motor Control ReferenceDesign,” Application Note: Spartan and Virtex FPGAFamilies, Xilinx XAPP808 vol. 1.0, September 16,2005.[4] Mohamed Abdelati, “FPGA-Based PIDController Implementation,” The Islamic Universityof Gaza, Palestine, This research was supported bythe Ministry of Higher Education in Palestine.[5] Anthony Cataldo, “Low-priced FPGA options setto expand,” Electronic Engineering Times Journal,no. 1361, pp. 38-45, USA, 2005.[6] Gordon Hands, “Optimised FPGAs vs dedicatedDSPs,” Electronic Product Design Journal, vol. 25,no. 12, UK, December 2004.[7] R. Jastrzebski, A. Napieralski, O. Pyrhonen andH. Saren, “Implementation and simulation of fastinverter control algorithms with the use of FPGAcircuit,” Nanotechnology Conference and TradeShow, pp. 238-241, Nanotech 2003.[8] Lin. F.S, Chen. J.F, Liang. T.J, Lin. R.L and Kuo,Y.C, “Design and implementationof FPGA-basedsingle stage photovoltaic energy conversion system,”Proceedings of IEEE Asia-Pacific Conference onCircuits and Systems, pp 745-748, Taiwan, December2004.[9] Bouzid Aliane and Aladin Sabanovic, “Designand implementation of digital bandpass FIR filter inFPGA,” Computers in Education Journal, vol.14, pp.76-81, 2004.ISSN: 2231-5381[10] M. Canet, F. Vicedo, V. Almenar and J. Valls,“FPGA implementation of an IF transceiver forOFDM-based WLAN,” IEEE Workshop on SignalProcessing Systems, SiPS: Design andImplementation , pp. 227-232, USA, 2004.[11] Xizhi Li and Tiecai Li, “ECOMIPS: Aneconomic MIPS CPU design on FPGA,”Proceedings- 4th IEEE International Workshop onSystem-on-Chip for Real-Time Applications, pp.291-294, Canada 2004.[12] R. Gao, D. Xu and J. P. Bentley,“Reconfigurable hardware implementation of animproved parallel architecture for MPEG-4motion estimation in mobile applications,” IEEETransactions on Consumer Electronics, vol.49, no.4,November 2003.[13] H. D. Maheshappa, R. D. Samuel and A.Prakashan, “Digital PID controller for speed controlof DC motors, IEEE Technical Review Journal, vol.6, no.3, pp. 171-176, India, 1989.[14] J. Tang, “PID controller using the TMS320C31DSK with on-line parameter adjustment for real-timeDC motor speed and position control,” IEEEInternational Symposium on Industrial Electronics,vol. 2, pp. 786-791, Pusan, 2001.[15] D. Deng, S. Chen and G. Joos, “FPGAimplementation of PWM pattern generators,”Canadian Conference on Electrical and ComputerEngineering, and Electronics Engineers Inc, vol. 1,pp. 225-230 May, 2001.[16] Rivera. D.E, S. Skogestad and M. Morari,“Internal Model Control 4. PID Controller Design.”Ind. Ene Chem. Proc. Des & Dev, 25, pp. 252.265,1986.[17] Nagabhushana Katte, “Design and Developmentof Computer Based Fuzzy and Integrated FuzzyLogic Controllers for Process Parameters,” Ph.DThesis July 2006.http://www.internationaljournalssrg.orgPage 476
[1]. For many decades, the digital PID controller has been used extensively in real time digital control. The PID is used extensively in the field of servo motor control, robotics, temperature control and power electronics. It has a long history of development and very mature tunin
PID-controller Today most of the PID controllers are microprocessor based DAMATROL MC100: digital single-loop unit controller which is used, for example, as PID controller, ratio controller or manual control station. Often PID controllers are integrated directly into actuators (e.g valves, servos)File Size: 1MBPage Count: 79Explore furtherWhen not to use PID-controllers - Control Systems .www.eng-tips.comPID Controller-Working and Tuning Methodswww.electronicshub.org(PDF) DC MOTOR SPEED CONTROL USING PID CONTROLLERwww.researchgate.netTuning for PID Controllers - Mercer Universityfaculty.mercer.eduLecture 9 – Implementing PID Controllerscourses.cs.washington.eduRecommended to you b
In this thesis, FPGA-based simulation and implementation of direct torque control (DTC) of induction motors are studied. DTC is simulated on an FPGA as well as a personal computer. Results prove the FPGA-based simulation to be 12 times faster. Also an experimental setup of DTC is implemented using both FPGA and dSPACE. The FPGA-based design .
The LabVIEW implementation of the control system consisted of two main parts; (i) host PC virtual instrument (VI) and (ii) FPGA VI. A host PC VI was deve loped to model the PID control transfer function and inter act with the FPGA based RIO hardware. The FPGA VI was programmed in LabVIEW and synthesized to ru n on the FPGA.
FPGA ASIC Trend ASIC NRE Parameter FPGA ASIC Clock frequency Power consumption Form factor Reconfiguration Design security Redesign risk (weighted) Time to market NRE Total Cost FPGA vs. ASIC ü ü ü ü ü ü ü ü FPGA Domain ASIC Domain - 11 - 18.05.2012 The Case for FPGAs - FPGA vs. ASIC FPGAs can't beat ASICs when it comes to Low power
Step 1: Replace ASIC RAMs to FPGA RAMs (using CORE Gen. tool) Step 2: ASIC PLLs to FPGA DCM & PLLs (using architecture wizard), also use BUFG/IBUFG for global routing. Step 3: Convert SERDES (Using Chipsync wizard) Step 4: Convert DSP resources to FPGA DSP resources (using FPGA Core gen.)
Plot System Responses . (time-domain response) or Bode plots (frequency-domain response). For 1-DOF PID controller types such as PI, PIDF, and PDF, PID Tuner computes system responses based upon the following single-loop control architecture: For 2-DOF PID controller types such as PI2, PIDF2, and I-PD, PID Tuner computes responses based upon .
typical unit negative feedback control system [4]. PID control theory is widely used in the field of industrial automation control. The basic principle is clear and concise. As a useful complement to PDCA theory, PID control theory has good feasibility.PID control theory uses PID control ideology to supplement and improve the correction
14 2 FPGA Architectures: An Overview Fig. 2.5 Overview of mesh-based FPGA architecture [22] 2.4.1 Island-Style Routing Architecture Figure2.5 shows a traditional island-style FPGA architecture (also termed as mesh-based FPGA architecture). This is the most common
