Lecture 8: ARM Arithmetic And Bitweise Instructions
Lecture 8: ARM Arithmetic and BitweiseInstructionsCSE 30: Computer Organization and Systems ProgrammingWinter 2014Diba MirzaDept. of Computer Science and EngineeringUniversity of California, San Diego
Basic Types of ARM Instructions1.Arithmetic: Only processor and registers involved1.2.2.Data Transfer Instructions: Interacts with memory1.2.3.compute the sum (or difference) of two registers, store theresult in a registermove the contents of one register to anotherload a word from memory into a registerstore the contents of a register into a memory wordControl Transfer Instructions: Change flow of execution1.2.3.jump to another instructionconditional jump (e.g., branch if registeri 0)jump to a subroutine
ARM Addition and Subtraction§ Syntax of Instructions:1 2, 3, 4where:1) instruction by name2) operand getting result (“destination”)3) 1st operand for operation (“source1”)4) 2nd operand for operation (“source2”)§ Syntax is rigid (for the most part):§ § 1 operator, 3 operandsWhy? Keep Hardware simple via regularity
Addition and Subtraction of Integers§ Addition in AssemblyExample:ADD r0,r1,r2 (in ARM)Equivalent to: a b c (in C)where ARM registers r0,r1,r2 are associatedwith C variables a, b, c§ § Subtraction in AssemblyExample:SUB r3, r4, r5 (in ARM)Equivalent to: d e - f (in C)where ARM registers r3,r4,r5 are associatedwith C variables d, e, f§
Setting condition bits§ Simply add an ‘S’ following the arithmetic/logic instructionExample:ADDS r0,r1,r2 (in ARM)This is equivalent to r0 r1 r2 and set thecondition bits for this operation§
What is the min. number of assemblyinstructions needed to perform the following ?a b c d - e;A.B.C.D.Single instructionTwo instructionsThree instructionsFour instructionsAssume the value of each variable is stored in aregister.
What is the min. number of assemblyinstructions needed to perform the following ?a b c d - e;A.B.C.D.Single instructionTwo instructionsThree instructionsFour instructionsAssume the value of each variable is stored in aregister.
Addition and Subtraction of Integers§ § How do the following C statement?a b c d - e;Break into multiple instructions§ § § § § ADD r0, r1, r2ADD r0, r0, r3SUB r0, r0, r4; a b c; a a d; a a - eNotice: A single line of C may break up intoseveral lines of ARM.Notice: Everything after the semicolon oneach line is ignored (comments)
Addition and Subtraction of Integers§ How do we do this?§ § f (g h) - (i j);Use intermediate temporary registerADD r0,r1,r2ADD r5,r3,r4SUB r0,r0,r5; f g h; temp i j; f (g h)-(i j)
Immediates§ § § Immediates are numerical constants.They appear often in code, so there are waysto indicate their existenceAdd Immediate:§ § § § f g 10 (in C)ADD r0,r1,#10 (in ARM)where ARM registers r0,r1 are associatedwith C variables f, gSyntax similar to add instruction, exceptthat last argument is a #number instead of aregister.
Arithmetic operations: Addressing Modes1.Register Direct Addressing: Operand values arein registers:v ADD2.r3, r0, r1; r3 r0 r1Immediate Addressing Mode: Operand value iswithin the instructionv ADDr3, r0, #7; r3 r0 7v The number 7 is stored as part of the instruction3.Register direct with shift or rotate (more nextlecture)v ADD r3, r0, r1, LSL#2; r3 r0 r1 2
What is a likely range for immediates inthe immediate addressing modeA.0 to (232-1)B.0 to 255
What is a likely range for immediates inthe immediate addressing modeA.0 to (232-1)B.0 to 255 Immediates are part of the instruction(which is a total of 32 bits). Number of bitsreserved for representing immediates is 8 bits
Add/Subtract instructions1.2.3.4.5.6.ADD r1, r2, r3;ADC r1, r2, r3;SUB r1, r2,r3;SUBC r1, r2, r3;RSB r1, r2, r3;RSC r1, r2, r3;r1 r2 r3r1 r2 r3 C(arry Flag)r1 r2-r3r1 r2-r3 C -1r1 r3-r2;r1 r3-r2 C -1
Integer Multiplicationv Paperand pencil example (unsigned):Multiplicand1000Multiplier x1001100000000000 100001001000v m bits x n bits m n bit product
Multiplication§ Example:§ § in C: a b * c;in ARM:let b be r2; let c be r3; and let a be r0 and r1 (since it may be up to 64 bits)MUL r0, r2, r3; b*c only 32 bits storedNote: Often, we only care about the lower half of the product.SMULL r0,r1,r2,r3 ; 64 bits in r0:r1
Multiply and Divide§ § There are 2 classes of multiply - producing 32-bit and 64-bit results32-bit versions on an ARM7TDMI will execute in 2 - 5 cycles§ § § ; r0 r1 * r2; r0 (r1 * r2) r364-bit multiply instructions offer both signed and unsigned versions§ For these instruction there are 2 destination registers§ § § MUL r0, r1, r2MLA r0, r1, r2, r3[U S]MULL r4, r5, r2, r3[U S]MLAL r4, r5, r2, r3; r5:r4 r2 * r3; r5:r4 (r2 * r3) r5:r4Most ARM cores do not offer integer divide instructions§ Division operations will be performed by C library routines or inline shifts
Logical Operations operate onA.BitsB.InstructionsC.NumbersD.Strings18
Logical Operations operate onA.BitsB.InstructionsC.NumbersD.Strings19
Logical Operatorsv Basiclogical operators:v ANDv ORv XORv BIC(Bit Clear)v Ingeneral, can define them to accept 2 inputs,but in the case of ARM assembly, both of theseaccept exactly 2 inputs and produce 1 outputv Again,rigid syntax, simpler hardware20
Logical Operatorsv TruthTable: standard table listing all possiblecombinations of inputs and resultant output for eachv Truth Table for AND, OR and XORA AND (NOT B)A0!0!!1!1BA AND B0!0 !!0!1!0!0!1!1!A OR B A XOR B A BIC B0!0!0!0!1!1!1!1!1!0!1!0!21
Bitwise Logic Instruction Syntaxv Syntaxof Instructions:1 2, 3, 4where:1) instruction by name2) operand getting result (“destination”)3) 1st operand for operation (“source1”)4) 2nd operand for operation (“source2”)v Syntaxis rigid (for the most part):v 1operator, 3 operandsv Why? Keep Hardware simple via regularity22
Bitwise Logic Operationsv BitwiseAND in Assemblyv Example:ANDEquivalent to: r0 v Bitwise OR in Assemblyv Example:ORREquivalent to: r3 v Bitwise XOR in Assemblyv Example:EOREquivalent to: r0 v Bitwise Clear in Assemblyv Example:BICEquivalent to: r3 r0,r1,r2 (in ARM)r1 & r2 (in C)r3, r4, r5 (in ARM)r4 r5 (in C)r0,r1,r2 (in ARM)r1 r2 (in C)r3, r4, r5 (in ARM)r4 & (!r5) (in C)23
Bit wise operationsr0: 01101001r1: 11000111ORR r3, r0,r1; r3: 11101111AND r3,r0,r1; r3: 01000001EOR r3,r0,r1; r3: 10101110BIC r3, r0, r1; r3: 0010100024
Uses for Logical Operatorsthat ANDing a bit with 0 produces a 0 at theoutput while ANDing a bit with 1 produces theoriginal bit.v This can be used to create a mask.v Notev Example:mask:!v The1011 0110 1010 0100 0011 1101 1001 10100000 0000 0000 0000 0000 1111 1111 1111result of ANDing these:0000 0000 0000 0000 0000 1101 1001 1010mask last 12 bits!25
Uses for Logical Operatorsnote that ORing a bit with 1produces a 1 at the output while ORing a bitwith 0 produces the original bit.v This can be used to force certain bits of astring to 1s.v Similarly,v Forexample, 0x12345678 OR 0x0000FFFresults in 0x1234FFFF (e.g. the high-order 16bits are untouched, while the low-order 16 bitsare forced to 1s).26
Invert bits 0-2 of xA.x AND 00000111B.x OR 00000111C.x MOVN 00000111D.x XOR 0000011127
Invert bits 0-2 of xA.x AND 00000111B.x OR 00000111C.x MOVN 00000111D.x XOR 0000011128
Uses for Logical Operatorsnote that BICing a bit with 1 resetsthe bit (sets to 0) at the output while BICinga bit with 0 produces the original bit.v This can be used to force certain bits of astring to 0s.v Finally,v Forexample, 0x12345678 OR 0x0000FFFFresults in 0x12340000 (e.g. the high-order 16bits are untouched, while the low-order 16 bitsare forced to 0s).29
Find the 1's complement of xA.x XOR 00000000B.x XOR 11111111C.x XOR 11111110D.x BIC 1111111130
Find the 1's complement of xA.x XOR 00000000B.x XOR 11111111C.x XOR 11111110D.x BIC 1111111131
Assignment Instructionsv Assignmentin Assemblyv Example:MOV r0,r1(in ARM)Equivalent to:a b(in C)where ARM registers r0, r1 are associated with Cvariables a & bv Example:MOV r0,#10Equivalent to: a 10(in ARM)(in C)32
Assignment Instructionsv MVN– Move Negative – moves one’scomplement of the operand into the register.v Assignment in Assemblyv Example:MVN r0,#0(in ARM)Equivalent to:a -1(in C)where ARM registers r0 are associated with Cvariables aSince 0x00000000 0xFFFFFFFF33
Shifts and Rotatesv LSL – logical shift by n bits – multiplication by 2nCv CASR – arithmetic shift by n bits – signed division by 2n v 0LSR – logical shift by n bits – unsigned division by 2n0v CROR – logical rotate by n bits – 32 bit rotate C34
01101001 2A.00011010B.00101001C.01101001D.1010010035
A new instruction HEXSHIFTRIGHT shifts hexnumbers over by a digit to the right.HEXSHIFTRIGHT i times is equivalent toA.Dividing by iB.Dividing by 2iC.Dividing by 16iD.Multiplying by 16i36
A new instruction HEXSHIFTRIGHT shifts hexnumbers over by a digit to the right.HEXSHIFTRIGHT i times is equivalent toA.Dividing by iB.Dividing by 2iC.Dividing by 16iD.Multiplying by 16i37
Ways of specifying operand 2v OpcodeDestination, Operand 1, Operand 2v Registerv With1)2)Direct:ADD r0, r1, r2;shift/rotate:Shift value: 5 bit immediate (unsigned integer)ADD r0, r1, r2, LSL #2; r0 r1 r2 2; r0 r1 4*r2Shift value: Lower Byte of register:ADD r0, r1, r2, LSL r3; r0 r1 r2 r3; r0 r1 (2 r3)*r2v Immediate:ADD r0, r1, #0xFFv Withrotate-rightADD r0,r1, #0xFF, 28Rotate value must be even: #0xFF ROR 28 generates:0XFF0000000038
Ways of specifying operand 2v OpcodeDestination, Operand 1, Operand 2v Registerv With1)2)Direct:ADD r0, r1, r2;shift/rotate:Shift value: 5 bit immediate (unsigned integer)ADD r0, r1, r2, LSL #2; r0 r1 r2 2; r0 r1 4*r2Shift value: Lower Byte of register:ADD r0, r1, r2, LSL r3; r0 r1 r2 r3; r0 r1 (2 r3)*r2v Immediate addressing:v 8 bit immediate valuev With rotate-rightADD r0, r1, #0xFFADD r0,r1, #0xFF, 8Rotate value must be even#0xFF ROR 8 generates: 0XFF000000§ Maximum rotate value is 30§ 39
Reasons for constraints on Immediate Addressingv Thedata processing instruction format has 12 bitsavailable for operand2118 7rotx20immed 8ShifterROR0xFF000000MOV r0, #0xFF,8Immed 8 0xFF, rot 4v 4bit rotate value (0-15) is multiplied by two togive range 0-30 in steps of 2v Ruleto remember is “8-bits rotated right by aneven number of bit positions”40
Generating Constants using immediatesRotate 0000xxxxxxxx0-2550-0xFFRight, 30 bits ht, 28 bits ight, 26 bits C0 Right, 8 40x1000000-0xFF000000Right, 6 bitsxxxxxx0000000000000000000000xx--Right, 4 bitsxxxx0000000000000000000000xxxx--Right, 2 bitsxx0000000000000000000000xxxxxx--This scheme can generate a lot, but not all, constants.v Others must be done using literal pools (more on that later)v 41
Implementation in h/w using a Barrel ShifterOperand 1 Operand 2BarrelShifterALUResult1. Register, optionally with shift operationv Shift value can either be:v 5 bit unsigned integerv Specified in bottom byte ofanother register.v Used for multiplication by constant2. Immediate valuev 8 bit number, with a range of 0-255.v Rotated right through evennumber of positionsv Allows increased range of 32-bitconstants to be loaded directly intoregisters42
Shifts and Rotatesv Shiftingin AssemblyExamples:MOVMOVv Rotatingr4, r6, LSL #4 ; r4 r6 4r4, r6, LSR #8 ; r4 r6 8in AssemblyExamples:MOVr4, r6, ROR #12; r4 r6 rotated right 12 bits; r4 r6 rotated left by 20 bits (32 -12)Therefore no need for rotate left.43
Variable Shifts and Rotatesv Alsopossible to shift by the value of a registerv Examples:MOVr4, r6, LSL r3; r4 r6 value specified in r3MOVv Rotatingr4, r6, LSR #8 ; r4 r6 8in Assemblyv Examples:MOVr4, r6, ROR r3; r4 r6 rotated right by value specifiedin r344
Constant Multiplicationv Constant multiplication is often faster using shifts andadditionsMUL r0, r2, #8 ; r0 r2 * 8Is the same as:MOV r0, r2, LSL #3 ; r0 r2 * 8v Constant divisionMOV r1, r3, ASR #7 ; r1 r3/128Treats the register value like signed values (shifts in MSB).Vs.MOV r1, r3, LSR #7 ; r1 r3/128Treats register value like unsigned values (shifts in 0)45
Constant Multiplicationv Constant multiplication with subtractionsMUL r0, r2, #7 ; r0 r2 * 7Is the same as:RSB r0, r2, r2, LSL #3 ; r0 r2 * 7; r0 -r2 8*r2 7*r2RSB r0, r1, r2 is the same asSUB r0, r2, r1 ; r0 r1 – r2Multiply by 35:ADDr9,r8,r8,LSL #2RSBr10,r9,r9,LSL #3; r9 r8*5; r10 r9*7Why have RSB? B/C only the second source operand can be shifted. 46
Conclusionv Instructionsso far:v Previously:ADD, SUB, MUL, MLA, [U S]MULL, [U S]MLALv New instructions:RSBAND, ORR, EOR, BICMOV, MVNLSL, LSR, ASR, RORv Shiftingcan only be done on the second source operandv Constant multiplications possible using shifts andaddition/subtractions47
Comments in Assembly§ § Another way to make your code morereadable: comments!Semicolon (;) is used for ARM comments§ § anything from semicolon to end of line is acomment and will be ignoredNote: Different from C§ C comments have format /* comment */, sothey can span many lines
Conclusion§ In ARM Assembly Language:§ § § § § Instructions so far:§ § Registers replace C variablesOne Instruction (simple operation) per lineSimpler is BetterSmaller is FasterADD, SUB, MUL, MULA, [U S]MULL, [U S]MLALRegisters:§ Places for general variables: r0-r12
Addition in Assembly ! Example: ADD r0,r1,r2 (in ARM) Equivalent to: a b c (in C) where ARM registers r0,r1,r2 are associated with C variables a, b, c! Subtraction in Assembly ! Example: SUB r3, r4, r5 (in ARM) Equiv
3.2 Arithmetic series: the sum of an arithmetic sequence Analysis, interpretation and prediction where a model is not perfectly arithmetic in real life. 7C 7D Arithmetic Sequence Arithmetic Series 6C 6D Arithmetic sequences Arithmetic series 3.1 3.2 Arithmetic sequence Arithmetic s
Introduction of Chemical Reaction Engineering Introduction about Chemical Engineering 0:31:15 0:31:09. Lecture 14 Lecture 15 Lecture 16 Lecture 17 Lecture 18 Lecture 19 Lecture 20 Lecture 21 Lecture 22 Lecture 23 Lecture 24 Lecture 25 Lecture 26 Lecture 27 Lecture 28 Lecture
arithmetic sequence finds the nth term of an arithmetic sequence lists down the first few terms of an arithmetic sequence given the general term and vice-versa solves word problems involving arithmetic mean applies the concepts of mean and the nth term of an arithmetic sequence
Arithmetic Series: A series whose terms form an arithmetic sequence. 11 4 Arithmetic Series 7 April 27, 2009 Apr 21 4:18 PM. 11 4 Arithmetic Series 8 April 27, 2009 Apr 21 4:19 PM. 11 4 Arithmetic Series . Homework: page 622 (2 32 even, 37, 40) Title: 11-4 Arithmetic Series Subject: SMART Board Interactive Whiteboard Notes
arithmetic sequence are called arithmetic means. In the sequence below, 38 and 49 are the arithmetic means between 27 and 60. 5, 16, 27, 38 , 49 , 60 760 Chapter 12 Sequences and Series The n th term of an arithmetic sequence with first term a 1 and common difference d is given by a n a 1 (n 1) d . The n th Term of an Arithmetic Sequence .
2.2 Affine Arithmetic Themodeling tool in thispaper is a ne arithmetic, which is an e cient and recent variant of range arithmetic. In this section, we begin with introducing its predecessor, inter-val arithmetic, and then emphasize the advantage of a ne arithmetic. Interval arithmetic (IA), also known as interval analysis,
Trx arm workouts pdf. Trx band arm workout. Trx full arm workout. Trx chest and arm workout. Trx shoulder and arm workout. Trx arm workout video. Trx arm workout youtube. Whether you're looking for TRX exercises for beginners or a more advanced TRX workout plan, these moves have something for everyone. "The pike is a personal favorite of mine!"
Reference Material §ARM ARM(“Architecture Reference Manual ”) §ARM DDI 0100E covers v5TE DSP extensions §Can be purchased from booksellers - ISBN 0-201-737191 (Addison-Wesley) §Available for download from ARM’swebsite §ARM v7-M ARM available for download from ARM’swebsite §Conta
