STM32 GPIO Configuration For Hardware Settings And Low .

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AN4899Application noteSTM32 GPIO configuration for hardware settingsand low-power consumptionIntroductionThe STM32 microcontroller general-purpose input/output pin (GPIO) provides many ways tointerface with external circuits within an application framework. This application noteprovides basic information about GPIO configurations as well as guidelines for hardwareand software developers to optimize the power performance of their STM32 32-bit ARMCortex MCUs using the GPIO pin.This application note must be used in conjunction with the related STM32 reference manualand datasheet available at www.st.com.September 2017DocID029601 Rev 11/31www.st.com1

ContentsAN4899Contents1Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.2Register abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843.1GPIO abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.2GPIO equivalent schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3GPIO modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.24.32/31Input mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3.2Output mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3.3Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3.4Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12GPIO electrical characteristics and definitions . . . . . . . . . . . . . . . . . . 134.153.3.1GPIO general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1.1Pad leakage current (Ilkg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1.2Injected current (IINJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1.3GPIO current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1.4Voltage output and current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1.5Pull-up calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Three-volt tolerant and five-volt tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2.1Three-volt tolerant GPIO (TT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2.2Five-volt tolerant GPIO (FT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Five-volt tolerant application examples . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.1White LED drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.2Triac drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.3I2C application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.3.4UART application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3.5USB VBUS example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3.6I/O usage for the five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . 21GPIO hardware guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23DocID029601 Rev 1

AN48996Contents5.1Avoid floating unused pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2Cross-voltage domains leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.3Voltage protection when no VDD is supplied . . . . . . . . . . . . . . . . . . . . . . 245.4Open-drain output with no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.5Using the MCO clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.6Debug pins have PU or PD by default . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.7NRST pin cannot be used as enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.8VBAT GPIO has limited current strength . . . . . . . . . . . . . . . . . . . . . . . . . 265.9BOOT0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26GPIO software guidelines for power optimization . . . . . . . . . . . . . . . . 276.1Configure unused GPIO input as analog input . . . . . . . . . . . . . . . . . . . . . 276.2Adapt GPIO speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.3Disable GPIO register clock when not in use . . . . . . . . . . . . . . . . . . . . . . 276.4Configure GPIO when entering low-power modes . . . . . . . . . . . . . . . . . . 276.5Shutdown exit mode(STM32L4 Series and STM32L4 Series only) . . . . . . . . . . . . . . . . . . . . 277GPIO selection guide and configuration . . . . . . . . . . . . . . . . . . . . . . . . 288Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30DocID029601 Rev 13/313

List of tablesAN4899List of tablesTable 1.Table 2.4/31List of GPIO structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30DocID029601 Rev 1

AN4899List of figuresList of figuresFigure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.Figure 10.Figure 11.Figure 12.Figure 13.Figure 14.Figure 15.Figure 16.Figure 17.Figure 18.Figure 19.Three-volt compliant GPIO structure (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Three-volt or five-volt tolerant GPIO structure (TT or FT). . . . . . . . . . . . . . . . . . . . . . . . . . 10Output buffer and current flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Logical level compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15STM32 current flow according to output voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Example of white LED drive connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Example of triac drive connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Example of I2C connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Example of 5 V to 3.3 V power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Example of UART connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Example of USB VBUS connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Example of VBUS to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Example of five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Workaround example for five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Multi voltage leakage example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Voltage protection when VDD is not supplied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Open-drain output with no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25GPIO configuration flowchart (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28GPIO configuration flowchart (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29DocID029601 Rev 15/315

Documentation conventionsAN48991Documentation conventions1.1GlossaryThis section defines the main acronyms and abbreviations used in this document.6/31AMR:absolute maximum ratingGPIO:general-purpose input ull-downOD:open-drainAF:alternate functionVIH:the minimum voltage level that is interpreted as a logical 1 by a digital inputVIL:the maximum voltage level that is interpreted as a logical 0 by a digital inputVOH:the guaranteed minimum voltage level that is provided by a digital output set tothe logical 1 valueVOL:the guaranteed maximum voltage level that is provided by a digital output set tothe logical 0 valueVDD:external power supply for the I/OsVDDIO2:external power supply for the I/Os, independent from the VDD voltageVDDA:external power supply for analogVSS:groundIIH:input current when input is 1IIL:input current when input is 0IOH:output current when output is 1IOL:output current when output is 0Ilkg:leakage currentIINJ:injected currentDocID029601 Rev 1

AN48991.2GPIO main featuresRegister abbreviationsThe following abbreviations are used in register descriptions (x A to H):2GPIOx MODER:GPIO port mode registerGPIOx OTYPER:GPIO output type registerGPIOx OSPEEDR:GPIO output speed registerGPIOx PUPDR:GPIO port pull-up / pull-down registerGPIOx IDR:GPIO port input data registerGPIOx ODR:GPIO port output data registerGPIOx BSRR:GPIIO port it set / reset registerGPIOx LCKR:GPIO port configuration lock registerGPIOx AFRL:GPIO alternate function low registerGPIOx AFRH:GPIO alternate function high registerGPIOx ASCR:GPIO port analog switch control registerGPIO main featuresSTM32 GPIO exhibits the following features: Output states: push-pull, or open drain pull-up / pull-down according toGPIOx MODER, GPIOx OTYPER, and GPIOx PUPDR registers settings Output data from output data register GPIOx ODR or peripheral (alternate functionoutput) Speed selection for each I/O (GPIOx OSPEEDR) Input states: floating, pull-up / pull-down, analog according to GPIOx MODER,GPIOx PUPDR and GPIOx ASCR registers settings Input data to input data register (GPIOx IDR) or peripheral (alternate function input) Bit set and reset register (GPIOx BSRR) for bitwise write access to GPIOx ODR Locking mechanism (GPIOx LCKR) provided to freeze the I/O port configurations Analog function selection registers (GPIOx MODER and GPIOx ASCR) Alternate function selection registers (GPIOx MODER, GPIOx AFRL, andGPIOx AFRH) Fast toggle capable of changing every two clock cycles Highly flexible pin multiplexing allowing the use of I/O pins as GPIO or as one ofseveral peripheral functionsDocID029601 Rev 17/3130

GPIO functional description3AN4899GPIO functional descriptionSTM32 GPIO can be used in a variety of configurations. Each GPIO pin can be individuallyconfigured by software in any of the following modes:3.1 Input floating Input pull-up Input-pull-down Analog Output open-drain with pull-up or pull-down capability Output push-pull with pull-up or pull-down capability Alternate function push-pull with pull-up or pull-down capability Alternate function open-drain with pull-up or pull-down capabilityGPIO abbreviationsSeveral GPIO structures are available across the range of STM32 devices. Each structureis associated with a list of options.Table 1 summarizes the GPIO definitions and abbreviations applicable to STM32 productsTable 1. List of GPIO structuresNameAbbreviationPin TypeSSupply pinIInput only pinI/OFTInput / output pin(1)TT(1)TCI/O structureThree-volt tolerant I/O pinDedicated boot pinRSTAlternate functionsFive-volt tolerant I/O pinThree-volt capable I/O pin (Standard 3.3 V I/O)BPin functionsDefinitionBidirectional reset pin with embedded weak pull-up resistorFunctions selected through GPIOx AFR registersAdditional functions Functions directly selected and enabled through peripheral registers1. FT and TT I/Os have options depending on the device. The user must refer to the datasheet for their definitions.As an example, the following description refers to a GPIO in a STM32 datasheet:PB1 I/O FT means:–pin PB1 I/O: port B bit 1 input / output–FT: five-volt tolerantBefore starting a board design, it is important to refer to the datasheet of the STM32 productor to the STM32CubeMX tool to check for GPIO availability in coherence with the targetapplication.Refer to the section about software development tools at www.st.com/stm32.8/31DocID029601 Rev 1

AN48993.2GPIO functional descriptionGPIO equivalent schematicsSTM32 products integrate three main GPIO basic structures:Note: Three-volt compliant (abbreviated as TC).The equivalent GPIO diagram structure is given in Figure 1. Three-volt tolerant (abbreviated as TT). Five-volt tolerant (abbreviated as FT)The equivalent GPIO diagram structure for TT or FT is given in Figure 2.In Figure 1 and Figure 2, the analog switch in the dotted square is optional. Its presencedepends on the STM32 product considered. Refer to the product datasheet for details.In Figure 1 and Figure 2, the VDD supply may refer to VDD or VDDIO2 according to theSTM32 product considered. Refer to the product datasheet for details.Figure 1. Three-volt compliant GPIO structure (TC) QDORJ9'' QDORJRSWLRQ3DUDVLWLF GLRGHDQG UHVLVWRU QDORJ ,3 QDORJ VZLWFK9''RQ RII OWHUQDWH IXQFWLRQ LQSXW9''538,QSXW GDWDUHJLVWHU, 2 SLQ,QSXW EXIIHU9''2XWSXW GDWDUHJLVWHU(6'SURWHFWLRQ30262XWSXWFRQWURO1026 OWHUQDWH IXQFWLRQ RXWSXW'LJLWDO53'RQ RII2XSXW EXIIHU96696696696606Y 9 Note:The parasitic diode in the analog domain is connected to VDDA and cannot be used as aprotection diode.The voltage level called VDD FT in some datasheets and reference manuals is inside theESD protection block.DocID029601 Rev 19/3130

GPIO functional descriptionAN4899Figure 2. Three-volt or five-volt tolerant GPIO structure (TT or FT) QDORJ9'' QDORJRSWLRQ3DUDVLWLF GLRGHDQG UHVLVWRU QDORJ ,3 QDORJ VZLWFK9''RQ RII OWHUQDWH IXQFWLRQ LQSXW538,QSXW GDWDUHJLVWHU, 2 SLQ,QSXW EXIIHU9''2XWSXW GDWDUHJLVWHU(6'SURWHFWLRQ30262XWSXWFRQWURO1026 OWHUQDWH IXQFWLRQ RXWSXW9662XSXW EXIIHU'LJLWDO53'RQ RII96696696606Y 9 Note:The parasitic diode in the analog domain is connected to VDDA and cannot be used as aprotection diode.The voltage level called VDD FT in some datasheets and reference manuals is inside theESD protection block.When the analog option is selected, the FT I/O is not five-volt tolerant anymore since the pinis supplied with VDDA.Caution:A TT or FT GPIO pin has no internal protection diode connected to supply (VDD). There isno physical limitation against over-voltage. Therefore, for applications requiring a limitedvoltage threshold, it is recommended to connect an external diode to VDD.3.3GPIO modes descriptionThis section describes the possible GPIO pin configurations available in STM32 devices.3.3.1Input mode configurationWhen a STM32 device I/O pin is configured as input, one of three options must be selected:10/31 Input with internal pull-up. Pull-up resistors are used in STM32 devices to ensure awell-defined logical level in case of floating input signal. Depending on applicationrequirements, an external pull-up can be used instead. Input with internal pull-down. Pull-down resistors are used in STM32 devices to ensurea well-defined logical level in case of floating input signal. Depending on applicationrequirements, an external pull-down can be used instead. Floating input. Signal level follows the external signal. When no external signal ispresent, the Schmitt trigger randomly toggles between the logical levels induced by theexternal noise. This increases the overall consumption.DocID029601 Rev 1

AN4899GPIO functional descriptionProgrammed as input, an I/O port exhibits the following characteristics:3.3.2 The output buffer is disabled The Schmitt trigger input is activated The pull-up or pull-down resistors are activated depending on the value in theGPIOx PUPDR register The data present on the I/O pin is sampled into the input data register at each AHBclock cycle The I/O state is obtained by reading the GPIOx IDR input data registerOutput mode configurationWhen a STM32 device I/O pin is configured as output, one of two options must be selected: Push-pull output mode:The push-pull output actually uses two transistors: one PMOS and one NMOS. Eachtransistor is ON to drive the output to the appropriate level:–The top transistor (PMOS) is ON when the output has to drive HIGH state–The bottom transistor (NMOS) is ON when the output has to drive a LOW stateThe control of the two transistors is done through the GPIO port output typeregister (GPIOx OTYPER).Writing the related bit of the output register (GPIOx ODR) to 0 activates theNMOS transistor to force the I/O pin to ground.Writing the related bit of the output register (GPIOx ODR) to 1 activates thePMOS transistor to force the I/O pin to VDD. Open-drain output mode:Open-drain output mode does not use the PMOS transistor and a pull-up resistor isrequired.When the output has to go high, the NMOS transistor must be turned off, pulling theline high only by the pull-up resistor. This pull-up resistor could be internal with a typicalvalue of 40 kOhm and activated through GPIO port pull-up / pull-down register(GPIOx PUPDR).Note:It is important to note that it is not possible to activate pull-up and pull-down at the sametime on the same I/O pin.It is also possible to use an external pull-up or pull-down resistor instead of the internalresistor. In this case, the value must be adapted to be compliant with the GPIO outputvoltage and current characteristics.Programmed as output, an I/O port exhibits the following characteristics: The output buffer can be configured in open-drain or push-pull mode The Schmitt trigger input is activated The internal pull-up and pull-down resistors are activated depending on the value in theGPIOx PUPDR register. The written value into the output data register GPIOx ODR sets the I/O pin state The written data on GPIOx ODR can be read from GPIOx IDR register that is updatedevery AHB clock cycleOpen-drain output is often used to control devices which operate at a different voltagesupply than the STM32. Open-drain mode is also used to drive one or several I2C deviceswhen specific pull-up resistors are required.DocID029601 Rev 111/3130

GPIO functional description3.3.3AN4899Alternate functionsOn some STM32 GPIO pins, the user has the possibility to select alternate functionsinputs / outputs. Each pin is multiplexed with up to sixteen peripheral functions such ascommunication interfaces (SPI, UART, I2C, USB, CAN, LCD and others), timers, debuginterface, and others.The alternate function of the selected pin is configured through two registers: GPIOx AFRL (for pin 0 to 7) GPIOx AFRH (for pin 8 to 15)To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.When the I/O port is programmed as alternate function mode: The output buffer can be configured in open-drain or push-pull mode The output buffer is driven by the signals coming from the peripheral (transmitterenable and data) The Schmitt trigger input is activated The pull-up and pull-down resistors activations depend on the value in the registerGPIOx PUPDRThe data present on the I/O pin are sampled into the input data register at each AHB clockcycle.A read access to the input data register provides the I/O state.Alternate functions details are provided in the datasheet and the reference manual of theproduct.3.3.4Analog configurationFew STM32 GPIO pins can be configured in analog mode which allows the use of ADC,DAC, OPAMP, and COMP internal peripherals. To use a GPIO pin in analog mode

and software developers to optimize the power performance of their STM32 32-bit ARM Cortex MCUs using the GPIO pin. This application note must be used in conjunction with the related STM32 reference manual and datas

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