Low Power System-on-Chip Design Advanced Power

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1Low Power System-on-Chip DesignAdvanced Power Modeling Supportin today‟s EDA FlowsPetri Solanti, CAESynopsys Finland OyThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636Advanced Power Modeling Support in today‟s EDA Flows23.1.2009

2Part 1 : Power Analysis with Virtual Platforms What is a Virtual Platform Power Modeling & Estimation goals Power Modeling Support Clock Modeling Voltage Modeling Power Estimation DashboardsThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636Advanced Power Modeling Support in today‟s EDA Flows23.1.2009

What is a Virtual Platform? Fully functional software model ofcomplete systems SoC, board, I/O, user interface Executes unmodified productioncode Drivers, OS, and applications Runs close to real time Boots OS in seconds Highest debugging efficiencythrough full system visibility andcontrol Supports multi-core SoCs debugThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Virtual Platform – Closer LookUser InterfaceEmulationVirtual I/OVirtual I/ O & User InterfaceHigh-Level, High-speedC/C /SystemCModelsSystem IOFast InstructionAccurate SimulatorM emBoard-levelSystem-on-ChipCPUFunc TLM BusFunc TLM BusFunctionalPeripheralsSimulation InfrastructureTransaction-levelGraphicalThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInterfacesPeripheral ModelsInstitute of Digital and Computer Systems / TKT-9636

Power Modeling & Estimation Goals Increase visibility into global system state & individual power/clockdomains Architectural power trade-offs Explore performance vs. power trade-offs Test drive new power scheme with “system software” load Power-related software development1. Perform software power optimizations by providing (relative) power consumptionestimations2. Enable development of power management software3. Provide insight into system power consumption, when running actual systemsoftwareThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Modeling Support The following power support is added to a TLM platform:1. Power management modeling1. Clock modeling – gating, scaling freq(t), 2. Voltage distribution - power domains, scaling V(t) , 3. Power state control – power state sequencing (power down,retention, )2. Power estimation equations – evaluated at run-time3. Dashboards – clocks, state, voltage, power Applies both to PV & PVT level modeling PV Instantaneous power consumption, at each point in timePVT Supports trade-off of performance vs. power Graphs: Power(t) & Energy(t) Improved accuracy for accounting for (memory) transactions powercontributionThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

System-level Power ExplorationSW-Driven Power Analysis & OptimizationStart with functionalaccurate TLM SystemModelRun System SoftwareAnalyze Power ResultsCameraUSBDesignWare SpecifyVirtual n Power ConsumptionsSystemI/OP(f,V,mode)timeCPU(s)Add ClockDistributionTLM BusInstructionSet SimulatorI MemCtrlP(f,V,mode)MemDevice EnergyP(f,V,mode)P(f,V,mode)D TLM tModulePowerMgmtICtimePower EventsP(f,V,mode)VoltageClocksFlashMemoryAdd PowerManagementAdd Power Complete imize SystemThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Clock ModelingClockControllerMaster2Master1Signal is used to transmit value of clockfrequencyfrom controller to peripheral;TLM Busdoes not model actual clock waveformCPU(s)Instr uctionSet SimulatorPeriphPeriph Functional clock modeling Models functional operation of the clock controller, including: Clock distribution Control over peripheral clock gating Registers, to model software control over clock frequenciesThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Voltage & Power State Control Modeling Functional models of: On-chip Power Manager (SoC) Control of (internal) voltagedistribution & domains State control & sequencing Power management chip (PMIC) Voltage scaling of SoC SoC I2C control interface,power sequencing, LDO regulatorscontrol, DC/DC convertors, VDD (SoC voltage scaling)Voltage DomainsPRCMI2CLDOsVDD USBVDD RFI2CVoltageDistributionPMSequencerSystem-on-Chip (SoC)Power Management ChipThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation - ConceptsParametrizable power model, consisting of:1. Component power characteristics2. Component power calc. equations3. Power accumulatorPowerManagerMaster2Master1CPU(s)TLM BusInstr uctionSet SimulatorPV / PVTModelVoltageFrequencyPower StatePowerAccumulatorPower eventLogging (file)Power DashboardPower EstimationEquationPower request /response APIsPowerAccumulatorThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation – Component Characterization Power parameters Components are characterized by a set of representative power parameters(„kernels‟) Used in power equations to calculate power Flexible to support specific component characteristics Interactively changeable by user Source Power consumption numbers are delivered by semiconductor company Based on (1) budget planning, (2) estimations, (3) measurementsThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation – Component Characterization Examples: OMAP2420 (PV model)1.CPUExample – PRCM (OMAP2420) Power active (mA / MHz) Power dormant (mA) Power inactive (mA) Power shutdown (mA)2.Peripherals: Power clock off (mA) Power idle (mA / MHz) Power typical (mA / MHz) Power maximum (mA / MHz)3.On-chip Memories (RAM / ROM) Power clock off (mA) Power idle (mA / MHz) Power read transaction (mA / MHz) Power write transaction (mA / MHz)This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation System power estimations expressions, contain:1.2.3.4.Component power characteristicsPower state of APLLs & DPLLs { off, on }Power state of domain { off, ret, on }Voltage applied (to domain) At run-time power estimation expressions areevaluated on the fly, as triggered by user requests Complements functional component modelLeverage power state & frequency modeling of func. componentmodelExpressed in C code (Magic-C or C )This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation (cont‟d) Expressions can be linear, or more complex,depending on: Component typeData / charatistics which can be measured / estimated Fixed modeling APIs for voltage, frequency & powerstate updates, and reporting to accumulatorThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation - ExampleARM1136 (OMAP2420)ARM MPU PowerEstimation ComponentMPU Voltage (Volt)Powerupdate requestPRCMPower updateresponseMPU Clock(frequency (MHz))MPU Power State(on, off, )Power ParametersMagic-C Power ModelThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Estimation – PVT Platform Example– 1st order power modelPenalty for each bustransaction(D transaction (length))Fixed powerf(V,f,st)Fixed powerf(V,f,st)Penalty whenCache miss(Dcache iss)Penalty for each busPower(t)transaction(D transaction (length))CameraUSBSystemI/OSystemI/OtimeCPU(s)TLM BusEnergy(t)MemCtrlMemtimeInstr uctionSet SimulatorI D TLM BusSlavePeriphSlavePeriphPenalty for each bustransaction(D sys memory (length))APLLDPLLPower PMICFixed powerf(freq,St)System/ DevicePlatform Analyzer ** Under developmentThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Dashboards OverviewOn-chip Power Reset ControllerClock DashboardVoltage MonitorPower DashboardSoC Voltage DashboardThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power Analysis View ExampleThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

19Part 2 : UPF Language in Design Flows UPF Target Design Styles UPF Conceptual model Synopsys UPF Flows Multi-Voltage Rule Checks Multi-Voltage Simulation Flow Logic Synthesis Design for Testing Flow Multi-Voltage Place & Route FlowThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636Advanced Power Modeling Support in today‟s EDA Flows23.1.2009

UPF Targets Design Styles usingAdvanced Power Management Techniques Mainstream LatchClock Leakage CurrentClock GatingLow VTHNominal VTHHigh VTHDelayAdvanced TechniquesOFF0.9V0.7VOFF0.9V0.9V0.9VMulti-Voltage (MV)0.9VMTCMOS powergating (shut down)0.9V0.7V0.9VMV with powergatingPWRCTRL0.7V0.7 – 0.9VOFFDynamic VoltageFrequency Scaling(DVFS)This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-96360.9V

UPF Conceptual Model Overlay power information on top of the designPower Domain 1Power Domain 3PS 3PS 1PS 2Power Domain 2This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Synopsys UPF VCS MVSIMMVRCDesign CompilerPower CompilerGateUPF’RefPrimeTimePrimeTime PXFormalityImplIC CompilerPrimeTimePrimeTime PXGateUPF”VCS MVSIMMVRCRefFormalityPG NetlistImplPrimeRailThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Multi-Voltage Rule Checking using MVRCImplementationRTLUPFDesign CompilerPower CompilerStaticFunctionalVerificationMVRC:RTL ChecksGateUPF’IC CompilerGateUPF’’MVRC:Netlist ChecksPGNetlistMVRC:Final SignoffThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

MVRCStructural ChecksPMIC/PMUChecks protectionlogic againstISO-EnableDomain 1ON(1.2V)/OFFIsolationDomain 2Domain 3ON (1.2V)0.9-1.2 Missing cellRedundant cellIncorrect cell typeIncorrect power domainIncorrect isolation polarityIncorrect iso-enableLevel ShiftersDomain1 Domain2 ff0.9V1.2VStructural checks performed usingsupplied MV state tableThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

MVRCArchitectural ChecksProcessorControlMemory Architecture checks verify thatisolation / sleep control signals aregenerated from the proper domain ISO Control is driven during Mode2,but in Mode3 it becomes HighZIO ControlRTC(Battery)PowerManagementISO ControlDomain1Domain 2Domain 3Domain 3Off0.9VOff1.2VThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

MVRCArchitectural Checks (2)Always-ON BlockON/OFFBlock Non-MV aware DFT and CTS tools canplace buffers into an incorrect domain Structurally correct, but may lead tofunctional problems Can be caught with test vectors, butCLKGenMVRC can catch without vectorsISO ControlIsolation gateon clock pathThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

MVSIM FlowUPFTestbenchRTL/NetlistMVCMPAPDBMVDBGENVCS MVSIMMulti-VoltageVCD/FSDBThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Multi-voltage Simulation Steps mvcmp -f simulation file listmvcmp -upf tb ChipTop .upfmvdbgen -top tb/usr/bin/gmake -f Makefile.ev all TOOL vcs simulation file list consists of RTL verilog filesand testbench files The testbench needs to be made power aware. This isdone by creating a power domain for the testbench. Alsothe power supply nets defined in the design need to bepropagated up into the testbench, so that the testbenchcan control them. This is done with a testbench level UPF– tb ChipTop .upf mvdbgen is run in testbench moduleThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Power-down and Power-up Sequencesimulation ExampleGPRS registerloadedSave assertedfor retentionGPRS wake upISO signalassertedRestore signalassertedGPRS outputDATA clampedto 1GPRS shutdownsignal assertedRegister valuesrestoredThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Logic Synthesis compile( ultra) recognizes multiple operatingvoltages and automatically synthesizes logic compile( ultra) works with special cells Maps isolation cells and retention registers based on directivesHooks up control signals of retention registersPerforms always on synthesisOptimizes level shifters Automatic insertion of level shifter cells Sizing of level shifters and isolation cells remapping from ISO/LS to ELS All multi-voltage features are available in DesignCompiler Topographical mode as wellThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Always-on SynthesisChipTopVDDVDDGVDD1.0VVDDBAOgprs eVSSLibrary cellmarked asAlways-Onisolate ctrlretnPwrCtrl Mark lib cells to be used as AO AO anchor pins (ISO, ELS,Switch, Ret control pins) areautomatically inferred from PGpin library Use get always on logicto retrieve AO nets and cells To enable AO synthesisset enable ao synthesistrue compile/place optThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Overview of DFT support in UPF mode All DFT MV features in non-UPF mode are available inUPF mode DFT MAX in UPF mode is easier to use vs. non-UPFmode Automatic isolation and enable-level-shifter cell insertion as part ofinsert dft Correct handling of MV cell locationThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

DFT flows supported in UPF mode Standard scan Includes AutoFix, observe point insertion, user-defined test pointinsertion Multiplexed flip-flop scan style only Adaptive scan Default and High X-tolerance Multiplexed flip-flop scan style onlyThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Multi-Voltage-Aware DFT By default, scan stitching does not mix scan cells between power domains To allow mixing of scan-chainsset scan configuration –power domain mixing trueset scan configuration –voltage mixing true1.1V0.9V0.7VPD topPD1PD2voltage mixing falsepower domain mixing false1.1V0.9V0.7VPD topPD1PD2voltage mixing truepower domain mixing trueThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

IC Compiler UPF flowDesign SetupDesign Planningplace optclock opt Read ddc from DC/DCT Read TDF IO/pin constraints Timing constraints are passed throughddc UPF power intent is passed throughddc Same UPF subset is supported in DCand ICC Most of special cells (LS, ISO, ELS,RR) are inserted in DC andmaintained/optimized in ICCroute optThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Design PlanningVoltage Area Creation Create Voltage area for eachpower domain Rectilinear shapes are allowed Physically nested voltage areassupported## CREATE VA FOR EACH PDcreate voltage area \-power domain MULT \-coord { 40 40 60 60 }This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Design PlanningPG Pin HookupPN1 (switch input) PG pins of standard cells hookedPN2(switch output,primary)up to PG nets automatically PG connections are derived from PG pin syntax in the library Scoped and mapped power netP1UPF objectsG1 Tie-off nets are also hooked up tocorrect PG net Checks for any PG connectionVSSderive pg connectioncheck mv design –power netsviolations connect pg nets isrecommended for physical onlycellsThis material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Systems / TKT-9636

Switch Cell Placementadd header footer cell array-lib cell "mult sw“-voltage area MULT-design Multiplier-x increment 63-y increment 8This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibitedInstitute of Digital and Computer Sy

Low Power System-on-Chip Design Advanced Power Modeling Support in today‟s EDA Flows Petri Solanti, CAE Synopsys Finland Oy 1 Advanced Power Modeling Support in today‟s EDA Flows 23.1.2009. Institute of Digital and Computer Systems / TKT-9636 This material is property of Synopsys Inc.

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