0 PLBV46 Master Burst (v1.01a)
0PLBV46 Master Burst (v1.01a)DS565 December 14, 20100Product Specification0IntroductionLogiCORE IP Facts TableThe PLBV46 Master Burst is a continuation of the Xilinxfamily of IBM CoreConnect compatible LogiCOREproducts. It provides a bi-directional interface betweena User IP core and the PLB v4.6 bus standard. Thisversion of the PLBV46 Master Burst has been designedfor PLBV46 Master operations consisting of single databeat read or write transfers and Fixed Length BurstTransfers of 2 to 16 data beats.Supported UserInterfacesPLBV46, LocalLinkWindows XP Professional 32-Bit/64-Bit, WindowsVista Business 32-Bit/64-Bit, Red Hat EnterpriseLinux WS v4.0 32-bit/64-bit, Red Hat EnterpriseDesktop v5.0 32-bit/64-bit (with WorkstationOption), SUSE Linux Enterprise (SLE) desktop andserver v10.1 32-bit/64-bitResources Supports Single Beat Read and Write data transfersup to the IPIC data width Virtex -6, Virtex-5, Virtex-4, Spartan -6,Spartan-3E, Automotive Spartan-3E, Spartan-3,Automotive Spartan-3, Spartan-3A, AutomotiveSpartan-3A, Spartan-3A DSP, AutomotiveSpartan-3A DSPCompatible with IBM CoreConnect 32, 64 and128-bit PLB Parameterizable data width of Client IP Interface(IPIC) to 32, 64, or 128 bits SupportedDevice FamilySupportedOperatingSystemsFeatures Core SpecificsAutomatic Conversion Cycle support forsingle data beat transfers to/from narrowerPLB Slave devicesSupports Fixed Length Burst Read and Write datatransfers of 2 to 16 data beats on the PLB Transfer width is equal to the parameterizedIPIC data width Automatic Burst Length Adjustment forbursting to/from narrower PLB Slave devicesThe User interface consists of a Command/Statusinterface and Read and Write LocalLink interfacesfor the data transfer LocalLink transfers can be 1 to 4092 bytes inlength with data width equal to the IPIC datawidthThe Master will automatically break IP Clienttransfer requests requiring more than 16 databeats into multiple fixed length bursts (2 to 16data beats) on the PLBConfigurationLUTsFFsDSPSlicesBlockRAMs263-645 107-194 161-376Max.Freq.NoneProvided with CoreDocumentationProduct SpecificationDesign FileFormatsVHDLConstraints FileNoneInstantiationTemplateVHDL WrapperReferenceDesigns &ApplicationNotesNoneDesign Tool RequirementsXilinxImplementationToolsISE 12.4VerificationMentor Graphics ModelSim 6.5cSimulationMentor Graphics ModelSim 6.5cSynthesis ToolsXSTSupport: Provided by Xilinx, Inc. Copyright 2009-2010 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinxin the United States and other countries. All other trademarks are the property of their respective owners.DS565 December 14, 2010Product Specificationwww.xilinx.com1
PLBV46 Master Burst (v1.01a)Functional DescriptionThe PLBV46 Master Burst is designed to provide a User with a quick way to implement a mastering interfacebetween User logic and the IBM PLB V4.6. Figure 1 shows a block diagram of the PLBV46 Master Burst. The portreferences and groupings are detailed in Table 1. The design allows for parameterization of both the Master’sinternal data width (Native Data Width) and the PLB data width of 32, 64, or 128 bits. Transfer request protocolbetween the PLB and the User Logic is provided by the Read and Write Controller block. The Bus Width Adapterand Steering Logic block provides the necessary function to connect the Master’s internal logic to the three availablePLB widths; 32, 64, and 128-bits. The PLB width must be greater than or equal to the Master’s Native Data Width.Xilinx Local Link InterfaceX-Ref Target - Figure 1User IPDesignPLBV46 MASTER BURSTMPLB ClkIPICMPLB RstRd/Wr Req & QualifiersPLB BusMaster Request & QualifiersPLB ReplyMaster Write Data(32/64/128 bits)PLB Read Data(32/64/128 bits)Bus thAdjustAdptr.Read&WriteControllerStatus ReplyWriteLocalLinkBackendWrite LocalLinkReadLocalLinkBackendRead LocalLinkFigure 1: PLBV46 Master Burst Block DiagramThe Client IP receives data from and transmits data to the PLB Master via the Xilinx LocalLink Interface protocol.LocalLink is a point-to-point, synchronous interface intended for high data rate applications. Because data flow isunidirectional, the PLB Master employs two LocalLink interfaces, one for IP Client data read operations and one forIP Client data write operations.LocalLink is based upon the concept of a Source device transmitting data to a Destination device. Data flow isunidirectional; always from the Source to the Destination. Both Source and Destination can throttle transfers as wellas choose to discontinue the transfer. In order for a transfer data beat to complete., both the Source and theDestination must signal that they are ready at the rising edge of the transfer synchronization clock (clk). The Sourceindicates a ready condition by asserting the src rdy n signal. The Destination indicates ready by asserting thedst rdy n signal.Data (d[n:0]) is transferred in a delimited group otherwise known as a packet. The start of a packet is delimited withthe assertion of the Start-of-Frame signal (sof n) by the Source. The assertion of End-of-Frame by the Source (eof n)delimits the last data beat of a packet. A single data beat transfer is delimited with simultaneous assertion of sof nand eof n.Transfer acknowledge/throttling is accomplished with the assertion of src rdy n and dst rdy n. De-assertion ofeither signal will throttle the transfer. If the Destination device can no longer transfer data or no longer needs data,DS565 December 14, 2010Product Specificationwww.xilinx.com2
PLBV46 Master Burst (v1.01a)it may assert the dst dsc n to discontinue the transfer. Conversely, the Source may terminate transmissionprematurely with the assertion of the src dsc n signal.Note: The current implementation of the PLBV46 Master Burst does not support discontinue assertion by the Client IPLocalLink interface. See the I/O signal descriptions of the individual discontinue signals inTable 1.The rem[0:n] signal (short for remainder) is set by the Source during each data beat in which a delimiter flag is set(sof n, sop n, eop n, eof n). The value asserted specifies the valid bytes in that data beat and are somewhatapplication specific depending on the needs of the source and destination devices. The rem can be either anencoded value or a masked value and either active high or active low assertion levels. For the PLBV46 MasterBurst, the rem bits are always a mask representation and active low assertion levels. Byte lane ordering followsPLB byte lane ordering.A basic LocalLink data transfers are shown in Figure 2. The data packet consists of 16 data beats of 32 bits wide. Thediagram shows both the Source and Destination throttling the transfer. In this case, the sop n and eop n are notshown because header and footer data is not being transmitted in the packet,Note: Note: The Xilinx LocalLink Interface specification allows the use of either right-to-left or left-to-right bit ordering as longthe Source and Destination are consistent. The PLBV46 Master Burst follows the IBM CoreConnect convention of left-to-right bitordering and Big Endian byte ordering.X-Ref Target - Figure 20ns100ns200ns300ns400ns500ns600ns700ns800nsclksof neof nsrc rdy ndst rdy nd[0:31]012345678910 11 12 13 14 15dst dsc nsrc dsc nFigure 2: Basic LocalLink TransferDS565 December 14, 2010Product Specificationwww.xilinx.com3
PLBV46 Master Burst (v1.01a)I/O SignalsThe PLBV46 Master Burst signals are listed and described in the following table.Table 1: PLBV46 Master Burst I/O Signal DescriptionSignal NameInterfaceSignal TypeInit StatusDescriptionPLB Clock and ResetMPLB ClkPLB BusIPLB main bus clock. See Note 1.MPLB RstPLB BusIPLB main bus reset.See Note 1.Other System SignalMD errorPLB BusO0Master Detected Error StatusOutput (active high).PLB Request and Qualifier SignalsM requestPLB BusO0See Note 1.M priorityPLB BusO0See Note 1.M buslockPLB BusO0See Note 1.M RNWPLB BusO0See Note 1.M BE(0:[C MPLB DWIDTH/8]-1)PLB BusOzerosSee Note 1.M Msize(0:1)PLB BusO00See Note 1.M size(0:3)PLB BusO0000See Note 1.M type(0:2)PLB BusO000See Note 1.M ABus(0:31)PLB BusOzerosSee Note 1.M wrBurstPLB BusO0See Note 1.M rdBurstPLB BusO0See Note 1.M wrDBus(0:C MPLB DWIDTH-1)PLB BusOzerosSee Note 1.PLB Reply SignalsPLB MSSize(0:1)PLB BusIUnused. See Note 2.PLB MaddrAckPLB BusISee Note 1.PLB MrearbitratePLB BusISee Note 1.PLB MTimeoutPLB BusISee Note 1.PLB MRdErrPLB BusISee Note 1.PLB MWrErrPLB BusISee Note 1.PLB MRdDBus(0:C MPLB DWIDTH-1)PLB BusISee Note 1.PLB MRdDAckPLB BusISee Note 1.PLB MWrDAckPLB BusISee Note 1.PLB RdBTermPLB BusISee Note 1.PLB MWrBTermPLB BusISee Note 1.PLB Signal Ports Included in the Design but Unused InternallyM TAttribute(0 to 15)DS565 December 14, 2010Product SpecificationPLB BusOwww.xilinx.com0Unused. See Note 2.4
PLBV46 Master Burst (v1.01a)Table 1: PLBV46 Master Burst I/O Signal DescriptionSignal NameInterfaceSignal TypeInit StatusDescriptionM lockerrPLB BusO0Unused. See Note 2.M abortPLB BusO0Unused. See Note 2.M UABus(0:31))PLB BusOzerosUnused. See Note 2.PLB MBusyPLB BusIUnused. See Note 2.PLB MIRQPLB BusIUnused. See Note 2.PLB RdWdAddr(0:3)PLB BusIUnused. See Note 2.IPIC Command Interface SignalsIP2Bus MstRd ReqIPICIUser Logic Read Request.IP2Bus MstWr ReqIPICIUser Logic Write Request.IP2Bus Mst Addr(0 toC MPLB AWIDTH-1)IPICIUser Logic Request Address.See Note 4.IP2Bus Mst BE(0 to[C MPLB NATIVE DWIDTH/8]-1)IPICIUser Logic Request Byte Enables(only used during single data beatrequests).IP2Bus Mst Length(0 to 11)IPICIUser Logic Request Length (bytes)for Fixed Length Burst Transfers.See Note 4.IP2Bus Mst TypeIPICIUser Logic Request Type Indicator0 Single Data Beat1 Fixed Length BurstSee Note 5.IP2Bus Mst LockIPICIReserved: Tie to logic Low.User Logic Bus Lock Request.IP2Bus Mst ResetIPICIOptional User Logic Reset.Request.Bus2IP Mst CmdAckIPICO0Command Acknowledge Status.Bus2IP Mst CmpltIPICO0Command Complete Status.Bus2IP Mst ErrorIPICO0Command Error Status.Bus2IP Mst RearbitrateIPICO0Command Rearbitrate Status.User Logic should ignore thissignal.Bus2IP Mst TimeoutIPICO0Command Timeout Status.IPIC Read LocalLink Interface SignalsBus2IP MstRd d(0 toC MPLB NATIVE DWIDTH-1)IPICOzerosRead data output to User Logic.Bus2IP MstRd REM(0 to[C MPLB NATIVE DWIDTH/8]-1)IPICOzerosLocalLink Remainder Indicators(Mask format, active low).See Note 6.Bus2IP MstRd sof nIPICO1Active low signal indicating thestarting data beat of a ReadLocalLink transfer.DS565 December 14, 2010Product Specificationwww.xilinx.com5
PLBV46 Master Burst (v1.01a)Table 1: PLBV46 Master Burst I/O Signal DescriptionSignal NameInterfaceSignal TypeInit StatusBus2IP MstRd eof nIPICO1Active low signal indicating theending data beat of a ReadLocalLink transfer.Bus2IP MstRd src rdy nIPICO1Active low signal indicating that thedata value asserted on theBus2IP MstRd d Bus is valid.Bus2IP MstRd src dsc nIPICO1Active low signal indicating that theRead LocalLink Source (Master)needs to discontinue the transfer.This will only be asserted if theMaster encounters a PLB Timeoutduring the address phase of aparent or child request to the PLB.IP2Bus MstRd dst rdy nIPICIIP2Bus MstRd dst dsc nIPICIDescriptionActive low signal indicating that thedata value asserted on theBus2IP MstRd d Bus is beingaccepted by the LocalLinkdestination (User Logic).Active low signal indicating that theRead LocalLink Destination (UserLogic) needs to discontinue thetransfer. This is currentlyunsupported in this Master. UserLogic should tie this signal to logichigh.IPIC Write LocalLink Interface SignalsIP2Bus MstWr d(0 toC MPLB NATIVE DWIDTH-1)IPICIWrite data input from the UserLogic.IP2Bus MstWr REM(0 toC REM WIDTH-1)IPICILocalLink Remainder input,ignored by the PLB Master Burst.User should tie to logic 0.IP2Bus MstWr sof nIPICIActive low signal indicating thestarting data beat of a WriteLocalLink transfer.IP2Bus MstWr eof nIPICIActive low signal indicating theending data beat of a WriteLocalLink transfer.IP2Bus MstWr src rdy nIPICIActive low signal indicating that thedata value asserted on theIP2Bus MstWr d Bus is valid.IP2Bus MstWr src dsc nIPICIActive low signal indicating that theWrite LocalLink Source (UserLogic) needs to discontinue thetransfer. This is currentlyunsupported in this Master. UserLogic should tie this signal to logichigh.DS565 December 14, 2010Product Specificationwww.xilinx.com6
PLBV46 Master Burst (v1.01a)Table 1: PLBV46 Master Burst I/O Signal DescriptionSignal NameInterfaceSignal TypeInit StatusDescriptionBus2IP MstWr dst rdy nIPICO1Active low signal indicating that thedata value asserted on theIP2Bus MstWr d Bus is beingaccepted by the LocalLinkdestination (Master).IP2Bus MstWr dst dsc nIPICO1Active low signal indicating that theWrite LocalLink Destination(Master) needs to discontinue thetransfer. This will only be assertedif the Master encounters a PLBTimeout during the address phaseof a parent or child request to thePLB.Note 1This signal’s function and timing is defined in the IBM 128-Bit Processor Local Bus Architecture SpecificationVersion 4.6.Note 2Output ports that are not used are driven to constant logic levels that are consistent with the inactive state for thesubject signal. Input ports that are required but not used are internally ignored by the design.Note 3For fixed length burst requests, the starting address for the request as specified by the IP2Bus Mst Addr(0:31)input must be aligned on an address boundary matching the C MPLB NATIVE DWIDTH value.Note 4The request length is specified in bytes and must be a multiple of C MPLB NATIVE DWIDTH/8.Note 5The requested data transfer width for a fixed length burst request will be automatically set to the native data widthof the Master which is assigned with the C MPLB NATIVE DWIDTH parameter.Note 6The PLBV46 Master Burst only supports Mask representation (as opposed to encoded representation) for values onthe LocalLink REM buses. In addition, the REM values must be asserted active low.DS565 December 14, 2010Product Specificationwww.xilinx.com7
PLBV46 Master Burst (v1.01a)Design ParametersThe PLBV46 Master Burst provides for User interface tailoring via VHDL Generic parameters. These parameters aredetailed in the following table. The FPGA Family Type parameter is used to select the target FPGA family type.Currently, this design supports Virtex-4, Virtex-5, and Spartan-3 family of devices.Table 2: PLBV46 Master Burst Design ParametersFeature/DescriptionParameter NameAllowable ValuesDefaultValuesVHDLTypePLB I/O SpecificationSpecifies the Number of UsedAddress bits out of the available 64bits of PLBV46 addressingC MPLB AWIDTH3232integerWidth of the PLB Data Bus towhich the Master is attachedC MPLB DWIDTH32, 64, 12832integerSpecifies the internal native datawidth of the MasterC MPLB NATIVE DWIDTH32, 64, 12832integerC MPLB SMALLEST SLAVE32, 64, 12832integer0integervirtex5stringNarrow Slave SupportIndicates the smallest Native DataWidth of any Slave attached to thePLBV46 Bus used by the Master(1)This parameter is used to overridethe automatic inclusion of theConversion Cycle and Burst lengthExpansion logic (1)C INHIBIT CC BLE INCLUSION 0, 10 Allow automaticinclusion of CC andBLE logic1 Inhibit automaticinclusion of the CC andBLE logicFPGA Family TypeXilinx FPGA FamilyC FAMILYvirtex4,virtex5,spartan3a, aspartan3a,spartan3, aspartan3,spartan3e, aspartan3e,spartan3adsp,aspartan3adspNote: If the Master is parameterized to have 64 or 128 bit Native Data Width and it potentially can access a Slave that isnarrower than the requested data transfer size by the Master (indicated by the C MPLB SMALLEST SLAVE parameter value),then Conversion Cycle and Burst Length Expansion logic is required by the Master to complete the transfer. Masters that areparameterized to 32-bit Native Data Width do not need the logic regardless of target Slave data width.DS565 December 14, 2010Product Specificationwww.xilinx.com8
PLBV46 Master Burst (v1.01a)Allowable Parameter CombinationsThe current implementation of the PLBV46 Master Burst has the following restrictions that apply to parametervalue settings: The assigned value for C MPLB AWIDTH is currently restricted to 32. The value of C MPLB DWIDTH must be greater than or equal to the value assigned toC MPLB NATIVE DWIDTH.Parameter - Port DependenciesTable 3: PLBV46 Master Burst Parameter-Port DependenciesName(Generic or Port)Affects(Port)Depends(Generic)Relationship DescriptionDesign ParametersC MPLB AWIDTHIP2Bus Mst AddrThe Parameter directly sets the portswidth.C MPLB DWIDTHM BEThe BE Bus width is derived from theparameter value by dividing it by 8.C MPLB DWIDTHM wrDBusThe port width is directly set by theparameter value.C MPLB DWIDTHPLB MRdDBusThe port width is directly set by theparameter value.C MPLB NATIVE DWIDTHIP2Bus Mst BEThe IPIC BE Bus width is derived fromthe parameter value by dividing it by 8.C MPLB NATIVE DWIDTHBus2IP MstRd dThe IPIC Read LocalLink Data port widthis directly set by the parameter value.C MPLB NATIVE DWIDTHIP2Bus MstWr dThe IPIC LocalLink Write Data port widthis directly set by the parameter value.C MPLB NATIVE DWIDTHBus2IP MstRd REMThe IPIC Read LocalLink REM port widthis derived from the parameter value bydividing it by 8.C MPLB NATIVE DWIDTHIP2Bus MstWr REMThe IPIC Write LocalLink REM port widthis derived from the parameter value bydividing it by 8.DS565 December 14, 2010Product Specificationwww.xilinx.com9
PLBV46 Master Burst (v1.01a)Parameter Detailed DescriptionsC MPLB AWIDTHThis integer parameter is used by the PLBV46 Master Burst to size internal address related components and theinput address from the User logic on the Command Interface. The parameter is provided for future growth beyond32-bit addressing. Currently, the parameter value is only allowed to be set 32.C MPLB DWIDTHThis integer parameter is used by the PLBV46 Master Burst to size and optimize the PLBV46 data bus interfacelogic. This value should be set to match the actual width of the PLBV46 bus, 32, 64 or 128-Bits.C MPLB NATIVE DWIDTHThis integer parameter is used to specify the internal data width of the PLBV46 Master Burst as well as the IPIC datawidth to the User Logic. The parameter may be set to 32, 64, or 128.C MPLB SMALLEST SLAVEThis parameter is defined as an integer and is set to the smallest Native Data Width of any Slave that is attached tothe same PLBV46 bus as the Master. Allowed values are 32, 64, and 128. The parameter is used when the Master isparameterized with a Native Data Width of 64 or 128 bits. If the value of the C MPLB SMALLEST SLAVE is lessthan the Native Data Width of the Master, then Conversion Cycle and Burst Length Expansion logic isautomatically included in the Master’s implementation.C INHIBIT CC BLE INCLUSIONThis parameter is used to inhibit the automatic inclusion of the Conversion Cycle and Burst Length Expansion logicif it is known by the User that the Master will not be accessing the narrower Slaves or the requested transfer widthsfor any access will not exceed the Native Data Width of any targeted Slave.C FAMILYThis parameter is defined as a string. It specifies the target FPGA technology for implementation of the PLB Slave.This parameter is required for proper selection of FPGA primitives. Currently, the PLBV46 Master Burst does notimplement any FPGA primitives that require the use of this parameter.IPIC Transaction TimingThe following section shows timing relationships for PLBV46 and IPIC interface signals during read and writetransfers. Single data beat and Fixed Length Burst transfers are shown.DS565 December 14, 2010Product Specificationwww.xilinx.com10
PLBV46 Master Burst (v1.01a)Single Data Beat Read OperationTwo single beat read cycles are shown in Figure 3. The Master has a Native Data Width of 32 bits and the PLB datawidth is 32 bits. The first cycle shows the PLB Slave address and data acknowledging the read cycle at the
Windows XP Professional 32-Bit/64-Bit, Windows Vista Business 32-Bit/64-Bit, Red Hat Enterprise Linux WS v4.0 32-bit/64-bit, Red Hat Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option), SUSE Linux Enterprise (SLE) desktop and server v10.1 32-bit/64-bit Resources Configuration LUTs
LogiCORE IP Facts Core Specifics Supported Device Family . The PLBV46 Master inte rface may be directly connected to the multi-port memory controller (MPMC5) or PPC440 SPLB using a point to point topology or to a PLBV46 shared bus configuration (not shown). The Host Core is connected to the USB 2.0 PHY (external to the FPGA)
(i.e., 10 ms) in-between each burst I know, it is confusing that we are specifying a burst size for steady traffic Notice the Inter-frame Gap is 130 Mbps Increase the burst size to send the burst more or less frequently The Bursty Traffic is items 2 and will send burst size 100 at 100% MBR Notice the Inter-frame Gap is 12 Bytes
Burst Tolerance After the rupture disc has been manufactured and tested, it is marked with the rated burst pressure. The rated (marked) burst pressure is established by bursting a minimum of two rupture discs and averaging the pressures at which the rupture discs burst. This average is the rated (mar
That is, a burst is carried by a time-slot. A burst in a time-slot must not overlap the bursts in the previous and next time-slots. Therefore, the time-slot is set to 156.25 bit-periods - bigger than the biggest burst (148 bits). The spare time (minimum 156.25 - 148 8.25 bit-periods) is the guard time. That is, Time-slot burst-
2.2 Hydrostatic Burst Test Test conditions of the hydrostatic burst test are presented in Table 2, and the schematic diagram of the apparatus for the burst test is shown in Fig. 1. Test tanks were prepared on a closed, dry pit floor. A pressure sensor was installed on the tank side of the pressure line to correctly measure the pressure of the .
The specified burst pressure calibrated at 20 C The tolerance on PRS The temperature for which the burst pressure is specified The coupling type The tightening torque The CE marking (for burst pressure 0.50 bar) The standard used The PED fluid gro
6.3 Burst Disc Tests 23 6.4 Conclusions 23 7 STEEL BURST DISCS 26 7.1 Introduction 26 7.2 Previous Tests - High Speed Film Clip 26 7.3 Burst Disc Inversion and Deformation 28 7.4 Previous Tests - Review of Data for the 8in Disc 30 7.5 New Experimental Tests 33 7.6 Conclusions 34 8 GRA
Wei Yang Introduction to Mean field games and applications. Introduction Our results and applications Mean field game Methodology consider an N-playerstochastic dynamic game study amean field game(a limit for N !1) which can be expressed bya system of coupled equations: Fokker-Planck equation Hamilton-Jacobi-Bellman equation any solution to the mean field game is an -equilibriumto the N .
