Low Voltage Quad Receiver UT54LVDS032LV/E

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/EFeatures RELEASED 10/17 400.0 Mbps (200 MHz) switching rates 340mV nominal differential signaling3.3 V power supplyTTL compatible inputsCold sparing all pinsUltra low power CMOS technology1.9ns maximum propagation delay200ps maximum differential skewOperational environment; total dose irradiation testing to MIL-STD-883 Method 1019- Total-dose: 300 krad(Si) and 1Mrad(Si)- Latchup immune (LET 100 MeV-cm2/mg) Packaging options:- 16-lead flatpack (0.7 grams) Standard Microcircuit Drawing 5962-98652- QML Q and V compliant part Compatible with ANSI/TIA/EIA-644 StandardIntroductionThe UT54LVDS032LV Quad Receiver is a quad CMOS differential line receiver designed for applications requiringultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400.0Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.The UT54LVDS032LV accepts low voltage (340mV) differential input signals and translates them to 3V CMOS outputlevels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver alsosupports OPEN, shorted and terminated (100 W) input fail-safe. Receiver output will be HIGH for all fail-safeconditions.The UT54LVDS032LV and companion quad line driver UT54LVDS031LV provides new alternatives to high powerpseudo-ECL devices for high speed point-to-point interface applications.All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/ERELEASED 10/17Figure 1. UT54LVDS032LV Quad Driver Block Diagram4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/EFigure 2. UT54LVDS032LV PinoutTruth TableEnablesInputOutputENENRIN - RIN-ROUTLHXZAll other combinations ofENABLE inputsVID 0.1VHVID -0.1VLFull Fail-safe OPEN/SHORT or TerminatedHPin DescriptionRELEASED 10/17Pin No.NameDescription2, 6, 10, 14RIN Non-inverting receiver input pin1, 7, 9, 15RIN-Inverting receiver input pin3, 5, 11, 13ROUTReceiver output pin4ENActive high enable pin, OR-ed with EN12ENActive low enable pin, OR-ed with EN16VDDPower supply pin, 3.3 0.3V8VSSGround pinApplications InformationThe UT54LVDS032LV receiver’s intended use is primarily in an uncomplicated point-to-point configuration as isshown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers.The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, aparallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of100W. A termination resistor of 100W should be selected to match the media and is located as close to the receiverinput pins as possible. The termination resistor converts the current sourced by the driver into voltages that aredetected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of amid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noisemargin limits, and total termination loading must be taken into account.Figure 3. Point-to-Point Application4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/EThe UT54LVDS032LV differential line receiver is capable of detecting signals as low as 100mV, over a 1V commonmode range centered around 1.2V. This is related to the driver offset voltage which is typically 1.2V. The drivensignal is centered around this voltage and may shift 1V around this center point. The 1V shifting may be the resultof a ground potential difference between the driver’s ground reference and the receiver’s ground reference, thecommon-mode effects of coupled noise or a combination of the two. Both receiver input pins should honor theirspecified operating input voltage range of 0V to 2.4V (measured from each pin to ground).Receiver Fail-SafeThe UT54LVDS032LV receiver is a high gain, high speed device that amplifies a small differential signal (20mV) toTTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise fromappearing as a valid signal.The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safeprotection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.RELEASED 10/171) Open Input Pins The UT54LVDS032LV is a quad receiver device, and if an application requires only 1, 2or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs toground or any other voltages. The input is biased by internal high value pull up and pull down resistors toset the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for openinputs.2) Terminated Input If the driver is disconnected (cable unplugged), or if the driver is in a three-state orpower-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Wtermination resistor across the input pins. The unplugged cable can become a floating antenna which canpick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise asa valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balancedinterconnect should be used. Twisted pair cable offers better balance than flat ribbon cable.3) Shorted Inputs If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0Vdifferential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is notsupported across the common-mode range of the device (VSS to 2.4V). It is only supported with inputsshorted and no external common-mode voltage applied.Operational EnvironmentParameterLimitUnitsTotal Ionizing Dose (TID)1.0E6rad(Si)Single Event Latchup (SEL) 100MeV-cm2/mg1.0E13n/cm2Neutron Fluence 1Note:1) Guaranteed but not tested.4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/EAbsolute Maximum Ratings 1(Referenced to VSS)SymbolVDDVI/OParameterLimitsDC supply voltage-0.3 to 4.0VLVDS I/O during operation-0.3V to 3.9VLVTTL I/O during operation-0.3 to (VDD 0.3V)All I/O during cold spare (VDD VSS)TSTGStorage temperaturePDMaximum power dissipationTJMaximum junction temperatureQJC-65 to 150 1.25 W2Thermal resistance, junction-to-caseII-0.3 to 4.3V 150 3DC input current10 /W 10mANotes:1) Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress ratingRELEASED 10/17only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sectionsof this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability and performance.2) Maximum junction temperature may be increased to 175 during burn-in and life test.3) Test per MIL-STD-883, Method 1012.Recommended Operating ConditionsSymbolParameterLimitsVDDPositive supply voltageTCCase temperature rangeVINDC input voltage, receiver inputsDC input voltage, logic inputs3.0 to 3.6V-55 to 125 2.4V0 to VDD for EN, ENDC Electrical Characteristics* 14350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/E(VDD 3.3V 0.3V; -55 TC 125 ); Unless otherwise noted, Tc is per the temperature range orderedSymbolParameterConditionVIHHigh-level input voltage(TTL)VILLow-level input voltage(TTL)0.8VVOLLow-level output voltageIOL 2mA, VDD 3.0V0.25VVOHHigh-level output voltageIOH -0.4mA, VDD 3.0V2.7IINLogic input leakage currentEnables EN/EN 0 and 3.6V, VDD 3.6-10 10µAIIReceiver input CurrentVIN 2.4V-15 15µAICSCold Spare Leakage CurrentVIN 3.6V, VDD VSS-20 20µA 100mVVTH 3MIN2.0Differential Input High ThresholdVCM 1.2VVTL3Differential Input Low ThresholdVCM 1.2V-100IOZ3Output Three-State CurrentDisabled, VOUT 0 V or VDD-10Input clamp voltageICL 18mA-1.5VCLIOS2, 3MAX2RELEASED 10/17Output Short Circuit CurrentEnabled, VOUT 0 VICC 3Supply current, receivers enabledEN, EN VDD or VSSInputs OpenICCZ 3Supply current, receivers disabledEN VSS, EN VDDInputs Open-15UnitVVmV 10µAV-130154mAmAmANotes:*For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25 per MILSTD-883 Method 1019, Condition A up to the maximum TID level procured.1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referencedto ground.2) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output shouldbe shorted at a time, do not exceed maximum junction temperature specification.3) Guaranteed by characterization.AC Switching Characteristics 1, 2, 3(VDD 3.3V 0.3V, TC -55 to 125 ); Unless otherwise noted, TC is per the temperature range ordered4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad DS032LVMINMAXUnitUT54LVDS032LVEtPHLDDifferential Propagation Delay High to Low (figures 4and 5)1.04.01.01.9nstPLHDDifferential Propagation Delay Low to High (figures 4and 5)1.04.01.01.9nstSKDDifferential Skew (tPHLD - tPLHD) (figures 4 and 5)03500210ps05000200pstSK1Channel-to-Channel Skew (figures 4 and 5)tSK2Chip-to-Chip Skew 5 (figures 4 and 5)3.00.9nsRise Time (figures 4 and 5)1.21.2nsFall Time (figures 4 and 5)1.21.2nstPHZDisable Time High to Z (figures 6 and 7)123.8nstPLZDisable Time Low to Z (figures 6 and 7)123.8nstPZHEnable Time Z to High (figures 6 and 7)123.8nstPZLEnable Time Z to Low (figures 6 and 7)123.8nstTLH 4tTHL41RELEASED 10/17Notes:*For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25 per MILSTD-883 Method 1019, Condition A up to the maximum TID level procured.1) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channelsin the same chip with an event on the inputs.2) Generator waveform for all tests unless otherwise specified: f 1 MHz, Z0 50W, tr and tf (0% - 100%) 1ns for RIN and trand tf 1ns for EN or EN.3) CL includes probe and jig capacitance.4) Guaranteed by characterization.5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagationdelays.4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/EFigure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent CircuitRELEASED 10/17Figure 5. Receiver Propagation Delay and Transition Time WaveformsFigure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/ERELEASED 10/17Figure 7. Receiver Three-State Delay Waveform4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com

DATASHEETLow Voltage Quad ReceiverUT54LVDS032LV/EPackagingRELEASED 10/17Figure 8. 16-pin Ceramic Flatpack4350 Centennial Blvd. Colorado Springs CO 80907 USA 1-800-645-8862 cobhamaes.com