ESP32 Technical Reference ManualEspressif SystemsSeptember 7, 2016
About This ManualESP32 Technical Reference Manual targets application developers. The manual provides detailed andcomplete information on how to use the ESP32 memory and peripherals.Release NotesDateVersionRelease notes2016.08V1.0Initial release.Disclaimer and Copyright NoticeInformation in this document, including URL references, is subject to change without notice. THIS DOCUMENTIS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OFMERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTYOTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.All liability, including liability for infringement of any proprietary rights, relating to use of information in thisdocument is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual propertyrights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetoothlogo is a registered trademark of Bluetooth SIG.All trade names, trademarks and registered trademarks mentioned in this document are property of theirrespective owners, and are hereby acknowledged.Copyright 2016 Espressif Inc. All rights reserved.
Contents1 System and Memory81.1Introduction81.2Features81.3Functional Description101.3.1Address Mapping101.3.2Embedded Memory126.96.36.199Internal ROM 0188.8.131.52Internal ROM 1184.108.40.206Internal SRAM 0220.127.116.11Internal SRAM 118.104.22.168Internal SRAM 222.214.171.124DMA126.96.36.199RTC FAST Memory188.8.131.52RTC SLOW Memory131.3.3External Memory131.3.4Peripherals184.108.40.206Asymmetric PID Controller Peripheral220.127.116.11Non-Contiguous Peripheral Memory Ranges18.104.22.168Memory Speed162 Interrupt l Description172.3.1Peripheral Interrupt Source172.3.2CPU Interrupt202.3.3Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU202.3.4CPU NMI Interrupt Mask212.3.5Query Current Interrupt Status of Peripheral Interrupt Source213 Reset and Clock223.1223.2System Reset3.1.1Introduction223.1.2Reset Source22System Clock233.2.1Introduction233.2.2Clock Source243.2.3CPU Clock243.2.4Peripheral Clock253.2.4.1APB CLK Source253.2.4.2REF TICK Source222.214.171.124LEDC SCLK Source2126.96.36.199APLL SCLK Source2188.8.131.52PLL D2 CLK Source26
184.108.40.206Clock Source Considerations273.2.5Wi-Fi BT Clock273.2.6RTC Clock274 IO MUX and GPIO Matrix284.1Introduction284.2Peripheral Input via GPIO Matrix2220.127.116.11.2.1Summary294.2.2Functional Description294.2.3Simple GPIO Input30Peripheral Output via GPIO Matrix304.3.1Summary304.3.2Functional Description304.3.3Simple GPIO Output31Direct I/O via IO MUX314.4.1Summary314.4.2Functional Description32RTC IO MUX for Low Power and Analog I/O324.5.1Summary324.5.2Functional Description324.6Light-sleep Mode Pin Functions324.7Pad Hold Feature334.8I/O Pad Power Supply318.104.22.168VDD SDIO Power DomainPeripheral Signal List33344.10 IO MUX Pad List384.11 RTC MUX Pin List394.12 Register Summary404.13 Registers455 LED PWM665.1Introduction665.2Functional Channels675.2.4Interrupts685.3Register Summary685.4Registers716 Remote Controller Peripheral816.1Introduction816.2Functional Description816.2.1RMT Architecture816.2.2RMT RAM826.2.3Clock826.2.4Transmitter82
6.2.5Receiver836.2.6Interrupts836.3Register Summary846.4Registers857 PULSE CNT907.1Introduction907.2Functional Description907.2.1Architecture907.2.2Counter Channel rrupts927.3Register Summary927.4Registers948 64-bit Timers988.1Introduction988.2Functional Description988.2.116-bit Prescaler988.2.264-bit Time-base Counter988.2.3Alarm r summary8.4Registers991019 Watchdog l Description1089.39.3.1Clock1089.3.1.1Operating Procedure1099.3.1.2Write Protection1099.3.1.3Flash Boot Protection1099.3.1.4Registers11010 AES Accelerator11110.1 Introduction11110.2 Features11110.3 Functional Description11110.3.1 AES Algorithm Operations11110.3.2 Key, Plaintext and Ciphertext11110.3.3 Endianness11210.3.4 Encryption and Decryption Operations11410.3.5 Speed11410.4 Register summary114
10.5 Registers11611 SHA Accelerator11811.1 Introduction11811.2 Features11811.3 Functional Description11811.3.1 Padding and Parsing the Message11811.3.2 Message Digest11811.3.3 Hash Operation11911.3.4 Speed11911.4 Register Summary11911.5 Registers121
List of Tables1Address Mapping102Embedded Memory Address Mapping113Module with DMA134External Memory Address Mapping145Peripheral Address Mapping146PRO CPU, APP CPU interrupt configuration187CPU Interrupts208PRO CPU and APP CPU reset reason values229CPU CLK Source2410CPU CLK Derivation2511Peripheral Clock Usage2512APB CLK Derivation2613REF TICK Derivation2614LEDC SCLK Derivation2615IO MUX Light-sleep Pin Function Registers3216GPIO Matrix Peripheral Signals3417IO MUX Pad Summary3818RTC MUX Pin Summary3926Operation Mode11127AES Text Endianness11228AES-128 Key Endianness11329AES-192 Key Endianness11330AES-256 Key Endianness113
List of Figures1System Structure92System Address Mapping93Interrupt Matrix Structure174System Reset225System Clock236IO MUX, RTC IO MUX and GPIO Matrix Overview287Peripheral Input via IO MUX, GPIO Matrix298Output via GPIO Matrix319ESP32 I/O Pad Power Sources3310LED PWM Architecture6611LED PWM High-speed Channel Diagram6612LED PWM Output Signal Diagram6713Output Signal Diagram of Gradient Duty Cycle6814RMT Architecture8115Data Structure8216PULSE CNT Architecture9017PULSE CNT Upcounting Diagram9218PULSE CNT Downcounting Diagram92
1 SYSTEM AND MEMORY1.System and Memory1.1IntroductionThe ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning they use thesame addresses to access the same memory. Multiple peripherals in the system can access embedded memoryvia DMA.The two CPUs are named “PRO CPU” and “APP CPU” (for “protocol” and “application”), however for mostpurposes the two CPUs are interchangeable.1.2Features Address Space– Symmetric address mapping– 4 GB (32-bit) address space for both data bus and instruction bus– 1296 KB embedded memory address space– 19704 KB external memory address space– 512 KB peripheral address space– Some embedded and external memory regions can be accessed by either data bus or instruction bus– 328 KB DMA address space Embedded Memory– 448 KB Internal ROM– 520 KB Internal SRAM– 8 KB RTC FAST Memory– 8 KB RTC SLOW Memory External MemoryOff-chip SPI memory can be mapped into the available address space as external memory. Parts of theembedded memory can be used as transparent cache for this external memory.– Supports up to 16 MB off-Chip SPI Flash.– Supports up to 8 MB off-Chip SPI SRAM. Peripherals– 41 peripherals DMA– 13 modules are capable of DMA operationEspressif Systems8ESP32 Technical Reference Manual V1.0
1.2 Features1 SYSTEM AND MEMORYFigure 1 block diagram illustrates the system structure, the block diagram in Figure 2 illustrates the address mapstructure.Figure 1: System StructureFigure 2: System Address MappingEspressif Systems9ESP32 Technical Reference Manual V1.0
1.3 Functional Description22.214.171.124 SYSTEM AND MEMORYFunctional DescriptionAddress MappingEach of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces aresymmetric between the two CPUs.Addresses below 0x4000 0000 are serviced using the data bus. Addresses in the range 0x4000 0000 0x4FFF FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000 0000 areshared by the data and instruction bus.The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 accessthe least significant, second least significant, second most significant, and most significant bytes of the 32-bitword stored at address 0x0, respectively. The CPU can access data bus addresses via aligned or non-alignedbyte, half-word and word read and write operations. The CPU can read and write data through the instructionbus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.Each CPU can directly access embedded memory through both the data bus and the instruction bus, externalmemory which is mapped into the address space (via transparent caching & MMU) and peripherals. Table 1illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.Some embedded memories and some external memories can be accessed via the data bus or the instructionbus. In these cases, the same memory is available to either of the CPUs at two address ranges.Table 1: Address MappingBus TypeBoundary AddressSizeTargetLow AddressHigh Address0x0000 00000x3F3F FFFFData0x3F40 00000x3F7F FFFF4 MBExternal MemoryData0x3F80 00000x3FBF FFFF4 MBExternal Memory0x3FC0 00000x3FEF FFFF3 MBReservedData0x3FF0 00000x3FF7 FFFF512 KBPeripheralData0x3FF8 00000x3FFF FFFF512 KBEmbedded MemoryInstruction0x4000 00000x400C 1FFF776 KBEmbedded MemoryInstruction0x400C 20000x40BF FFFF11512 KBExternal Memory0x40C0 00000x4FFF FFFF244 MBReserved0x5000 00000x5000 1FFF8 KBEmbedded Memory0x5000 20000xFFFF FFFFData Instruction1.3.2ReservedReservedEmbedded MemoryThe Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FASTmemory (8 KB) and RTC SLOW memory (8 KB).The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB).The 520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), andInternal SRAM 2 (200 KB).RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.Table 2 lists all embedded memories and their address ranges on the data and instruction buses.Espressif Systems10ESP32 Technical Reference Manual V1.0
1.3 Functional Description1 SYSTEM AND MEMORYTable 2: Embedded Memory Address MappingBoundary AddressBus TypeSizeTargetComment0x3FF8 1FFF8 KBRTC FAST MemoryPRO CPU Only0x3FF8 20000x3FF8 FFFF56 KBReserved-0x3FF9 00000x3FF9 FFFF64 KBInternal ROM 1-0x3FFA 00000x3FFA DFFF56 KBReserved-Data0x3FFA E0000x3FFD FFFF200 KBInternal SRAM 2DMAData0x3FFE 00000x3FFF FFFF128 KBInternal SRAM 1DMASizeTargetCommentDataDataLow AddressHigh Address0x3FF8 0000Boundary AddressBus TypeLow AddressHigh AddressInstruction0x4000 00000x4000 7FFF32 KBInternal ROM 0RemapInstruction0x4000 80000x4005 FFFF352 KBInternal ROM 0-0x4006 00000x4006 FFFF64 KBReserved-Instruction0x4007 00000x4007 FFFF64 KBInternal SRAM 0CacheInstruction0x4008 00000x4009 FFFF128 KBInternal SRAM 0-Instruction0x400A 00000x400A FFFF64 KBInternal SRAM 1-Instruction0x400B 00000x400B 7FFF32 KBInternal SRAM 1RemapInstruction0x400B 80000x400B FFFF32 KBInternal SRAM 1-Instruction0x400C 00000x400C 1FFF8 KBRTC FAST MemoryPRO CPU OnlySizeTargetComment8 KBRTC SLOW Memory-Boundary AddressBus TypeData Instruction126.96.36.199Low AddressHigh Address0x5000 00000x5000 1FFFInternal ROM 0The capacity of Internal ROM 0 is 384 KB, It is accessible by both CPUs through the address range0x4000 0000 0x4005 FFFF, which is on the instruction bus.The address range of the first 32 KB of the ROM 0 (0x4000 0000 0x4000 7FFF) can be re-mapped to accessa part of Internal SRAM 1 that normally resides in the memory range 0x400B 0000 0x400B 7FFF instead.While remapping, such 32 KB SRAM can not be accessed by address range 0x400B 0000 0x400B 7FFF anymore, but it can still be accessible through the data bus (0x3FFE 8000 0x3FFE FFFF). This can be done on aper-CPU basis: setting bit 0 of register DPORT PRO BOOT REMAP CTRL REG orDPORT APP BOOT REMAP CTRL REG will remap SRAM for the PRO CPU and APP CPU,respectively.188.8.131.52Internal ROM 1The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at address range 0x3FF9 0000 0x3FF9 FFFF of the data bus.Espressif Systems11ESP32 Technical Reference Manual V1.0
1.3 Functional Description184.108.40.206 SYSTEM AND MEMORYInternal SRAM 0The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64KB to cache externalmemory access. When not used as cache, the first 64KB can be read and written by either CPU at addresses0x4007 0000 0x4007 7FFF of the instruction bus. The remaining 128 KB can always be read and written byeither CPU at addresses 0x4007 8000 0x4007 FFFF of instruction bus.220.127.116.11Internal SRAM 1The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses0x3FFE 0000 0x3FFF FFFF of the data bus, and also at addresses 0x400A 0000 0x400B FFFF of theinstruction bus.The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via thedata bus. That is to say, address0x3FFE 0000 and 0x400B FFFC access the same word0x3FFE 0004 and 0x400B FFF8 access the same word0x3FFE 0008 and 0x400B FFF4 access the same word 0x3FFF FFF4 and 0x400A 0008 access the same word0x3FFF FFF8 and 0x400A 0004 access the same word0x3FFF FFFC and 0x400A 0000 access the same wordThe data bus and instruction bus of the CPU are still both little endian, so the byte order of individual words is notreversed between address spaces. For example, address0x3FFE 0000 accesses the least significant byte in the word accessed by 0x400B FFFC.0x3FFE 0001 accesses the second least significant byte in the word accessed by 0x400B FFFC.0x3FFE 0002 accesses the second most significant byte in the word accessed by 0x400B FFFC.0x3FFE 0003 accesses the most significant byte in the word accessed by 0x400B FFFC.0x3FFE 0004 accesses the least significant byte in the word accessed by 0x400B FFF8.0x3FFE 0005 accesses the second least significant byte in the word accessed by 0x400B FFF8.0x3FFE 0006 accesses the second most significant byte in the word accessed by 0x400B FFF8.0x3FFE 0007 accesses the most significant byte in the word accessed by 0x400B FFF8. 0x3FFF FFF8 accesses the least significant byte in the word accessed by 0x400A 0004.0x3FFF FFF9 accesses the second least significant byte in the word accessed by 0x400A 0004.0x3FFF FFFA accesses the second most significant byte in the word accessed by 0x400A 0004.0x3FFF FFFB accesses the most significant byte in the word accessed by 0x400A 0004.0x3FFF FFFC accesses the least significant byte in the word accessed by 0x400A 0000.0x3FFF FFFD accesses the second most significant byte in the word accessed by 0x400A 0000.0x3FFF FFFE accesses the second most significant byte in the word accessed by 0x400A 0000.0x3FFF FFFF accesses the most significant byte in the word accessed by 0x400A 0000.Part of this memory can be remapped to the ROM 0 address space. See Internal Rom 0 for moreinformation.Espressif Systems12ESP32 Technical Reference Manual V1.0
1.3 Functional Description18.104.22.168 SYSTEM AND MEMORYInternal SRAM 2The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA E000 0x3FFD FFFF on the data bus.22.214.171.124DMADMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.This means DMA uses address range 0x3FFE 0000 0x3FFF FFFF to read and write Internal SRAM 1 andaddress range 0x3FFA E000 0x3FFD FFFF to read and write Internal SRAM 2.In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals.Table 3: Module with DMAUART0UART1UART2SPI1SPI2SPI3I2S0I2S1SDIO SlaveSDMMCEMACBT126.96.36.199WIFIRTC FAST MemoryRTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO CPU only at address range0x3FF8 0000 0x3FF8 1FFF on the data bus or address range 0x400C 0000 0x400C 1FFF on theinstruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by theAPP CPU.The two address ranges of PRO CPU access RTC FAST Memory in the same order, so for example, address0x3FF8 0000 and 0x400C 0000 access the same word. On the APP CPU, these address ranges do notprovide access to RTC FAST Memory or any other memory location.188.8.131.52RTC SLOW MemoryRTC SLOW Memory is 8 KB of SRAM which can be read from and written by either CPU at address range0x5000 0000 0x5000 1FFF. This address range is shared by both the data bus and the instruction bus.1.3.3External MemoryThe ESP32 can access external SPI flash and SPI SRAM as external memory. Table 4 provides a list of externalmemories that can be accessed by either CPU at a range of addresses on the data and instruction buses. Whena CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to anexternal physical memory address (in the external memory’s address space), according to the MMU settings. Dueto this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.Espressif Systems13ESP32 Technical Reference Manual V1.0
1.3 Functional Description1 SYSTEM AND MEMORYTable 4: External Memory Address MappingBus TypeBoundary AddressSizeTargetComment0x3F7F FFFF4 MBExternal FlashRead0x3FBF FFFF4 MBExternal SRAMRead and WriteSizeTargetComment11512 KBExternal FlashReadLow AddressHigh AddressData0x3F40 0000Data0x3F80 0000Bus TypeInstruction1.3.4Boundary AddressLow AddressHigh Address0x400C 20000x40BF FFFFPeripheralsThe ESP32 has 41 peripherals. Table 5 specifically describes the peripherals their respective address ranges.Almost all peripheral modules can be accessed by either CPU at the same address, the only exception being thePID Controller.Table 5: Peripheral Address MappingBus TypeBoundary AddressSizeTarget0x3FF0 0FFF4 KBDPort Register0x3FF0 10000x3FF0 1FFF4 KBAES AcceleratorData0x3FF0 20000x3FF0 2FFF4 KBRSA AcceleratorData0x3FF0 30000x3FF0 3FFF4 KBSHA AcceleratorData0x3FF0 40000x3FF0 4FFF4 KBSecure Boot0x3FF0 50000x3FF0 FFFF44 KBReserved0x3FF1 00000x3FF1 3FFF16 KBCache MMU Table0x3FF1 40000x3FF1 EFFF44 KBReserved0x3FF1 F0000x3FF1 FFFF4 KBPID Controller0x3FF2 00000x3FF3 FFFF128 KBReserved0x3FF4 00000x3FF4 0FFF4 KBUART00x3FF4 10000x3FF4 1FFF4 KBReservedData0x3FF4 20000x3FF4 2FFF4 KBSPI1Data0x3FF4 30000x3FF4 3FFF4 KBSPI0Data0x3FF4 40000x3FF4 4FFF4 KBGPIO0x3FF4 50000x3FF4 7FFF12 KBReservedData0x3FF4 80000x3FF4 8FFF4 KBRTCData0x3FF4 90000x3FF4 9FFF4 KBIO MUX0x3FF4 A0000x3FF4 AFFF4 KBReservedData0x3FF4 B0000x3FF4 BFFF4 KBSDIO SlaveData0x3FF4 C0000x3FF4 CFFF4 KBUDMA10x3FF4 D0000x3FF4 EFFF8 KBReservedData0x3FF4 F0000x3FF4 FFFF4 KBI2S0Data0x3FF5 00000x3FF5 0FFF4 KBUART10x3FF5 10000x3FF5 2FFF8 KBReservedData0x3FF5 30000x3FF5 3FFF4 KBI2C0Data0x3FF5 40000x3FF5 4FFF4 KBUDMA0Low AddressHigh AddressData0x3FF0 0000DataDataDataDataEspressif Systems14CommentPer-CPU peripheralOne of three partsESP32 Technical Reference Manual V1.0
1.3 Functional DescriptionBus Type1 SYSTEM AND MEMORYBoundary AddressSizeTargetComment0x3FF5 5FFF4 KBSDIO SlaveOne of three parts0x3FF5 60000x3FF5 6FFF4 KBRMTData0x3FF5 70000x3FF5 7FFF4 KBPCNTData0x3FF5 80000x3FF5 8FFF4 KBSDIO SlaveData0x3FF5 90000x3FF5 9FFF4 KBLED PWMData0x3FF5 A0000x3FF5 AFFF4 KBEfuse ControllerData0x3FF5 B0000x3FF5 BFFF4 KBFlash Encryption0x3FF5 C0000x3FF5 DFFF8 KBReservedData0x3FF5 E0000x3FF5 EFFF4 KBPWM0Data0x3FF5 F0000x3FF5 FFFF4 KBTIMG0Data0x3FF6 00000x3FF6 0FFF4 KBTIMG10x3FF6 10000x3FF6 3FFF12 KBReservedData0x3FF6 40000x3FF6 4FFF4 KBSPI2Data0x3FF6 50000x3FF6 5FFF4 KBSPI3Data0x3FF6 60000x3FF6 6FFF4 KBSYSCONData0x3FF6 70000x3FF6 7FFF4 KBI2C1Data0x3FF6 80000x3FF6 8FFF4 KBSDMMCData0x3FF6 90000x3FF6 AFFF8 KBEMAC0x3FF6 B0000x3FF6 BFFF4 KBReservedData0x3FF6 C0000x3FF6 CFFF4 KBPWM1Data0x3FF6 D0000x3FF6 DFFF4 KBI2S1Data0x3FF6 E0000x3FF6 EFFF4 KBUART2Data0x3FF6 F0000x3FF6 FFFF4 KBPWM2Data0x3FF7 00000x3FF7 0FFF4 KBPWM30x3FF7 10000x3FF7 4FFF16 KBReserved0x3FF7 50000x3FF7 5FFF4 KBRNG0x3FF7 60000x3FF7 FFFF40 KBReservedLow AddressHigh AddressData0x3FF5 5000DataData184.108.40.206One of three parts
10 AES Accelerator 111 10.1 Introduction 111 10.2 Features 111 10.3 Functional Description 111 10.3.1 AES Algorithm Operations 111 10.3.2 Key, Plaintext and Ciphertext 111 10.3.3 Endianness 112 10.3.4 Encryption and Decryption Operations 114 10
The ESP32 strong series /strong of chips includes ESP32-D0WD-V3, ESP32-D0WDQ6-V3, ESP32-D0WD, ESP32-D0WDQ6, ESP32-D2WD, and ESP32-S0WD, among which, ESP32-D0WD-V3 and and ESP32-D0WDQ6-V3 are based on . strong Espressif /strong Systems 4 Submit Documentation Feedback ESP32 Datasheet V3.3. 1.Overview 1.6 Block Diagram Core and memory ROM Cryptographic hardware acceleration .
1 ESP32-S2-SOLOBlockDiagram 8 2 ESP32-S2-SOLO-UBlockDiagram 8 3 PinLayout(TopView) 9 4 ESP32-S2-SOLOSchematics 18 5 ESP32-S2-SOLO-USchematics 19 6 PeripheralSchematics 20 7 ESP32-S2-SOLOPhysicalDimensions 21 8 ESP32-S2-SOLO-UPhysicalDimensions 21 9 ESP32-S2-SOLORecommendedPCBLandPattern 22 10 ESP32-S2-SOLO-URecommendedPCBLandPattern 23
Figure 1: ESP32-WROOM-32D Pin Layout (Top View) Note: The pin layout of ESP32-WROOM-32U is the same as that of ESP32-WROOM-32D, except that ESP32-WROOM-32U has no keepout zone. 2.2 Pin Description The ESP32-WROOM-32D and ESP32-WROOM-32U have 38 pins. See pin definitions in Table 3. Table
The guidelines outline recommended design practices when developing standalone or add-on systems based on the ESP32-C3 series of products, including ESP32-C3 SoCs, ESP32-C3 modules and ESP32-C3 development . 16 ESP32-C3 Family Stub in a Four-layer PCB Design 20 17 ESP32-C3 Family Crystal Layout 21 18 ESP32-C3 Family RF Layout in a Four-layer .
The ESP32 strong series /strong of chips includes ESP32-D0WDQ6, ESP32-D0WD, ESP32-D2WD, and ESP32-S0WD. For details on part numbers and ordering information, please refer to Part Number and Ordering Information. 1.1 Featured Solutions 1.1.1 Ultra-Low-Power Solution ESP32 is designed for mobile, wearable electronics, and Internet-of-Things (IoT) applications.
15 Nine-Grid Design for EPAD 14 16 ESP32 Power Traces in a Two-layer PCB Design 15 17 ESP32 Crystal Oscillator Layout 16 18 ESP32 RF Layout in a Four-layer PCB Design 17 19 ESP32 RF Layout in a Two-layer PCB Design 17 20 ESP32 Flash and PSRAM Layout 18 21 ESP32 UART Design 18 22 A Typical Touch Sensor Application 19 23 Electrode Pattern .
List of Tables 1 ESP32-WROOM-32D vs. ESP32-WROOM-32U 6 2 ESP32-WROOM-32D and ESP32-WROOM-32U
1.1 ESP32-C3 strong Series /strong of SoCs 1. ESP32-C3 strong Series /strong 1.1. ESP32-C3 strong Series /strong of SoCs Product Name Variants MPN Product Description Flash Size PSRAM Size Antenna Type Temperature Dimensions (mm) SPQ MOQ Production Status Related Product ESP32-C3 Datasheet - - SMD IC ESP32-C3, RISC-V single-core MCU, 2.4G Wi-Fi & BLE 5.0 combo, QFN 32-pin, 5*5 mm, –40 .