PicoGuard XS TM ESD Clamp Array With ESD Protection CM1238
PicoGuard XSTM ESD Clamp Arraywith ESD ProtectionCM1238FeaturesFunctional Description ESD protection for 4 pairs of differential channelsThe PicoGuard XS protection family is specifically designed ESD protection to IEC61000-4-2 Level 4:for next generation deep sub-micron high speed data line 20kV contact dischargeprotection. 25kV air discharge Pass-through impedance matched clampThe CM1238 is ideal for protecting systems with high dataarchitecture)and clock rates or for circuits requiring low capacitiveFlow-through routing for high-speed signalloading and tightly controlled signal skews (with channel-to-integritychannel matching at 2% max deviation).100Ω matched impedance for each paireddifferential channelThe device is particularly well-suited for protecting systems capacitance change with temperature and voltageusing high-speed ports such as DVI or HDMI, along with Each I/O pin can withstand over 1000 ESDcorrespondingstrikes*camcorders, DVD-RW drives and other applications whereRoHS-compliant (lead-free) packagingextremely low loading capacitance with ESD protection are Applications DVI ports, HDMI ports in notebooks, set topboxes, digital TVs, LCD displays General purpose high-speed data line ESDportsinremovablestorage,digitalrequired.The CM1238 also features easily routed "pass-through"pinouts in a RoHS-compliant (lead-free), 16-lead TDFN,small footprint package.protectionBlock DiagramOut 1 Out 1-In 1 In 1-Out 2 Out 2-In 2 In 2-Out 3 Out 3-In 3 In 3-Out 4 Out 4-In 4 In 4-Gnd 100 differentialmatched characteristicimpedance* Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to 8kv contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. 2010 SCILLC. All rights reserved.April 2010 Rev. 2Publication Order Number:CM1238/D
CM1238PicoGuard XS ESD Protection ArchitectureConceptually, an ESD protection device performs the following actions upon an ESD strike discharge into a protected ASIC(see Figure 1):1. When an ESD potential is applied to the system under test (contact or air-discharge), Kirchoff’s Current Law (KCL)dictates that the Electrical Overstress (EOS) currents will immediately divide throughout the circuit, based on thedynamic impedance of each path.2. Ideally, the classic shunt ESD clamp will switch within 1ns to a low-impedance path and return the majority of the EOScurrent to the chassis shield/reference ground. In actuality, if the ESD component's response time (tCLAMP) is slower thanthe ASIC it is protecting, or if the Dynamic Clamping Resistance (RDYN) is not significantly lower than the ASIC's I/Ocell circuitry, then the ASIC will have to absorb a large amount of the EOS energy, and be more likely to fail.3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, and be readyfor an additional strike. Any deterioration in parasitics or clamping capability should be considered a failure, since it canthen affect signal integrity or subsequent protection capability. (This is known as "multi-strike" capability.)In the CM1238 PicoGuard XS architecture, the signal line leading the connector to the ASIC routes through the CM1238 chipwhich provides 100matched differential channel characteristic impedance that helps optimize 100load impedanceapplications such as the HDMI high speed data lines.Note:When each of the channels is used individually for single-ended signal lines protection, the individual channelprovides 50 characteristic impedance matching.The load impedance matching feature of the CM1238 helps to simplify system designer’s PCB layout considerations inimpedance matching and also eliminates associated passive components.The route through the PicoGuard XS architecture enables the CM1238 to provide matched impedance for the signal pathbetween the connector and the ASIC. Besides this function, this circuit arrangement also changes the way the parasiticinductance interacts with the ESD protection circuit and helps reduce the IRESIDUAL current to the ASIC.ESD StrikeESD ESDProtectionPROTECTIONDeviceDEVICEASICI /OConnectorISHUNTIRESIDUALFigure 1. Standard ESD Protection Device Block DiagramRev. 2 Page 2 of 9 www.onsemi.com
CM1238The PicoGuard XS Architecture AdvantagesFigure 2 illustrates a standard ESD protection device.The inductor element represents the parasitic inductancearising from the bond wire and the PCB trace leading toCM1238 Inductor ElementsIn the CM1238 PicoGuard XS architecture, the inductorelements and ESD protection diodes interact differentlythe ESD protection diodes.compared to the standard ESD model. In the standardConnectorESD protection device model, the inductive elementASICpresents high impedance against high slew rate strikevoltage, i.e. during an ESD strike. The impedanceincreases the resistance of the conduction path leading tothe ESD protection element. This limits the speed that theBond WireInductanceESD pulse can discharge through the ESD protectionelement.In the PicoGuard XS architecture, the inductive elementsESDStageare in series to the conduction path leading to theprotected device. The elements actually help to limit thecurrent and voltage striking the protected device.First the reactance of the inductive element, L1, on theconnector side when an ESD strike occurs, acts in theFigure 2. Standard ESD Protection Modelopposite direction of the ESD striking current. This helpslimit the peak striking voltage. Then the reactance of theFigure 3 illustrates one of the channels. Similarly, theinductive element, L2, on the ASIC side forces this limitedinductor elements represent the parasitic inductanceESD strike current to be shunted through the ESDarising from the bond wire and PCB traces leading to theprotection diodes. At the same time, the voltage dropESD protection diodes as well.across both series element acts to lower the clampingvoltage at the protected device terminal.Through this arrangement, the inductive elements alsotune the impedance of the ESD protection element bycancelling the capacitive load presented by the ESDdiodes to the signal line. This improves the signal integrityand makes the overall ESD protection device moretransparent to the high bandwidth data signals passingthrough the channel.The innovative PicoGuard XS architecture turns theFigure 3. CM1238 PicoGuard XS ESD ProtectionModeldisadvantages of the parasitic inductive elements intouseful components that help to limit the ESD currentstrike to the protected device and also improves thesignal integrity of the system by balancing the capacitiveloading effects of the ESD diodes. At the same time, thisarchitecture provides an impedance matched signal pathfor 50Ω loading applications.Rev. 2 Page 3 of 9 www.onsemi.com
CM1238Precision Internal Component MatchingBoard designs can take advantage of precision internalEach ESD channel consists of a pair of diodes in seriescomponent matching for improved signal integrity, notwhich steer the positive or negative ESD current pulse tootherwise possible with discrete components at the systemeither the Zener diode or to ground. This eliminates the needlevel. This simplifies PCB layout considerations andfor a separate bypass capacitor to absorb positive ESDeliminates associated passive components for load matchingstrikes. The CM1238 protects against ESD pulses up tonormally required by standard ESD protection circuits. 20kv contact per the IEC 61000-4-2 standard.Ordering Information1# of PinsPackageOrdering Part NumberPart Marking16TDFNCM1238-08DE1238(yw)2Note 1: Parts are shipped in tape and reel form.Note 2: (yw) is a 2-character datecode.Package/Pin InformationPin DescriptionsPinNameDescription1In 1 Bidrectional Clamp to ASIC (inside system)2In 1-Bidrectional Clamp to ASIC (inside system)3In 2 Bidrectional Clamp to ASIC (inside system)4In 2-Bidrectional Clamp to ASIC (inside system)5In 3 Bidrectional Clamp to ASIC (inside system)6In 3-Bidrectional Clamp to ASIC (inside system)7In 4 Bidrectional Clamp to ASIC (inside system)8In 4-Bidrectional Clamp to ASIC (inside system)9Out 4-Bidrectional Clamp to Connector (outside system)10Out 4 Bidrectional Clamp to Connector (outside system)11Out 3-Bidrectional Clamp to Connector (outside system)12Out 3 Bidrectional Clamp to Connector (outside system)13Out 2-Bidrectional Clamp to Connector (outside system)14Out 2 Bidrectional Clamp to Connector (outside system)15Out 1-Bidrectional Clamp to Connector (outside system)16Out 1 Bidrectional Clamp to Connector (outside system)PADGNDGround return to shieldRev. 2 Page 4 of 9 www.onsemi.com
CM1238Absolute Maximum RatingsPARAMETERRATINGUNITSOperating Temperature Range-40 to 85oCStorage Temperature Range-65 to 150oCBreakdown Voltage (Positive)6Electrical Operating Characteristis(See Note 1)SYMBOL PARAMETERCONDITIONSVINI/O Voltage Relative to GNDIINContinuous Current through signal pins(IN to OUT) 1000 HrIFChannel Leakage CurrentVESDMINoTA 25 C; VN 0V, VTEST 5VoTA 25 C; Note 2oTA 25 C; Note 2IEC 61000-4-2 8kV;oRDUP 5Ω, TA 25 C;Note 2Channel Clamp Voltage(Channel clamp voltage perIEC 61000-4-5 Standard)Positive TransientsNegative TransientsIPP 1A, TA 25 C,tP 8/20µs;Note 2Dynamic ResistancePositive TransientsNegative TransientsIPP 1A, TA 25 CtP 8/20µs;Note 2ZoDifferential Channels pair characteristicimpedance ZoRDYNZCHANNEL ZCHANNELMAXUNITS5.5V100Residual ESD Peak Current on RDUP(Resistance of Device Under Protection)VCLTYP-0.5ESD Protection - Peak Discharge Voltageat any channel input, in system:a) Contact discharge perIEC 61000-4-2 Standardb) Air discharge per IEC 61000-4-2StandardIRESV0.1mA1.0µAkVkV 20 253.8A 10-1.9VV2.00.7ΩΩTR 200ps;Note 2100ΩChannel-to-Channel Impedance Match(Differential)TR 200ps;Note 22%Individual Channel CharacteristicImpedance in Single-ended ConnectionTR 200ps50ΩChannel-to-Channel Impedance Match(Individual)TR 200ps;Note 22%ooNote 1: All parameters specified at TA –40 oC to 85 oC unless otherwise noted.Note 2: This parameter is guaranteed by design and verified by device characterizationRev. 2 Page 5 of 9 www.onsemi.com
CM1238Performance InformationGraphical Comparison and Test SetupFigure 4. shows that the CM1238 lowers the peak voltage and clamping voltage by more than 60% across a wide range ofloading conditions in comparison to a standard ESD protection device. Figure 5. also indicates that the DUP/ASIC protectedby the CM1238 dissipates less power than a standard ESD protection device. This data was derived using the test setupsshown in Figure 6.Figure 4. Normalized VPeak (8KV IEC-61000 4-2 ESD Contact Strike) vs. Loading (RDUP)*Figure 5. Normalized Residual Current into DUP vs. RDUP**RDUP is the emulated Dynamic Resistance (load) of the Device Under Protection (DUP). See Figure 6.Rev. 2 Page 6 of 9 www.onsemi.com
CM1238Figure 6. Test Setups: Standard Device (Left) and CM1238 (Right)CM1238 Application and GuidelinesAs a general rule, the CM1238 ESD protection array should be located as close as possible to the point of entry of expectedelectrostatic discharges with minimum PCB trace lengths to the ground planes and between the signal input and the ESDdevice to minimize stray series inductance.Figure 7. Application of Positive ESD Pulse Between Input Channel and GroundFigure 8. Typical PCB LayoutRev. 2 Page 7 of 9 www.onsemi.com
CM1238Package DimensionsTDFN-16 EEP Mechanical Specifications, 0.5mmThe 0.5mm pitch TDFN package dimensions withExposed End Pads (EEP) are presented 300.031A10.000.020.050.0000.0010.0020.20 REFA30.008 00.0590.0630.067E20.300.400.500.0120.0160.020e0.50 BSC0.020 BSCF0.25 REF0.010 REFK0.30 REF0.012 REFL# pertape andreel0.200.300.400.0080.0120.0163000 piecesControlling dimension: millimetersDimensions for 16-Lead, 0.5mm pitch TDFN pckagewith Exposed End Pads (EEP)*This package is compliant with JEDEC standard MO229C with the exception of the D, D2, E, E2, K and Ldimensions as called out in the table above.Rev. 2 Page 8 of 9 www.onsemi.com
CM1238Tape and Reel SpecificationsPART NUMBERPACKAGE SIZE(mm)POCKET SIZE (mm)B0 X A0 X K0TAPE WIDTHWREELDIAMETERQTY PERREELP0P1CM1238-08DE4.00 X 1.60 X 0.754.30 X 1.90 X 1.2012mm178mm (7")30004mm4mmON Semiconductor andare registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to anyproducts herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arisingout of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operatingparameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor therights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase oruse SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributorsharmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with suchunintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative ActionEmployer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATIONLITERATURE FULFILLMENT:FULFILLMENTLiterature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone:Phone 303-675-2175 or 800-344-3860 Toll Free USA/CanadaFax:Fax 303-675-2176 or 800-344-3867 Toll Free USA/CanadaEmail:Email orderlit@onsemi.comN. American Technical Support:Support 800-282-9855Toll Free USA/CanadaEurope, Middle East and Africa TechnicalSupport:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81-3-5773-3850Rev. 2 Page 9 of 9 www.onsemi.comON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representative
Bond Wire Inductance Connector ASIC Figure 2. Standard ESD Protection Model Figure 3 illustrates one of the channels. Similarly, the inductor elements represent the parasitic inductance arising from the bond wire and PCB traces leading to the ESD protection diodes as well. Figure 3. CM1238 P
BC1 Page 41 BEAM CLAMP BD1 Page 41 BEAM CLAMP BF1 Page 42 BEAM CLAMP BG1 Page 42 BEAM CLAMP BH1 Page 42 BEAM CLAMP BF2 Page 42 BEAM CLAMP BG2 Page 42 BEAM CLAMP BL FLANGE CLAMP Page 43 GRATE FIX Page 44 BEAM CLAMP GRATING CLIP Page 45 BEAM CLAMP FLOORFIX HT Page 46 FLOORFIX Page
An Electrostatic Discharge (ESD) safe work area and proper ESD handling procedures (that conform to ANSI/ESD S20.20 -1999 or ANSI/ ESD S20.20-2007) are mandatory to avoid ESD damage when handling subassemblies or components found in the MS2717A. Additional information pertaining to ESD can be found at the ESD Association Web site:
ANSI/ESD STM97.2 100 volts ESD TR53 Footwear Section 1.0 x 109 ohms S20.20 -2007 TABLE 3. EPA ESD Control Items Technical Requirement ESD Control Item Product Qualification1 Compliance Verification Test Method Required Limit(s)2 Test Method Required Limit(s) EPA Worksurface ANSI/ESD S 4.1 and/or ANSI/ESD STM 4.2 1 x 109 ohms and/or 200
ANSI/ESD S20.20 (a complimentary.pdf copy can be downloaded at no charge from the ESD Association website ESDA.org. Also, other documents such as the ESD Handbook ESD TR20.20 can be purchased). “The 100 volt HBM limit was selected for ANSI/ESD S20.20 as the baseline susceptibility threshold since a large majority of the ESD
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1 IEC 61000-4-2 System ESD Immunity 1.1 IEC61000-4-2 Overview The IEC 61000-4-2 standard covers system level ESD immunity. Electrostatic Discharge can be very harmful to a system and even a small amount of voltage can damage components. Most systems require some sort of IEC ESD protection, as any user accessible areas can be subjected to ESD .
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