A Guide To Digital Design And Synthesis Samir Palnitkar

Verilog HDLA Guide to Digital Designand SynthesisSamir PalnitkarSunSoft PressA Prentice Hall Title

Table of ContentsAbout the viiPart1: Basic Verflog Topics1. Overview of Digital Design with Verflog HDL1.11.21.31.41.51.6Evolution of Computer Aided Digital DesignEmergence of HDLsTypical Design FlowImportance of HDLsPopularity of Verilog HDLTrends in HDLs2. Hierarchical Modeling Concepts2.1 Design Methodologies2.2 4-bit Ripple Carry Counter2.3 Modules2.4 Instances2.5 Components of a Simulation2.6 Example2.6.1 Design Block2.6.2 Stimulus Block2.7 Summary2.8 Exercises3. Basic Concepts3.1 Lexical Conventions3.1.1 Whitespace3.1.2 Comments3.1.3 ii

3.1.4 Number SpecificationSized numbersUnsized numbersX or Z valuesNegative numbersUnderscore characters and question marks3.1.5 Strings3.1.6 Identifiers and Keywords3.1.7 Escaped Identifiers3.2 Data Types3.2.1 Value Set3.2.2 Nets3.2.3 Registers3.2.4 Vectors3.2.5 Integer , Real, and Time Register Data TypesIntegerRealTime3.2.6 Arrays3.2.7 Memories3.2.8 Parameters3.2.9 Strings3.3 System Tasks and Compiler Directives3.3.1 System TasksDisplaying InformationMonitoring InformationStopping and finishing in a Simulation3.3.2 Compiler Directives"define'include3.4 Summary3.5 Exercises4. Modules and Ports474.1 Modules4.2 Ports4.2.1 List of Ports4.2.2 Port Declaration4.2.3 Port Connection 737383838404142424343444751515253Verilog HDL: A Guide to Digital Design and Synthesis

InputsOutputsInoutsWidth matchingUnconnected portsExample of illegal port connection4.2.4 Connecting Ports to Extemal SignalsConnecting by ordered listConnecting ports by name4.3 Hierarchical Names4.4 Summary4.5 Exercises5. Gate-Level Modeling535454545454555556575859615.1 Gate Types5.1.1 And/Or Gates5.1.2 Buf/Not GatesBufif/notif5.1.3 ExamplesGate-level multiplexer4-bit füll adder5.2 Gate Delays5.2.1 Rise, Fall, and Tum-off DelaysRise delayFall delayTurn-off delay5.2.2 Min/Typ/Max ValuesMin valueTyp valMax value5.2.3 Delay Example5.3 Summary5.4 Exercises6. Dataflow 1 Continuous Assignments6.1.1 Implicit Continuous Assignment6.2 Delays6.2.1 Regulär Assignment DelayTable of Contents86878888ix

6.2.2 Implicit Continuous Assignment Delay6.2.3 Net Declaration Delay6.3 Expressions, Operators, and Operands6.3.1 Expressions6.3.2 Operands6.3.3 Operators6.4 Operator Types6.4.1 Arithmetic OperatorsBinary OperatorsUnary Operators6.4.2 Logical Operators6.4.3 Relational Operators6.4.4 Equality Operators6.4.5 Bitwise Operators6.4.6 Reduction Operators6.4.7 Shift Operators6.4.8 Concatenation Operator6.4.9 Replication Operator6.4.10 Conditional Operator6.4.11 Operator Precedence6.5 Examples6.5.1 4-to-l MultiplexerMethod 1: logic equationMethod 2: conditional Operator6.5.2 4-bit Füll AdderMethod 1: dataflow OperatorsMethod 2: füll adder with carry lookahead6.5.3 Ripple Counter6.6 Summary6.7 Exercises7. Behavioral Modeling1157.1 Structured Procedures7.1.1 initial Statement7.1.2 always Statement7.2 Procedural Assignments7.2.1 Blocking assignments7.2.2 Nonblocking AssignmentsApplication of nonblocking assignments7.3 Timing 01102102102103104104105106112112Verilog HDL: A Guide to Digital Design and Synthesis116116118119119120122124

7.3.1 Delay-Based Timing ControlRegulär delay controlIntra-assignment delay controlZero delay control7.3.2 Event-Based Timing ControlRegulär event controlNamed event controlEvent OR control7.3.3 Level-Sensitive Timing Control7.4 Conditional Statements7.5 Multiway Branching7.5.1 case Statement7.5.2 casex, casez Keywords7.6 Loops7.6.1 While Loop7.6.2 For Loop7.6.3 Repeat Loop7.6.4 Forever loop1.1 Sequential and Parallel Blocks7.7.1 Block TypesSequential blocksParallel blocks7.7.2 Special Features of BlocksNested blocksNamed blocksDisabling named blocks7.8 Examples7.8.1 4-to-l Multiplexer7.8.2 4-bit Counter7.8.3 Traffic Signal ControllerSpecificationVerilog descriptionStimulus7.9 Summary7.10 Exercises8. Tasks and Functions8.1 Differences Between Tasks and Functions8.2 TasksTable of 47149151153154157157158xi

8.2.1 Task Declaration and Invocation8.2.2 Task ExamplesUse of input and output argumentsAsymmetrie Sequence Generator1618.3 Functions8.3.1 Function Declaration and Invocation8.3.2 Function ExamplesParity calculation162162163164Left/right shifter1658.4 Summary8.5 Exercises1661669. Useful Modeling Techniques1699.1 Procedural Continuous Assignments9.1.1 assign and deassign9.1.2 force and releaseforce and release on registers169169171171force and release on nets1729.2 Overriding Parameters9.2.1 defparam Statement9.2.2 Module Instance Parameter Values9.3 Conditional Compilation and Execution9.3.1 Conditional Compilation9.3.2 Conditional Execution9.4 Time Scales9.5 Useful System Tasks9.5.1 File OutputOpening a file172172173175175176177179179179Writing to files180Closing files1809.5.2 Displaying Hierarchy9.5.3 Strobing9.5.4 Random Number Generation9.5.5 Initializing Memory from File9.5.6 Value Change Dump File9.6 Summary9.7 Exercisesxii159160160Verilog HDL: A Guide to Digital Design and Synthesis181182182183185186188

Part2:Advanced Verilog Topics10. Timing and Delays19119310.1 Types of Delay Models10.1.1 Distributed Delay10.1.2 Lumped Delay10.1.3 Pin-to-Pin Delays10.2 Path Delay Modeling10.2.1 Specify Blocks10.2.2 Inside Specify BlocksParallel connectionFüll connectionspecparam StatementsConditional path delaysRise, fall, and turn-off delaysMin, max, and typical delaysHandling x transitions10.3 Timing Checks10.3.1 setup and hold checks setup task hold task10.3.2 width Check10.4 Delay Back-Annotation10.5 Summary10.6 Exercises11. Switch-Level 20520620620720720821021121311.1 Switch-Modeling Elements11.1.1 MOS Switches11.1.2 CMOS Switches11.1.3 Bidirectional Switches11.1.4 Power and Ground11.1.5 Resistive Switches11.1.6 Delay Specification on SwitchesMOS and CMOS SwitchesBidirectional pass switchesSpecify blocks11.2 Examples11.2.1 CMOS Nor GateTable of Contents213214215216217218219219220220220220xiii

11.2.2 2-to-l Multiplexer11.2.3 Simple CMOS Flip-Flop11.3 Summary11.4 Exercises22322422622712. User-Defined Primitives12.1 UDP basics12.1.1 Parts of UDP Definition12.1.2 UDP Rules12.2 Combinational UDPs12.2.1 Combinational UDP Definition12.2.2 State Table Entries12.2.3 Shorthand Notation for Don't Cares12.2.4 Instantiating UDP Primitives12.2.5 Example of a Combinational UDP12.3 Sequential UDPs12.3.1 Level-Sensitive Sequential UDPs12.3.2 Edge-Sensitive Sequential UDPs12.3.3 Example of a Sequential UDP12.4 UDP Table Shorthand Symbols12.5 Guidelines for UDP Design12.6 Summary12.7 224424524624713. Programming Language Interface13.1 Uses of PLI13.2 Linking and Invocation of PLI Tasks13.2.1 Linking PLI TasksLinking PLI in Verilog-XLLinking in VCS13.2.2 Invoking PLI Tasks13.2.3 General Flow of PLI Task Addition and Invocation13.3 Internal Data Representation13.4 PLI Library Routines13.4.1 Access RoutinesMechanics of access routinesTypes of access routinesExamples of access routines13.4.2 Utility RoutinesMechanics of Utility 268268xivVerilog HDL: A Guide to Digital Design and Synthesis

Types of Utility routinesExample of Utility routines13.5 Summary13.6 Exercises14. Logic Synthesis with Verilog HDL14.1 What Is Logic Synthesis?14.2 Impact of Logic Synthesis14.3 Verilog HDL Synthesis14.3.1 Verilog Constructs14.3.2 Verilog Operators14.3.3 Interpretation of a Few Verilog ConstructsThe assign StatementThe if-else StatementThe case Statementfor loopsThe function statement14.4 Synthesis Design Flow14.4.1 RTL to GatesRTL descriptionTranslationUnoptimized intermediate representationLogic optimizationTechnology mapping and optimizationTechnology libraryDesign constraintsOptimized gate-level description14.4.2 An Example of RTL-to-GatesDesign specificationRTL descriptionTechnology libraryDesign constraintsLogic synthesisFinal, Optimized, Gate-Level DescriptionIC Fabrication14.5 Verification of Gate-Level Netlist14.5.1 Functional VerificationTiming verificationTable of 3293293296296296299xv

14.6 Modeling Tips for Logic Synthesis14.6.1 Verflog Coding StyleUse meaningful names for Signals and variablesAvoid mixing positive and negative edge-triggered flip-flopsUse basic building blocks vs. Use continuous assign StatementsInstantiate multiplexers vs. Use if-else or case StatementsUse parentheses to optimize logic structureUse arithmetic Operators *, / , and % vs. Design building blocksBe careful with multiple assignments to the same variableDefine if-else or case Statements explicitly14.6.2 Design PartitioningHorizontal partitioningVertical PartitioningParallelizing design structure14.6.3 Design Constraint Specification14.7 Example of Sequential Circuit Synthesis14.7.1 Design Specification14.7.2 Circuit Requirements14.7.3 Finite State Machine (FSM)14.7.4 Verflog Description14.7.5 Technology Library14.7.6 Design Constraints14.7.7 Logic Synthesis14.7.8 Optimized Gate-Level Netlist14.7.9 Verification14.8 Summary14.9 ExercisesPart3: Appendices319A. Strength Modeling and Advanced Net DefinitionsA.l Strength LevelsA.2 Signal ContentionA.2.1 Multiple Signals with Same Value and Different StrengthA.2.2 Multiple Signals with Opposite Value and Same StrengthA.3 Advanced Net TypesA.3.1 triA.3.2 5306306306306307307310311311311314316317Verilog HDL: A Guide to Digital Design and Synthesis321321322322322322322323

A.3.3 triO and trilA.3.4 supplyO and supplylA.3.5 wor, wand, trior, and triandB. List of PLI Routines327B.l ConventionsB.2 Access RoutinesB.2.1 Handle RoutinesB.2.2 Next RoutinesB.2.3 Value Change Link (VCL) RoutinesB.2.4 Fetch RoutinesB.2.5 Utility Access RoutinesB.2.6 Modify RoutinesB.3 Utility (tfJ RoutinesB.3.1 Get Calling Task/Function InformationB.3.2 Get Argument List InformationB.3.3 Get Parameter ValuesB.3.4 Put Parameter ValueB.3.5 Monitor Parameter Value ChangesB.3.6 Synchronize TasksB.3.7 Long ArithmeticB.3.8 Display MessagesB.3.9 Miscellaneous Utility RoutinesB.3.10 Housekeeping TasksC. List of Keywords, System Tasks, and Compiler DirectivesC.l KeywordsC.2 System Tasks and FunctionsC.3 Compiler DirectivesD. Formal Syntax 343344344345Source TextDeclarationsPrimitive InstancesModule InstantiationsBehavioral StatementsSpecify SectionExpressions346349351352353355359Table of Contentsxvii

D.8 General361E. Verilog TidbitsOrigins of Verilog HDLOpen Verilog International (OVI)Interpreted, Compiled, Native Compiled SimulatorsEvent-Driven Simulation, Oblivious SimulationCycle-Based SimulationFault SimulationVerilog NewsgroupVerilog FTP SiteVerilog SimulatorsVerilog Related Mosaic Sites363363363363364364364364365365365F. Verilog ExamplesEl Synthesizable FIFO ModelInput portsOutput portsF.2 Behavioral DRAM ModelInput portsInout xviiiVerilog HDL: A Guide to Digital Design and Synthesis

x Verilog HDL: A Guide to Digital Design and Synthesis . 7.3.1 Delay-Based Timing Control 124 Regulär delay control 125 Intra-assignment delay control 126 Zero delay control 127 7.3.2 Event-Based Timing Control 127 Regulär event control 128 Named event control 128 Event OR control 129