Copyright 2017 California Institute Of Technology Government .
byReza Ghaffarian, Ph.D.NASA-JPL-CalTech(818) 354-2059Reza.Ghaffarian@JPL.NASA.govCopyright 2017 California Institute of TechnologyGovernment sponsorship acknowledgedNEPP Electronics Technology Workshop (ETW 2017)June 26-29,2017, NASA GSFChttp://nepp.nasa.gov
QFN TC ReliabilityBest Practices andGuidelines Test, usage, screening,qualification Radiation facility studiesNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
Outline Single Packaging Trends QFN use projections QFN Packages/Assemblies Various sizes and I/OsTin-lead and Pb-free on ENIG PCB finishX-ray/Optical evaluation Thermal Shock Cycles (TSC) 200 TSC1 (-55 C/100 C) 1000 TSC2 (-55 C/125 C) Age at 125 C for 250 hour plus TSC2 Failure analyses by X-section SummaryNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
Single Chip PackagingPBGA/SOCQFN/MLFWire bond to Flip ChipCBGA to CCGACSP / WLPa/M/WQFN/LGAPBGACBGAWaferLevelPackagingChip ScalePackaging(CSP)Multi-rowQFNQFN2116 FCBGAASICNEPP ETW- 2017LGAReza Ghaffarian/JPL/Caltech
OFN CAAGR to 2026NEPP ETW- 2017Source iNEMI 2015 & 2017Reza Ghaffarian/JPL/Caltech
OFN CAAGR to 2026NEPP ETW- 2017Source iNEMI 2015 & 2017Reza Ghaffarian/JPL/Caltech
QFN CubeSatRef: M. Sundgaard, ETW2016NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
QFN TrendsMicroLead Frame NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
QFN AssembliesNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
QFN TypesNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech10
NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
QFNs-Thermal ShockCycle (TSC1)NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
QFNs-TSC2NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
QFN Failure 1116 TSC2SnPb No AgingFail Under Thermal CyclingNEPP ETW- 2017No Part or Fail As ReceivedReza Ghaffarian/JPL/Caltech
QFN Failure 1116 TSC2SnPb with Pre-AgingFail Under Thermal CyclingNEPP ETW- 2017No Part or Fail As ReceivedReza Ghaffarian/JPL/Caltech
NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
MLF68-10mmNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
MLF28-7mmNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
Summary Released NEPP report No failure to 200 TC cycles (–55 /100 C) Assemblies with tin-lead solder Cycling stopped @ 200 A large number of failures for MLF 68 I/O 1166 thermal shock cycles only (–55 to 125 C) 250 hours age at 125 C & 1166 TSC cycles. Pre-aged had lower failures X-sections confirmed daisy-chain results MLF68 showed full cracking MLF28 showed only minor microcracking COTS QFNs to 68 I/Os are robustNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
TMV/TSV TC ReliabilityGuidelineTest ResultsNEWNEPP TASKBest Practices andGuidelines Test, usage, screening,qualification Radiation facility studiesNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
Electronics RoadmapiNEMI : ITRS to IRDS (device & system) Re-stores Defense/Aerospace Data centers as utilities & clouds as “rent vs.buy” Assembly to lower cost/temp Pb-free The “IoT”, sensors ubiquitous- cyber-attacks? Portables shift to “wearables” Auto safety systems to proliferate Remote patient care, proactive/preventiveNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
Packaging as Enabler ofMoore’s Law Scaling Historically Silicon growth by Moore’s law Packaging supporting role Packaging focused on powering performance and siliconlatency Now, Packaging is differentiator Wafer level package (WLP), fan-in & fan-out Embedded passive/active System on package (SoP), System in package (SiP), andHeterogeneous integration (HI) Complex products: SiP (2.5D & 3D) Through-silicon-via (TSV) to compete with optical on chipNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
2.5D/3D PackagingStack DiePoPPackage on Package (PoP)2D to 2.5 DSingle Chip to Multi-chipTSV for Interposer2.5D to 3DTSV3D SIP3D Wafer-level Packaging3D Wire BondThrough-silicon Via3DNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
TMV/TSV PackagingEvaluationTMV2.5 DSIP3D TSVThrough Mold Via (TMV)3D Wafer-level PackagingNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
TMV/TSV PackagingStatusTMV2.5 DSIP3D TSVThrough Mold Via (TMV)NEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
TMV/TSV PackagingStatus3D TSVNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
NEPP TMV/TSV Challenges package/2nd Level Reliability Availability of COTS packages Assembly challenges/Reliability testing Through mold via (TMV) stack Packages/PCBs are ready to assemble 2.5D (Joint effort Univ/Industry) First article built successfullyAdditional build and Reliability Daisy-chain TSV Concept is finalized Numerous options Select & evaluate assembly/reliabilityNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
The research described in this publication is being conducted at the Jet Propulsion Laboratory, California Institute ofTechnology, under a contract with the National Aeronautics and Space Administration. Copyright 2017 CaliforniaInstitute of Technology. U.S. Government sponsorship acknowledged.The author would like to acknowledge the support of the JPL team and industry partners. The author also extendshis appreciation to the program managers of the National Aeronautics and Space Administration Electronics Partsand Packaging (NEPP) Program.http://nepp.nasa.govNEPP ETW- 2017Reza Ghaffarian/JPL/Caltech
qualification Radiation facility studies . SnPb with Pre -Aging. NEPP ETW - 2017. Reza Ghaffarian/JPL/Caltech. NEPP ETW - 2017. Reza Ghaffarian/JPL/Caltech. MLF68-10mm. NEPP ETW - 2017. Reza Ghaffarian/JPL/Caltech. MLF28-7mm. . The author would like to acknowledge the support of the JPL team and industry partners. The author also extends
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