A3M36SL039 3400-3800 MHz, 29 DB, 8 W Avg Data Sheet

Power supply sequenceTable 11. Register overview and bit description y OTPAttributeEMModeNot availableN/AN/AN/ANo0–5Sense DAC B 6-bit logic value forpeaking amplifiers. DAC B sets thereference voltage to compare to theVDS across the reference device.Minimum typical value is 6'b001000and maximum value is 6'b111111.Recommendation is that the value inthis register be set higher than6'b010000.6'h20YesRWYesRegisterNameBitB Sense DAC6–7Bit Descriptions25B VGS3 DAC0–7Sets 8-bit DAC logic value forpeaking driver stage. 8'h00 sets gateto equal ceiling voltage. 8'hFFreduces gate voltage by a maxvalue.8'h806B VGS4 DAC0–7Sets 8-bit DAC logic value forpeaking final stage. 8'h00 sets gateto equal ceiling voltage. 8'hFFreduces gate voltage by a maxvalue.8'h807–14ReservedN/ANot availableN/AN/AN/ANo15Temp ADC0–7Temperature sensor 8-bit DACvalue. 8'h00 is lowest temperature,8'hFF is highest temperature.8'h00NoRNo16ReservedN/ANot availableN/AN/AN/ANo17EM Passcode0–7Engineering Mode (EM). By writing8'hE3 to this register the user canenter engineering mode. EM can becleared by writing any other code tothis register. In EM registersidentified in EM mode column can bechanged.N/ANoWYes1.2.4At power on or reset, OTP values set by NXP are automatically loaded into registers indicated with a “Yes” in the“Overwritten by OTP” column. For these registers, values shown in the “Power On/Reset Value column” will be loadedonly if OTP has not been programmed to prevent damage to the device.Register can be read at any time. Can write to register only when in Engineering Mode (EM).Power supply sequencePower Up Sequence1.VCC 5V: 5 V power up2.SPI/I2C interface is active3.VDP1,VDP2,VDC1,VDC2 power upA3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data10 / 33

Autobias functionalityPower Down Sequence1.VDP1,VDP2,VDC1,VDC2 power down2.SPI/I2C interface deactivated3.VCC 5V: 5 V power downNote: All digital interfaces (SDA, SCLK, CS B,Tx EN) are 1.8 V logic.55.1Autobias functionalityGeneral overviewAfter power up, the integrated bias controller develops and applies a thermally compensated quiescent bias voltage to the gateof each of the four RF transistors contained within the power amplifier module (PAM) based on the preset OTP values. SeeSection 3.1 for more information on the OTP memory. This achieves optimal RF performance over the full temperature range.The standard SPI or I2C interface can be used to read the temperature sensor and overwrite preset DAC values. The devicecan be used without the programming interface. The thermal compensation circuit is analog and not programmable; however,the preset DAC values can be overwritten to provide an alternate thermal compensation scheme via the SPI or I2C interface.This section describes the operation and programming of the bias controller.5.2Operational overviewFigure 2 shows a detailed view of the carrier side (Group A) autobias controller. The peaking side (Group B) controller is aduplicate of the carrier; however, the RF transistor peripheries and quiescent operating points will be different as required bythe Doherty operation. The module contains four RF LDMOS field-effect transistors (FET) consisting of a driver and final forthe carrier amplifier (on a single IC die) and a driver and final for the peaking amplifier (on a single IC die). Each IC die alsocontains a small periphery reference FET that is designed to match the properties of the larger RF transistors with regard topart-to-part process and temperature-dependent variations. The bias controller interfaces with each of the RF FETs andprovides flexibility to control the biasing of each transistor independently.The bias controller operates by establishing a known current through the reference FET typically in the range of 1 2 mA perreference FET. This in turn establishes a gate-source operating voltage by sensing the voltage drop across an integrated, hightolerance resistor placed between VCC (5 V) and the reference device drain terminal. The bias controller VCC 5V pin shouldbe operated from a 5 V supply with tolerance of 5%. The reference voltage across the precision resistor R1 is compared to avoltage programmed in the bias controller (A Sense DAC and B Sense DAC), thereby providing fine incremental adjustmentto the default bias current of the reference FET. Because the reference FET and RF FET are manufactured on the same die inclose proximity, they exhibit similar process and temperature dependencies.A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data11 / 33

Autobias functionalityFigure 2. Block diagram of carrier (A) autobias functionality. Peaking (B) autobias functionality is identical.The initial bias condition is set via the A Sense DAC register. The bias condition is then sensed and adjusted as temperaturechanges via the closed-loop feedback. The feedback mechanism adjusts the DAC ceiling voltage to maintain a constant IDScurrent through the reference FET. The temperature compensated DAC ceiling voltage can either be passed to the carrier PAfinal and carrier PA driver directly, or reduced by values set in the A VGS1 DAC and A VGS2 DAC to the DAC floor voltage.5.3Tx enable controlA 1.8 V JEDEC compliant enable signal (Tx EN) is included for bias On/Off operation to support TDD operation. The controllerprovides capability to quickly switch the RF FETs between ON and OFF modes in less than 100 ns. With Tx EN in an ONstate, the RF FET gate terminals are internally decoupled with sufficient capacitance providing a low impedance for widebaseband signals. The large capacitance also serves as a charge holding cap for reducing switching transient time in TDDoperation. In Tx OFF mode, RF FET device gates are grounded shutting them OFF.Table 12. TX EN Off-State Typical CurrentsCharacteristicTypical ValueUnitVCC 5V Supply Current11mACombined Drain Supply Currents (VDC1, VDC2, VDP1, VDP2)20μA5.4Sense DACThe current in the reference FET is controlled and programmed with 6 bits (two MSBs of the 8-bit register are not used) via thesense DAC (A Sense DAC and B Sense DAC). By programming the sense DAC, the RF stage DAC ceiling voltagereference operating point can be optimally set. The DAC ceiling voltage reference point impacts both RF PA stages (driver andfinal) simultaneously. After OTP has been programmed, the Sense DAC is loaded with the programmed values and are thenonly programmable in Engineering Mode.The factory programmed values for A Sense DAC and B Sense DAC are decimal 30 and 34 respectively. These valueshave been optimized for best power, linearity and efficiency tradeoffs.A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data12 / 33

Ordering information5.5VGS DACThe VGS DAC voltage is determined via the Sense DAC setting, creating the top end or ceiling of the VGS DAC voltagerange and a fixed offset voltage creating the bottom end or floor of the VGS DAC voltage range. With a decimal VGS DACsetting of 0, the gate voltage developed on the reference FET is buffered with minimum offset to the gates of the RFtransistors in the carrier amplifier. As the VGS DAC value increases, the voltage applied to the gates of the RF transistorsdecreases, which also reduces IDQ. This allows the operating point of the four RF devices to be set to any desired value, fromClass AB to Class C.The reference FETs and RF FETs exhibit approximately the same current density (that is, IDQ/mm gate width). It is important tonote that, because the reference device and RF transistors are manufactured on the same die in close proximity, they exhibitsimilar process and temperature dependencies. Both the peaking amplifier and the carrier amplifier operate in the same waywith regard to the reference device and the RF transistors.5.6Engineering Mode (EM)Flexibility exists to overwrite the OTP memory values, if needed. A special Engineering Mode (EM) is available to allow theuser to overwrite data that has been placed into the OTP memory space. To enter EM, issue the write address d’17 commandwith the predefined EM passcode (see Table 10). After entering EM, all DAC OTP registers (address 1–6) can be overwrittenwith the normal I2C/SPI write instruction. This interface programmed value will be valid so long the VCC supply power ismaintained. The VCC power cycle will load OTP programmed DAC settings again. If the user writes the address d’17 registerwith any value other than the passcode, EM will automatically exit.6Ordering informationTable 13. Ordering informationDeviceTape and Reel 2 Suffix 2,000 Units, 24 mm Tape Width, 13-inch ReelI2 C10 mm 8 mm ModuleA3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data13 / 33

Component layout and parts list77.1Component layout and parts listComponent layoutFigure 3. A3M36SL039 reference circuit component layoutA3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data14 / 33

Temperature sensorComponent designations and values7.2Table 14. A3M36SL039 reference circuit component designations and valuesPartDescriptionPart NumberManufacturerB130 Ω Ferrite BeadBLM15PD300SN1MurataC1, C2, C14, C1510 µF Chip CapacitorGRM31CR61H106KA12MurataC4, C10, C121 µF Chip CapacitorGRM188R61H105KAALMurataC171000 pF Chip CapacitorGRM022R71A102KA12LMurataC18220 µF, 50 V Electrolytic CapacitorUUJ1H221MNQ1MSNichiconL113 nH Chip InductorLQW15AN13NG80DMurataQ1Power Amplifier ModuleA3M36SL039NXPR10 Ω, 1/8 W Chip ResistorCRCW08050000Z0EAVishayPCBRogers RO4350B, 0.020″, εr 3.66D139037MTLNote: Component numbers C3, C5, C6, C7, C8, C9, C11, C13 and C16 are intentionally omitted.8Temperature sensorThe temperature value is converted from the 8-bit temperature sense ADC value (stored in the Temp ADC register) via thefollowing equation.Temperature ( C) (0.67798 Temp ADC) – 36.64A plot of this equation is shown in Figure 4.Figure 4. Die temperature versus ADC codeTable 15. Temperature sensor accuracyCharacteristicValueUnitOperating Die Temperature, TJ 25 C to 125 C 3 COperating Die Temperature, TJ –35 C to 125 C 5 CA3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data15 / 33

Communication interfaces9Communication interfacesThe A3M36SL039 device contains a digital interface that supports either a 3-pin SPI or 2-pin I2C interface. The digital interfaceis used to both read and write data to and from the device. The preferred interface type must be set at the factory prior toshipment. For I2C functionality, order part number A3M36SL039I. For SPI functionality, order part number A3M36SL039S.9.1SPIThe A3M36SL039S can be programmed and the Tx bias settings and temperature read through the 3-pin SPI interface.9.1.1SPI timing diagramThe SPI interface timing of A3M36SL039S complies with SPI mode3 as shown in Figure 5.Figure 5. Serial interface timing diagramTable 16. Serial interface timing specificationSymbolParameterMin (ns)tSCSetup timing requirement of CS B (both rising and falling) in relation to the rising edge of SCLK50tWHclk high duration160tWLclk low duration160tSDDate to clock rising edge setup20tHDclk rising edge to data hold time20tHCclk to CS B hold time50tWH tWLMinimum clock period4009.1.2SPI instruction set definitionThe SPI instruction set is determined by the first byte after releasing the CS B signal. The order of SPI instruction is MSB sentfirst, LSB sent last. Bit 7 of the SPI instruction set is defined as read (1) or write (0) command. Bits 6 5 define the burst widthin the range of 1 4 bytes: 00 is for 1 byte data, 01 for 2 bytes data, 10 for 3 bytes data and 11 is for 4 bytes data. Bits 4 0 aredefined as the register address that is to be accessed.A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data16 / 33

Communication interfacesFigure 6. SPI instruction sets diagramSPI instruction set information: 9.2R/W read 1, write 0N1, N0o 2’b00 1 byteo 2’b01 2 byteso 2’b10 3 byteso 2’b11 4 bytesA4, A3, A2, A1, A0 decode for address 0–15MSB sent first, LSB lastI2CThe A3M36SL039I follows the I2C protocol standard. It supports I2C fast mode with a bit rate up to 400 Kbit/s. It also supportsI2C standard mode with bit rate up to 100 Kbit/s.9.2.1I2C addressingThe two external tri-state address pins A0 and A1 use 5 V logic levels and are decoded into 7-bit I2C addresses as shownin Table 17. The three LSBs of the 7-bit address are set via the A0 and A1 pins. The four MSBs are the base address, which isfixed at 1000.Table 17. I2C 7-bit address assignmentA1A0I2C 7-Bit Address00Not Translated0Z1000 000011000 001Z01000 010ZZ1000 011Z11000 100101000 1011Z1000 110111000 111A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data17 / 33

Communication interfaces9.2.2I2C instruction setI2C Write instructionFigure 7. I2C Write instructionI2C Read instructionFigure 8. I2C Read instructionA3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data18 / 33

Communication interfacesI2C Write and Read combination sequenceFigure 9. I2C Write and Read combination sequence9.2.3I2C Device ID Read instructionThe Device ID is read only, hardwired in the device and can be accessed as follows:1.START condition2.The leader sends the Reserved Device ID I2C bus address followed by the R/W bit set to ‘0’ (write): ‘1111 1000’.3.The leader sends the I2C bus follower address of the follower device it must identify. The LSB is a “don’t care” value. Onlyone device must acknowledge this byte (the device that has the I2C bus follower address).4.The leader sends a RESTART condition.Remark: A STOP condition followed by a START condition resets the follower state machine and the Device ID read cannotbe performed. Also, a STOP condition or a RESTART condition followed by an access to another follower device resets thefollower state machine and the Device ID read cannot be performed.1.The leader sends the Reserved Device ID I2C bus address followed by the R/W bit set to ‘1’ (read): ‘1111 1001’.2.The Device ID read can be completed, starting with the 12 manufacturer bits (first byte four MSBs of the second byte),followed by the nine part identification bits (four LSBs of the second byte five MSBs of the third byte), and then the threedie revision bits (three LSBs of the third byte).3.The leader ends the reading sequence by NACKing the last byte, thus resetting the follower device state machine andallowing the leader to send the STOP condition.Remark: The reading of the Device ID can be stopped anytime by sending a NACK.A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data19 / 33

Communication interfacesTable 18. I2C Device Read instructionsLeader toFollowerSTART9.3Leader toFollowerLeader toFollower1111 1000Leader toFollowerXXXXXXX ‘0/1’RESTARTLeader toFollowerFollower toLeader1111 10013 bytes IDLeader toFollowerLeader toFollowerNACKSTOPI2C electrical specification and timing for I/O stages and bus linestfSDAtrtSU;DAT70 %30 %70 %30 %tf70 %30 %70 %30 %tHD;STAStVD;DATtHIGHtr70 %30 %SCLKcont.tHD;DAT70 %30 %cont.tLOW9th clock1 / fSCLK1st clock 0 %30 %9th clockPSaaa-042715Note: VIL 0.3 VDD, VIH 0.7 VDDFigure 10. I2C electrical specification and timing for I/O stages and bus linesA3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021Data Sheet: Technical Data20 / 33

Communication interfaces9.3.1I2C SCLK and SDA characteristicsTable 19. I2C SCLK and SCLK clock frequency—tHD;STAHold t

No Connection . 7 : RF. in . RF Input Signal @ 50 Ohm : 9 . A1 : I. 2C Address A1 (tri-state, tie to 5 V, tie to ground or leave floating) 10 : A0 . I2C Address A0 (tri-state, tie to 5 V, tie to ground or leave floating) 11 . SCLK : SPI/I. 2C Serial Clock Signal (1.8 V JEDEC compatible) 12 : SDA . SPI/I2C Serial Data Signal (1.8 V JEDEC .