PL-2303HX Edition (Chip Rev D) USB To Serial Bridge .
PL-2303HX Edition (Chip Rev D)USB to Serial Bridge ControllerProduct DatasheetDocument Revision: 1.4.4Document Release: March 20, 2013Prolific Technology Inc.7F, No. 48, Sec. 3, Nan Kang Rd.Nan Kang, Taipei 115, Taiwan, R.O.C.Telephone: 886-2-2654-6363Fax: 886-2-2654-6161E-mail: sales@prolific.com.twWebsite: http://www.prolific.com.tw
Revised Date:March 20, 2013ds pl2303HXD v1.4.4DisclaimerAll the information in this document is subject to change without prior notice. Prolific Technology Inc.does not make any representations or any warranties (implied or otherwise) regarding the accuracyand completeness of this document and shall in no event be liable for any loss of profit or any othercommercial damage, including but not limited to special, incidental, consequential, or other damages.TrademarksThe Prolific logo is a registered trademark of Prolific Technology Inc. All brand names and productnames used in this document are trademarks or registered trademarks of their respective holders.CopyrightsCopyright 2005-2013 Prolific Technology Inc., All rights reserved.No part of this document may be reproduced or transmitted in any form by any means without theexpress written permission of Prolific Technology Inc.PL-2303HX (Rev D) Product Datasheet-2-Document Version 1.4.4
Revised Date:March 20, 2012ds pl2303HXD v1.4.4Revision HistoryRevisionDescriptionDate1.4.4 Added Android USB Host API Support1.4.3 Modify Features and OS Driver Support List Added QFN32 Reel Tape Information1.4.2 Modify Section 12.0 Ordering Information Part NumberJune 25, 20121.4.1 Modify Reel Tape Packing (MOQ) InformationMay 25, 20121.4 Added Windows 8 Driver Support Added OTPROM Configuration Section Modified BaudRate Support Table Added Reference Schematic Diagram Added Chip Marking Information Added Tube Packing Information Added Worldwide Distributors Information Added Windows 7 Logo Driver Information Modified Operating Temperature Characteristics Modified Baud Rate Settings Table1.2 Sec. 9.0: Modified DC & Temperature CharacteristicsJune 27, 20081.1 Added Windows Vista and XP Logo Driver informationApril 16, 2007 Added USB-IF Logo TID information1.0B Sec. 4.2: Modified QFN diagram to add IC bottom PADinformationJune 30, 20061.0A PL-2303HX (Chip Rev D) Datasheet – Formal ReleaseNovember 23, 20051.3PL-2303HX (Rev D) Product Datasheet-3-March 20, 2013September 11, 2012March 16, 2012September 9, 2010Document Version 1.4.4
Revised Date:March 20, 2013ds pl2303HXD v1.4.4Table of Contents1.0FEATURES. 71.1 Royalty-Free Driver Support . 81.2 Product Applications . 82.0FUNCTIONAL BLOCK DIAGRAM . 93.0INTRODUCTION . 104.0PIN ASSIGNMENT OUTLINE . 114.1 SSOP28 Package . 114.2 QFN32 Package. 125.0PIN ASSIGNMENT & DESCRIPTION . 135.1 SSOP28 Package . 135.2 QFN32 Package. 146.0OTPROM CONFIGURATION . 157.0DATA FORMATS & PROGRAMMABLE BAUD RATE GENERATOR . 178.0PL2303HXD REFERENCE SCHEMATIC DIAGRAM . 189.0DC & TEMPERATURE CHARACTERISTICS . 199.1 Absolute Maximum Ratings . 199.2 DC Characteristics . 199.3 Clock Characteristics . 209.4 Temperature Characteristics . 219.5 Leakage Current and Capacitance . 219.6 Power-On Reset . 2110.0 OUTLINE DIAGRAM . 2210.1 SSOP28 Package . 2210.2 QFN32 Package . 2311.0 PACKING INFORMATION . 2411.1 Carrier Tape (SSOP-28) . 2411.2 Carrier Tape (QFN32). 2511.3 Reel Dimension . 2611.4 Tube Packing . 27PL-2303HX (Rev D) Product Datasheet-4-Document Version 1.4.4
Revised Date:March 20, 2012ds pl2303HXD v1.4.412.0 ORDERING AND CHIP MARKING INFORMATION . 2813.0 CONTACT INFORMATION . 29PL-2303HX (Rev D) Product Datasheet-5-Document Version 1.4.4
Revised Date:March 20, 2013ds pl2303HXD v1.4.4List of FiguresFigure 2-1 Block Diagram of PL-2303HX (Rev D) . 9Figure 4-1 Pin Assignment Outline of PL-2303HX (Rev D) SSOP28 . 11Figure 4-2 Pin Assignment Outline of PL-2303HX (Rev D) QFN32 . 12Figure 6-1 PL2303 EEPROM Writer Program . 15Figure 8-1 PL2303HX (Chip Rev D) Reference Schematic Diagram . 18Figure 9-1 Power-On Reset Diagram. 21Figure 10-1 Outline Diagram of PL-2303HX (Rev D) SSOP28 . 22Figure 10-2 Outline Diagram of PL-2303HX (Rev D) QFN32 . 23Figure 11-1 SSOP28 Carrier Tape . 24Figure 11-2 IC Reel Placements . 24Figure 11-3 QFN32 Carrier Tape . 25Figure 11-4 Reel Dimension . 26Figure 11-5 Tube Packing Dimension . 27Figure 12-1 Chip Part Number Information (SSOP) . 28List of TablesTable 5-1 Pin Assignment & Description (SSOP28) . 13Table 5-2 Pin Assignment & Description (QFN32) . 14Table 6-1 EEPROM Writer Configuration . 15Table 7-1 Supported Data Formats . 17Table 7-2 Baud Rate Settings (Supported by Driver) . 17Table 9-1 Absolute Maximum Ratings . 19Table 9-2a Operating Voltage and Suspend Current . 19Table 9-2b 3.3V I/O Pins . 19Table 9-2c VDD 325@3.3V Serial I/O Pins . 20Table 9-2d VDD 325@2.5V Serial I/O Pins . 20Table 9-2e VDD 325@1.8V Serial I/O Pins . 20Table 9-3 Clock Characteristics . 20Table 9-4 Temperature Characteristics . 21Table 9-5 Leakage Current and Capacitance . 21Table 9-6 Power-On Reset . 21Table 10-1 Package Dimension . 22Table 11-1 Reel Part Number Information . 26Table 12-1 Ordering Information . 28Table 12-2 Chip Marking Information . 28PL-2303HX (Rev D) Product Datasheet-6-Document Version 1.4.4
Revised Date:March 20, 2012ds pl2303HXD v1.4.41.0 Features Single-chip USB to Serial (RS232/RS422/RS485) asynchronous serial data transfer interface Fully Compliant with USB Specification v2.0 (Full-Speed) USB-IF Logo Compliant with TID 40000100 UHCI/OHCI (USB1.1), EHCI (USB 2.0), xHCI (USB 3.0) Host Controller Compatible Integrated USB 1.1 Transceiver and 5V to 3.3V Regulator Integrated 96MHz clock generator (No external crystal required) Integrated OTPROM (One-Time Programming ROM) – no external EEPROM required.o For writing and storing customer USB VID/PID, Serial Number, Product String, andother device startup configurations. (uses default settings if OTPROM is empty)Supports USB to RS232 Serial UART InterfaceoFull-duplex transmitter and receiver (TXD and RXD)oSix MODEM control pins (RTS, CTS, DTR, DSR, DCD, and RI)o5, 6, 7 or 8 data bitsoOdd, Even, Mark, Space, or None parity modeoOne, one and a half, or two stop bitsoParity error, frame error, and serial break detectionoProgrammable baud rate from 75 bps to 12M bpsoExternal RS232 driver power down controloIndependent power source for serial interface Supports RS-422/RS-485 like serial interface (TXD, DTR N, and RTS N pins should beexternally pulled-up to 5V) Extensive Flow Control Mechanism oAdjustable high/low watermark leveloAutomatic hardware flow control with CTS/RTS or DSR/DTRoAutomatic software flow control with XON/XOFFoInbound data buffer overflow detectionConfigurable 512-byte bi-directional data buffero256-byte outbound buffer and 256-byte inbound buffer; oro128-byte outbound buffer and 384-byte inbound buffer Supports Remote Wake-up from RS232 input pin signals (RI, RXD, DSR, DCD, CTS) Four (4) General Purpose I/O (GP0, GP1, GP2, & GP3) pins and Four (4) Auxiliary GeneralPurpose I/O (RI N, DSR N, DCD N, & CTS N) pins. Supports Windows Selective Suspend by OTPROM configuration (Enable Remote Wakeup)oSuspends power of chip when idle (COM port is closed) Provides royalty-free USB to Virtual COM Port drivers for Windows, Mac, Linux, Android -40 C to 85 C Operating Temperature Small footprint 28-pin SSOP or 32-pin QFN IC packages (RoHS compliant and Pb-free GreenCompoundooPL-2303HX (Rev D) Product Datasheet-7-Document Version 1.4.4
Revised Date:March 20, 2013ds pl2303HXD v1.4.41.1Royalty-Free Driver Support Windows 8, 7, Vista, XP, 2000 (Microsoft Certified WHQL Drivers)oWindows Update Driver installation available in Windows Vista, 7, and 8 (32/64-bit)oDownload: http://www.prolific.com.tw/US/ShowProduct.aspx?p id 225&pcid 41 Windows Server 2003, 2008, 2008 R2, 2012 Windows XP Embedded (XPe), Point-of-Service (WEPOS), and POSReady Windows CE 4.2, 5.0, 6.0, and Windows Embedded Compact 7o Mac OS 8/9, OS X (supports latest Mac OS X 10.8 Mountain Lion)o Download: http://www.prolific.com.tw/US/ShowProduct.aspx?p id 229&pcid 41Linux/Android kernel 2.4.31 and above includes built-in drivers (pl2303.c)o Requires customer SDK image file for customizing WinCE 6.0 and 7.0 drivers.Android requires root permission for accessing virtual serial port (ttyusb)Android Java Driver Library (requires Android 3.2 and above with USB Host or OTG)oNo root permission neededoDownload: http://www.prolific.com.tw/US/ShowProduct.aspx?p id 230&pcid 41oAndroid device must support USB Host API: ctivity/usb/host.htmlProvides Driver Customization for Customer USB VID/PID and special baud ratesProduct Applications Single-chip upgrade solution for Legacy RS232 devices to USB interface USB to RS232/RS422/RS485 converters/cables/dongles/adapters Healthcare/Medical USB Interface Data Transfer Cable Personal Infotainment/Media Player Docking USB Interface Cellular/PDA USB Interface Data Transfer Cable Serial-over-IP Wireless Solution USB Barcode/Smart Card Readers GPS/Navigation USB Interface Point-of-Sale (POS) Terminals/Printers PC Docking Station/Port Replicators Industrial/Instrumentation/Automation Control USB Interface USB Modem/Wireless/Zigbee USB Interface Set-Top Box (STB) / Home Gateway USB Interface MCU-based devices to USB interfacePL-2303HX (Rev D) Product Datasheet-8-Document Version 1.4.4
Revised Date:March 20, 2012ds pl2303HXD v1.4.42.0 Functional Block DiagramUSB HostUSB 1.1Transceiver96MHz Clock GeneratorPowerManagementControl EndpointUSB Digital LockLoopUSB to Serial Interface bound DataBuffer256/128ByteOutbound DataBufferInterrupt Endpoint256-BytesOTP ROM5 to 3.3VRegulatorHardware ROMDefault DescriptorRS232 / RS-422 / RS-485 LikeSerial Interface EnginePL-2303HXDRS-232/RS-422/RS-485 Like InterfaceFigure 2-1 Block Diagram of PL-2303HX (Rev D)PL-2303HX (Rev D) Product Datasheet-9-Document Version 1.4.4
Revised Date:March 20, 2013ds pl2303HXD v1.4.43.0 IntroductionPL-2303HX (Chip Rev D) or PL-2303HXD provides a convenient solution for connecting an RS232-likefull-duplex asynchronous serial device to any Universal Serial Bus (USB) capable host. PL-2303HXDhighly compatible drivers could simulate the traditional COM port on most operating systems allowingthe existing applications based on COM port to easily migrate and be made USB ready.By taking advantage of USB bulk transfer mode, large data buffers, and automatic flow control,PL-2303HXD is capable of achieving higher throughput compared to traditional UART (UniversalAsynchronous Receiver Transmitter) ports. When real RS232 signaling is not required, baud ratehigher than 115200 bps could be used for even higher performance. The flexible baud rate generator ofPL-2303HXD could be programmed to generate any rate between 75 bps to 12M bps.PL-2303HXD is exclusively designed for mobile and embedded solutions in mind, providing a smallfootprint that could easily fit in to any connectors and handheld devices. With very small powerconsumption in either operating or suspend mode, PL-2303HXD is perfect for bus powered operationwith plenty of power left for the attached devices. Flexible signal level requirement on the RS232-likeserial port side also allows PL-2303HXD to connect directly to any 3.3V 1.8V range devices.PL-2303HX (Rev D) Product Datasheet- 10 -Document Version 1.4.4
Revised Date:March 20, 2012ds pl2303HXD v1.4.44.0 Pin Assignment Outline4.1SSOP28 Package1TXDRESERVED282DTR NNC273RTS NTEST264VDD 325GND255RXDNC246RI NGP1237GNDGP0228NCNC219DSR NVDD 52010DCD NRESET N1911CTS NGND1812SHTD NVO 331713GP3DM1614GP2DP15PL-2303HX (Rev D)Figure 4-1 Pin Assignment Outline of PL-2303HX (Rev D) SSOP28PL-2303HX (Rev D) Product Datasheet- 11 -Document Version 1.4.4
Revised Date:March 20, 2013ds pl2303HXD v1.4.4VD D 325GN DT ESTR ESER VEDNCNCT XDD T R NQFN32 PackageR T S N4.21NCR XDGP1R I NGP0GN DNCPL-2303HXDVD D 33VD D 5D SR NR ESET ND C D NGN DExposed Die Pad connects to VO 33C T S NNCDMDPNCNCGP2GP3SH T D NVO 33Figure 4-2 Pin Assignment Outline of PL-2303HX (Rev D) QFN32Warning: The exposed center die pad of the PL-2303HX QFN package is connected (bonded) to thepin VO 33 so it is very important to design the PCB layout wherein this exposed die padwon’t get grounded on the PCB when mounted.PL-2303HX (Rev D) Product Datasheet- 12 -Document Version 1.4.4
Revised Date:March 20, 2012ds pl2303HXD v1.4.45.0 Pin Assignment & DescriptionPin Type Abbreviation:I: Input5.1O: OutputB: Bidirectional I/OP: Power/GroundSSOP28 PackageTable 5-1 Pin Assignment & Description (SSOP28)Pin # NameType(1)123TXDDTR NRTS NO(1)O(1)O4VDD 325P5RXDI6RI NB78GNDNCP-9DSR NB(2)10DCD NB(2)11CTS NB(2)1213141516171819202122232425262728SHTD NGP3GP2DPDMVO 33GNDRESET NVDD )BI-(2)(2)(3)DescriptionSerial Port (Transmitted Data)Serial Port (Data Terminal Ready)Serial Port (Request To Send)RS232 VDD. The power pin for the serial port signals. Whenthe serial port is 3.3V, this should be 3.3V. When the serial portis 2.5V, this should be 2.5V. The range can be from 1.8V 3.3V.Serial Port (Received Data)Serial Port (Ring Indicator); or Auxiliary General Purpose I/O(7)Port when enabled .GroundNo ConnectionSerial Port (Data Set Ready); or Auxiliary General Purpose I/O(7)Port when enabled .Serial Port (Data Carrier Detect); or Auxiliary General Purpose(7)I/O Port when enabled .Serial Port (Clear to Send); or Auxiliary General Purpose I/O(7)Port when enabled .RS232 Transceiver Shut Down Control(6)Auxiliary GPIO Pin 3 (Default output high mode)(6)Auxiliary GPIO Pin 2 (Default output high mode)USB Port D signalUSB Port D- signalRegulator Power Output, 3.3VGroundExternal System Reset (Active Low)USB Port VBUS, 5V Power. (6.5V for OTPROM writing voltage).No ConnectionGeneral Purpose I/O Pin 0General Purpose I/O Pin 1No ConnectionGroundTest mode controlNo ConnectionReserved pin (Must be floating)Notes:(1) – Tri-State, Output Pad. Level and Driving Capability decided by VDD 325.(2) – Tri-State, CMOS Input/Output Pad with level shifter. Level and Driving Capability decided by VDD 325.(3) – CMOS Output Pad.(4) – CMOS Input Pad, 5V tolerant.(5) – Tri-State, CMOS Input/Output Pad. (Default mode: Input)(6) – Default output high mode; do not connect to ground.(7) – Enabling Auxiliary GPIO requires special customized driver.PL-2303HX (Rev D) Product Datasheet- 13 -Document Version 1.4.4
Revised Date:March 20, 2013ds pl2303HXD v1.4.45.2QFN32 PackageTable 5-2 Pin Assignment & Description (QFN32)Pin #NameType1VDD 325P2RXDI3RI NB45GNDVDD 33PP6DSR NB(2)7DCD NB(2)8CTS 32SHTD NGP3GP2NCNCDPDMNCVO 33GNDRESET NVDD 5NCGP0GP1NCGNDTESTReservedNCNCTXDDTR NRTS NIC Bottom scriptionRS232 VDD. The power pin for the serial port signals.When the serial port is 3.3V, this should be 3.3V. Whenthe serial port is 2.5V, this should be 2.5V. The range canbe from 1.8V 3.3V.Serial Port (Received Data)Serial Port (Ring Indicator); or Auxiliary General Purpose(
PL-2303HX (Rev D) Product Datasheet - 3 - Document Version 1.4.4 Revision History Revision Description Date 1.4.4 Added Android USB Host API Support March 20, 2013 1.4.3 Modify Features and OS Driver Support
The Rt. Rev. George N. Hunt The Rev. Frederick K. Jellison The Rev. Dn. Ida R. Johnson The Rev. Michaela Johnson The Rev. Paul S. Koumrian The Rev. Canon Harry E. Krauss * The Rev. H. August Kuehl The Rev. Richard T. Laremore * The Rev. Donald A. Lavallee The Rev. Canon John E. Lawrence The Rev. Dr. Gary C. Lemery * The Rev. Dn. Betsy Lesieur *
10.3.5 Connecting ADC and DAC IPs into a Cortex-M system 242 10.4 243Bring an SoC to life – Beetle test chip case study 10.4.1 Beetle test chip overview 243 10.4.2 Beetle test chip challenges 245 10.4.3 Beetle test chip system design 246 10.4.4 Implementation of the Beetle test chip 24
The parallel chip breaker, that the figure N 1 shows an example, is mainly used in finishing operations. Figure N 1 - Parallel chip breaker Inclined chip breaker The angular type is suitable for most machining operations and is the most difficult to do. The chip is flexed towards the area of the workpiece where is broken without damaging .
NEW CHIP BREAKER FGS TYPE FGS type chip breaker The FGS chip breaker is a positive ground type insert. Its sharp cutting edge generates low cutting resistance while guarantee-ing high precision machining. The chip breaker minimizes heat when machining heat resistant super alloys and the small dot located in the corner is effective for chip control.
Nomenclature bch Chip width (mm), (in) bγ1 Insert/chip restricted contact length (mm), (in) Ch Cutting ratio (the ratio of the undeformed chip thickness to the chip thickness) d Depth of cut (mm), (in) d0 The standard critical depth of cut under pre-defined standard cutting condition (mm), (in) dmax Maximum depth of cut in extra region of chip-breaking chart (mm), (in)
1.1 Chip breaker A chip breaker is the tool which has a groove or an obstacle placed on the incline face of the tool. A chip breaker can be used for increasing chip breakability which results in efficient chip control and improved productivity. It also decreases cutting resistance, and gives a better surface finish to the workpiece.
and processing unit in a single chip have been reported [7]-[13]. These architectures are proposed for a photo-image sensing chip. Fig. 1 shows the conventional photo-image-sensing chip architecture. In the architecture for a sensor-embedded chip, the sensor and processing unit are integrated on a single chip by placing them side by side, as .
Course of Russian language at school with native (non-Russian) language learning is based on the principles and requirements common to Russian and national schools. Basic principles of teaching children-migrants at the elementary school are: 1) Learning Russian language is focused on the development of children's ability to communicate.
