MIPS: A Microprocessor Architecture

MIPS: A Microprocessor ArchitectureJohn Hennessy, Norman Jouppi, Steven Przybylski, Christopher Rowen,Thomas Gross, Forest Baskett, and John GillDepartments of Electrical Engineering and Computer ScienceStanford UniversityAbstract3. The RISC project relies on a straightforward instruction setand straightforward compiler technology. MIPS will requiremore sophisticated compiler technology and will gainsignificant performance benefits from that technology. Thecompiler technology allows a microcode-level instructionset to appear like a normal instruction set to both codegenerators and assembly language programmers.MIPS is a new single chip VLSI microprocessor. It aftempts toachieve high performance with the use of a simplified instructionset, similar to those found in microengines. The processor is a fastpipelined engine without pipeline interlocks. Software solutionsto several traditional hardware problems, such as providingpipeline interlocks, are used.The MIPS architecture is closer to the 801 architecture in manyaspects. In both machines the macroinstruction set maps verydirectly to the microoperations of the processor. Both processorsmay be thought of as architectures with micro-level userinstruction sets. Microcode is created by compilers and codegenerators as it is needed to implement complex operations. Theprimary differences lie in various architectural choices aboutpipeline design, registers, opeodes and in the attempt in the MIPSinstruction set to make all the microengine parallelism available atthe user instruction set level. These attempts are most visiblewithin MIPS in the following ways: the two-part memory/ALUand A L U / A L U instructions, the explicit pipeline interlocks, andthe conditional jump instructions.IntroductionMIPS (Microprocessor without Interlocked Pipe Stages) is a newgeneral purpose microprocessor architecture designed to beimplemented on a single VLSI chip. The main goal of the designis high performance in the execution of comPiled code. Thearchitecture is experimental since it is a radical break with thetrend of modern computer architectures. The basic philosophy ofMIPS is to present an instruction set that is a co !apiler-drivenencoding of the microengine. Thus, little or no decoding isneeded and the instructions correspond closely to microeodeinstructions. The processor is pipelined but provides no pipelineinterlock hardware; this function must be provided by software.MIPS is designed for high performance. To allow the user to getmaximum perf )rmance, the complexity of individual instructionsis minimized. This allows the execution of these instructions atsignificantly higher speeds. To take advantage of simplerhardware and an instruction set that easily maps to themieroinstruction set, additional compiler-type translation isneeded. This compiler technology makes a compact and timeefficient mapping between higher level constructs and thesimplified instruction set. The shifting of the complexity from thehardware to the software has several major advantages:The MIPS architecture presents the user with a fast machine witha simple instruction set. This approach has been used by the IBM8071 project I and is currently being explored by the RISC projectat Berkeley2; it is directly 'opposed to the approach taken byarchitectures such as the VAX. However, there are significantdifferences between the RISC approach and the approach used inMIPS:1. The RISC architecture is simple both in the instruction setand the hardware needed to implement that instruction set.Although the MIPS instruction set has a simple hardwareimplementation (i.e. it requires a minimal amount ofhardware control), the user level instruction set is not asstraightforward, and the simplicity of the user levelinstruction set is secondary to the performance goals. The complexity is paid for only once during compilation.When a user runs his program on a complex architecture,he pays the cost of the architectural overhead cach time heruns his progrmn. It allows the concentration of energies on the software,rather than constructing a complex hardware engine, whichis hard to design, debug, and efficiently utilize. Software isnot necessarily easier to construct, but the WLSI environment makes hardware simplicity important.2. The thrust of the R I S C design is towards cfficientimplementation of a straightforward instruction set. In theM1PS design, high performance from the hardware engineis a primary goal, and the microengine is presented to theend user with a minimal amount of interpretation. Thismakes most of the microcngine's parallelism available at theinstruction set level.0194-1895/82/0000/0017500.75 1982 I E E EThe design of a high performance VLSI processor is drarnaticallyaffected by the technology. Among the most important designconsiderations are: the effect of pin limitations, available silicon17

area, and size/speed tradeoffs. Pin limitations force the carefuldesign of a scheme for multiplexing the available pins, especiallywhen data and instruction fetches are overlapped.Arealimitations and the speed of off-chip intercommunication requirechoices between on- and off-chip functions as well as limiting thecomplete on-chip design. With current state-of-the-art iechnologyeither some vital component of the processor (such as memorymanagement) must be off-chip, or the size of the chip will makeboth its performance and yields unacceptably low. Choosing whatfunctions are migrated off-chip must be done carefully so that theperformance effects of the partitioning are minimized. In somecases, through careful design, the effects may be eliminated atsome extra cost for high speed off-chip functions.architecture is simplicity of the pipeline structure. The simplifiedstructure has a fixed number of pipestages, each of the samelength. Because, the stages .can be used in varying (but related)ways, pipline utilization improves. Also, the absence ofsynchronization between stages of the pipe, increases theperformance of the pipeline and simplifies the hardware. Thesimplified pipeline eases the handling of both interrupts and pagefaults.Although MIPS is a pipelined processor it does not havehardware pipeline interlocks. This approach is often seen in lowand medium performance microengines. MIPS five stage pipelinecontains three active instructions at any time; either the odd oreven pipestages are active. The major pipestages and their tasksare shown in Table 1.Speed/complexity/area tradeoffs are perhaps the most importantand difficult phenomena to deal with. Additional on-chipfunctionality requires more area, which also slows down theperformance of every other function. "Ibis occurs for two equallyimportant reasons: additional control and decoding logic increases the length of the critical path (by increasing the number ofactive elements in the path) and each additional functionincreases the length of internal wire delays. In the processor's datapath these wire delays can be substantial, since thy accumulateboth from bus delays, which occur when the data path islengthed, and control delays, which occur when the decoding andcontrol is expanded or when the data path is widened. In theMIPS architecture we have attempted to control these delays;however, they remain a dominant factor in detexTnining the speedof the processor.TheDesignTable 1" Major pipestages and their functionsStaqeI n s t r u c t i o n FetchHnemonic TaskIFSend out the PC,increment i tInstruction DecodeIDDecode instructionOperand DecodeODCompute effectivoaddress and send tOmemory i f load orstore, use ALUOperand Store/ExecutionOS/EXStore: w r i t e operand/"Execution: use ALUOperand FetchOFLoad: read operandInterlocks that are required because of dependencies brought outby pipelining are not provided by the hardware. Instead, theseinterlocks must be statically provided where they areneeded by apipeline reorganizer. This has two benefits:1. A more regular and faster harclware implementation ispossible since it does not have the usual complexityassociated with a pipelined machine. Hardware interlockscause small delays for ,all instructions, regardless of theirrelationship on other instructions. Also, interlock hardwaretends to be very complex and nonregular 3,4. qhe lack ofsuch hardware is especially important for VLSI implementations, vhere regularity and simplicity is important.microarchitecturephilosophyThe fastest execution of a task on a microengine would be one inwhich all resources of the microengine were used at a 100% dutycycle performing a nonrcdundant and algorithmically efficientencoding of the task. The MIPS microengine attempts to achievethis goal. The user instruction set is an encoding of themicroengine that makes a maximum amount of the microengineavailable. This goal motivated many of the design decisionsfound in the architecture.2. Rearranging operations at compile time is better thandelaying them at mn time.With a good pipelinereorganizer, most cases where interlocks are avoidableshould be found and taken advantage of. This results inperformance better than a comparable machine withhardware interlocks, since usage of resources will not bedelayed. In cases where this is not detected or is notpossible, no-ops must be inserted into the code. This doesnot slow down execution compared to a similar machinewith- hardware interlocks, but does increase code size. Theshifting of work to a reorganizer would be a disadvantage ifit took excessive amounts of computation. It appears this isnot a problem for our first reorganizer.MIPS is a load/store architecture, i.e. data may be operated ononly when it is in a register and only load/store instructions accessmemory. If data operands are used repeatedly in a basic block ofcode, having them in registers will prevent redundant load/storesand redundant addressing calculations; this allows higherthroughput since more operations directly related to thecomputation can be performed. The only addressing modessupported are immediate, based with offset, indexed, or baseshifted. ibese addressing modes may require fields from theinstruction itself, general registers, and one ALU or shifter peration. Another ALU operation available in the fourth stageof every instruction can be used for a (possibly unrelated)computation. Another major benefit derived from the load/storeIn the MIPS pipeline resource usage is permanently allocated to18