PROBLEMS - University Of Iceland
612CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap. 12 - Famiglie di processori)PROBLEMS11.1How is conditional execution of ARM instructions (see Part I of Chapter 3) relatedto predicated execution of IA-64 instructions? Comment on similarities and differences.11.2The 16-bit Thumb instruction subset of ARM instructions is intended for compact program encoding. Estimate the number of Thumb instructions needed to program theevaluation of the arithmetic expression shown in Figure 11.9. Assume that the Thumbsubset has an appropriate divide instruction (which it does not) for the purposes of thisquestion. How does the estimated Thumb instruction count compare to the HP3000program instruction count in Figure 11.9a?11.3Discuss the similarities and differences between the Motorola 680X0 family and theIntel 80X86 family of processors, up to the 68040 and the 80486 versions.11.4The 68030 microprocessor has a 256-byte instruction cache and a 256-byte data cache.Is this better than having a 512-byte instruction cache and no data cache? What are theadvantages and disadvantages of these two alternatives? Answer the same two questionsfor a unified 512-byte instruction and data cache.11.5Intel IA-32 processors have special instructions for dedicated I/O operations, as described in Part III of Chapter 3. Motorola 680X0 processors use only memory-mappedI/O. What are the advantages and disadvantages of memory-mapped I/O compared todedicated I/O?11.6Discuss the relative merits of addressing modes in the Motorola 680X0 and Intel 80X86processors. In particular, discuss how the addressing modes in each processor facilitateprogram relocation, implementation of a stack, accessing an operand list, and manipulating character strings.Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
PROBLEMS61311.7Section 11.3.1 explains that an IA-32 processor can view the memory as being organizedin four different ways, depending on how segmentation and paging are used. Give someexamples of situations in which each of the four possibilities is beneficial.11.8Write an ARM, 68000, or IA-32 program to evaluate the arithmetic expression inFigure 11.9. How does your program compare to the one in the figure with respect to thenumber of machine instructions required? Assume that the standard ARM instructionset has an appropriate divide instruction (which it does not) for the purposes of thisquestion.11.9In Alpha processors, only 32-bit and 64-bit aligned loads and stores are directly handledin the datapath between the cache and the processor. Sketch the combinational logicnetwork that would be required in a 32-bit-wide datapath to permit loading any one ofthe four bytes of a 32-bit quantity into the low-order byte position at the destinationside of the path.11.10Compare the handling of the register stack in the IA-64 processors to that of the processor (memory) stack in Chapter 2. In particular, what are the counterparts of theChapter 2 stack pointer, SP, and frame pointer, FP, in the IA-64 scheme?11.11Give a general description of the hardware needed to support execution of the Alloc X,Yinstruction used for managing the IA-64 register stack. Assume that small registers andadders are available. How are they used?11.12The Alpha 21264 processor has a much different arrangement of caches than the 21164.Why is the arrangement in the 21264 better? That is, under what circumstances doprograms execute more quickly on the 21264, based only on the effects of cacheing?Include more than an observation on hit rates in your answer.11.13Show how the expression f gw a (b c) (d e) h i can be evaluated in an HP3000 computer.11.14In an HP3000 computer, Procedurei generates eight words of data, DI1 , . . . , DI8 , whichare stored in the stack. After these words are placed in the stack, but before the completion of Procedurei , a new procedure, Procedure j , is called. It generates 10 wordsof data, DJ1 , . . . , DJ10 , which are also stored in the stack. Then another procedure,Procedurek , is called, which places three words of data in the stack. Show the contentsof the top words of the stack at this time.11.15Show how the expressionw (a b)(c d) (d e)can best be evaluated by the HP3000, ARM, Motorola 68000, and IA-32 computers. Thevalues of variables w, a, b, c, d, and e are stored in memory locations. The followingassumptions are made. The addresses do not reference successive locations. Directmemory addressing in the DB relative mode is used in the HP3000. Absolute/DirectIntroduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
614CHAPTER 11 PROCESSOR FAMILIESmemory addressing is used in the 68000 and IA-32 computers, and Relative addressingis used in the ARM computer. All products are single length.11.16What is the largest number of stack locations occupied during execution of the programin Figure 11.9?11.17Repeat Problem 11.16 for the HP3000 programs in Problems 11.13 and 11.15.Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
SOLUTIONS - Chapter 11Processor Families11.1. The main ideas of conditional execution of ARM instructions (see Sections 3.1.2and B.1) and conditional execution of IA-64 instructions, called predication (seeSection 11.7.2), are very similar.The differences occur in the way that the conditions are set and stored in theprocessor, and in the way that they are referenced by the conditionally executedinstructions.In ARM processors, the state is stored in four conventional condition code agsN, Z, C, and V (see Section 3.1.1). These ags are optionally set by the resultsof instruction execution. The particular condition, which may be a function ofmore than one ag, is named in the condition eld of each ARM instruction (seeFigure B.1 and Table B.1).In the IA-64 architecture, there are no conventional condition code ags. Instead, the result (true or false) of executing a Compare condition instructionis stored in one of 64 one-bit predicate registers, as described in Section 11.7.2.Each instruction can name one of these bits in its 6-bit predicate eld; and theinstruction is executed only if the bit is 1 (true).1Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.2. Assume that Thumb arithmetic instructions have a 2-operand format, expressedin assembly language asOPRdst,Rsrcas discussed in Section 11.1.1Also assume that a signed integer Divide instruction (DIV) is available in theThumb instruction set with the assembly language formatDIVRdst,RsrcThis instruction performs the operation [Rdst]/[Rsrc]. It stores the quotient inRdst and stores the remainder in Rsrc.Under these assumptions, a possible Thumb program would R1,AR2,BR1,R2R1,R0R1,WLeaves g h in R0.Leaves e f in R1.Leaves (e f )/(g h) in R1.Leaves c/d in R0.Leaves denominator in R0.Leaves a b in R1.Leaves result in R1.Stores result in w.This program requires 16 instructions as compared to 13 instruction words (somecombined instructions) in the HP3000.2Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.3. The following table shows some of the important areas for similarity/differencecomparisons.MOTOROLA 680X0INTEL 80X868 Data registers and 8 Addressregisters (including aprocessor stack register)8 General registers (includinga processor stack register)CISC instruction set withe xible addressing modesCISC instruction set withe xible addressing modesLarge instruction set withmultiple-register load/storeinstructionsLarge instruction set withmultiple-register push/popinstructionsMemory-mapped I/O onlySeparate I/O space as well asmemory-mapped I/OFlat address spaceSegmented address spaceBig-endian addressingLittle-endian addressingThere is roughly comparable capability and performance between pairs fromthese two families; that is 68000 vs. 8086, 68020 vs. 80286, 68030 vs. 80386,and 68040 vs. 80486. The cache and pipelining aspects for the high end of eachfamily are summarized in Sections 11.2.2 and 11.3.3.11.4. An instruction cache is simpler to implement, because its entries do not have tobe written back to the main memory. A data cache must have a provision for writing any changed entries back to the memory, before they are overwritten by newentries. ¿From a performance standpoint, a single larger instruction cache wouldbe advantageous only if the frequency of memory data accesses were very low.A uni ed cache has the potential performance advantage that the proportions ofinstructions and data vary automatically as a program is executed. However, ifseparate instruction and data caches are used, they can be accessed in parallel ina pipelined machine; and this is the major performance advantage.11.5. Memory-mapped I/O requires no specialized support in terms of either instructions or bus signals. A separate I/O space allows simpler I/O interfaces andpotentially faster operation. Processors such as those in the IA-32 family, thathave a separate I/O space, can also use memory-mapped I/O.3Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.6. MOTOROLA - The Autoincrement and Autodecrement modes facilitate stackimplementation and accessing successive items in a list. Signi cant e xibilityin accessing structured lists and arrays of addresses and data of different sizesis provided by the displacement, offset, and scale factor features, coupled withindirection.INTEL - Relocatability in the physical address space is facilitated by the wayin which base, index and displacement features are used in generating virtualaddresses. As in the Motorola processors, these multiple-component addressfeatures enable e xible access to address lists and data structures.In both families of processors, byte-addressability enables handling of characterstrings, and the Intel IA-32 String instructions (see Sections 3.21.3 and D.4.1)facilitate movement and processing of byte and doubleword data blocks. TheMotorola MOVEM and MOVEP instructions perform similar operations.11.7. Flat address space — Simplest con guration from the standpoint of a single userprogram and its compilation.One or more variable-length segments — Ef cient allocation of available memory space to variable-length user or operating system programs.Paged memory — Facilitates automated memory management between the randomaccess main memory and a sector-organized disk secondary memory (see Chapters 5 and 10). Access privileges can be controlled on a page-by-page basisto ensure protection among users, and between users and the operating systemwhen shared data are involved.Segmentation and paging — Most e xible arrangement for managing multipleuser and system address spaces, including protection mechanisms. The virtualaddress space can be signi cantly larger than the physical main memory space.4Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.8. ARM program:Assume that a signed integer Divide instruction is available in the ARM instruction set, and that it has the same format as the Multiply (MUL) instruction (seeFigure B.4). The assembly language expression for the Divide (DIV) instructionisDIVRd,Rm,Rsand it performs the operation [Rm]/[Rs], loading the quotient into Rm and theremainder into 2,R3,R0R0,AR2,BR0,R0,R2R2,R0,R1R0,WLeaves c/d in R0.Leaves g h in R1.Leaves f /(g h) in R2.Leaves denominator in R1.Leaves a b in R0.Leaves result in R0.Stores result in w.This program requires 15 instructions as compared to 13 instruction words (somecombined instructions) in the HP3000.5Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
68000 program (assume 16-bit 0A,D1B,D1D1D0,D1D1,WLeaves g h in D0.Leaves e f in D1.Leaves (e f )/(g h) in D1.See Note below.Leaves c/d in D0.Leaves denominator in D0.See Note below.Leaves result in D1.Stores result in w.Note: The EXT.L instruction sign-extends the 16-bit dividend in the destinationregister to 32 bits, a requirement of the Divide instruction.This program contains 14 instructions, as compared to 13 instruction words(some combined instructions) in the HP3000.IA-32 X,EAXEAX,AEAX,BEBXW,EAXLeaves g h in EBX.Leaves e f in EAX.See Note below.Leaves (e f )/(g h) in EBX.See Note below.Leaves c/d in EAX.Leaves denominator in EBX.Leaves a b in EAX.See Note below.Leaves result in EAX.Stores result in w.Note: The CDQ instruction sign-extends EAX into EDX (see Section 3.23.1), arequirement of the Divide instruction.This program contains 16 instructions, as compared to 13 instruction words(some combined instructions) in the HP3000.6Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.9. A 4-way multiplexer is required, as shown in the following gure.32-bitdatapath in88884-way multiplexerMUXlow-order bytedatapath out11.10. There are no direct counterparts of the memory stack pointer registers SP and FPin the IA-64 architecture. The register remapping hardware in IA-64 processorsallows the main program and any sequence of nested subroutines to all use logical register addresses R32 and upward for their own local variables, with the rstpart of that register space containing parameters passed from the calling routine.An example of this is shown in Figure 11.4.If the 92 registers of the stacked physical register space are used up by registerallocations for a sequence of nested subroutine calls, then some of those physicalregisters must be spilled into memory to create physical register space for anyadditional nested subroutines. The memory pointer register used by the processor for that memory area could be considered as a counterpart of SP; but it is notactually used as a TOS pointer by the current routine. In fact, it is not visible touser programs.7Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.11. Consider the example of a main program calling a subroutine, as shown in Figure 11.4. The physical register addresses of registers used by the main programare the same as the logical register addresses used in the main program instructions. However, the logical register addresses above 31 used by instructions inthe subroutine must have 8 added to them to generate the correct physical registeraddresses.The value 8 is the rst operand in the Alloc 8,4 instruction executed by the mainprogram. When that instruction is executed, the value 8 is stored in a processorstate register associated with the main program. After the subroutine is entered,all logical register addresses above 31 issued by its instructions must be added,in a small adder, to the value (8) in that register. The output of this adder is thephysical register address to be used while in the subroutine.The operand 7 in the Alloc 7,3 instruction executed by the subroutine is storedin a second processor state register associated with the subroutine. The output ofthat register is added in a second adder to the output of the rst adder. After thesubroutine calls a second subroutine, logical register addresses above 31 issuedby the second subroutine are sent into the rst adder. The output of the secondadder (logical address 8 7) is the physical register address used while in thesecond subroutine.More register/adder pairs are cascaded onto this structure as more subroutinesare called. Note that logical register addresses above 31 are always applied tothe rst adder; and the output of the nth adder is the physical register addressto be used in the nth subroutine. All registers and adders are only 7 bits widebecause the largest physical register address that needs to be generated is 127.8Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.12. Considering cacheing effects only, the average access time over both instructionand data accesses is a function of both cache hit rates and miss penalties (seeSections 5.6.2 and 5.6.3 for general expressions for average access time).The hit rates in the 21264 L1 caches will be much higher than in the 21164 L1caches because the 21264 caches are eight times larger. Therefore, the averageaccess time for accesses that can be made on-chip will be larger in the 21164because of the miss penalty in going to its on-chip L2 cache.Next, we need to consider the effect on average access time of going to the offchip caches in each system. The total on-chip cache capacity (112K bytes inthe 21164 and 128K bytes in the 21264) is about the same in both the systems.Therefore, we can assume about the same hit rate for on-chip accesses; so theeffect on average access time of the miss penalties in going to the off-chip cacheswill be about the same in each system.Finally, if the off-chip caches have about the same capacity, the effect on averageaccess times of the miss penalties in going to the main DRAM memories will beabout the same in each sytem.The net result is that average access times in the 21264 should be shorter than inthe 21164, leading to faster program execution, primarily because of the differentarrangements of the on-chip caches.11.13. HP3000 DELABCDEFGHICombined with previousinstruction.ADDMPYSTORCombined with previousinstruction.W9Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.14. Procedurei generates 8 words of data, Procedurej generates 10 words of data,and Procedurek generates 3 words of data. Then, the top words in the stack havethe following contents:[Indexreg.]iReturn addressi[SR]i QiDI1 DI812[Indexreg.] jReturn address j[SR] j12DJ1 DJ1014[Indexreg.]kReturn addressk[SR]k14DK1DK2DK3TOS10Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
11.15. HP3000 RM 00 program (assume 16-bit 0C,D1D,D1D1,D0D,D1E,D1D1,D0D0,W11Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
IA-32 ,CEBX,DEAX,EBXEBX,DEBX,EEAX,EBXW,EAX11.16. Four11.17. Four and two12Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright 2006 - The McGraw-Hill Companies srl
values of variables w,a,b,c,d, and e are stored in memory locations. The following assumptions are made. The addresses do not reference successive locations. Direct memory addressing in the DB relative mode is used in the HP3000. Absolute/Direct Introduzione all'architettura dei calcolatori 2/ed - Carl Hamache
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