Chapter 8 –Timing Closure - Vlsicad Page
KLMHChapter 8 – Timing ClosureVLSI Physical Design: From Graph Partitioning to Timing ClosureOriginal Authors:VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure1LienigAndrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
KLMHChapter 8 – Timing Closure8.1Introduction8.2Timing Analysis and Performance Constraints8.2.1 Static Timing Analysis8.2.2 Delay Budgeting with the Zero-Slack Algorithm8.3 Timing-Driven Placement8.3.1 Net-Based Techniques8.3.2 Embedding STA into Linear Programs for Placement8.4 Timing-Driven Routing8.4.1 The Bounded-Radius, Bounded-Cost Algorithm8.4.2 Prim-Dijkstra Tradeoff8.4.3 Minimization of Source-to-Sink Delay8.5 Physical Synthesis8.5.1 Gate Sizing8.5.2 Buffering8.5.3 Netlist Restructuring8.6 Performance-Driven Design FlowVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure2Lienig8.7 Conclusions
Introduction KLMH8.1System SpecificationPartitioningArchitectural DesignENTITY test isport a: in bit;end ENTITY test;Functional Designand Logic DesignChip PlanningCircuit DesignPlacementPhysical DesignDRCLVSERCPhysical Verificationand SignoffClock Tree SynthesisSignal RoutingFabricationTiming ClosurePackaging and TestingVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure3LienigChip
Introduction KLMH8.1 IC layout must satisfy geometric constraints and timing constraints Setup (long-path) constraints Hold (short-path) constraints Chip designers must complete timing closure Optimization process that meets timing constraintsVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure4Lienig Integrates point optimizations discussed in previous chapters, e.g.,placement and routing, with specialized methods to improve circuit performance
Introduction KLMH8.1Components of timing closure covered in this lecture: Timing-driven placement (Sec. 8.3) minimizes signal delayswhen assigning locations to circuit elements Timing-driven routing (Sec. 8.4) minimizes signal delayswhen selecting routing topologies and specific routes Physical synthesis (Sec. 8.5) improves timing by changing the netlist. Sizing transistors or gates: increasing the width:length ratio of transistorsto decrease the delay or increase the drive strength of a gate Inserting buffers into nets to decrease propagation delays Restructuring the circuit along its critical pathsPerformance-driven physical design flow (Sec. 8.6)VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure5Lienig
Introduction KLMH8.1 Timing optimization engines must estimate circuit delays quickly and accuratelyto improve circuit timing Timing optimizers adjust propagation delays through circuit components,with the primary goal of satisfying timing constraints, including Setup (long-path) constraints, which specify the amount of time a data input signalshould be stable (steady) before the clock edge for each storage element(e.g., flip-flop or latch) Hold-time (short-path) constraints, which specify the amount of time a data inputsignal should be stable after the clock edge at each storage elementVLSI Physical Design: From Graph Partitioning to Timing Closuret combDelay t hold t skewChapter 8: Timing Closure6Lienigt cycle t combDelay t setup t skew
Introduction Timing closure is the process of satisfying timing constraintsthrough layout optimizations and netlist modifications Industry jargon: “the design has closed timing”VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure7Lienig KLMH8.1
Timing Analysis and Performance Constraints KLMH8.28.1Introduction8.2Timing Analysis and Performance Constraints8.2.1 Static Timing Analysis8.2.2 Delay Budgeting with the Zero-Slack Algorithm8.3 Timing-Driven Placement8.3.1 Net-Based Techniques8.3.2 Embedding STA into Linear Programs for Placement8.4 Timing-Driven Routing8.4.1 The Bounded-Radius, Bounded-Cost Algorithm8.4.2 Prim-Dijkstra Tradeoff8.4.3 Minimization of Source-to-Sink Delay8.5 Physical Synthesis8.5.1 Gate Sizing8.5.2 Buffering8.5.3 Netlist Restructuring8.6 Performance-Driven Design FlowVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure8Lienig8.7 Conclusions
Timing Analysis and Performance Constraints KLMH8.2Sequential circuit, “unrolled” in timeCombinationalLogicFFCopy 1CombinationalLogicCopy 2FFCombinationalLogicFFCopy 3Combinational logicVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure9LienigStorage elements 2011 Springer VerlagClock
Timing Analysis and Performance Constraints KLMH8.2 Main delay concerns in sequential circuits Gate delays are due to gate transitions Wire delays are due to signal propagation along wires Clock skew is due to the difference in time the sequential elements activate Need to quickly estimate sequential circuit timing Perform static timing analysis (STA)VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure10Lienig Assume clock skew is negligible, postpone until after clock network synthesis
Static Timing Analysis KLMH8.2.1 STA: assume worst-case scenario where every gate transitions Given combinational circuit, represent as directed acyclic graph (DAG) Every edge (node) has weight wire (gate) delay Compute the slack RAT – AAT for each node RAT is the required arrival time, latest time signal can transition AAT is the actual arrival time, latest possible transition time By convention, AAT is defined at the output of every node Negative slack at any output means the circuit does not meet timingVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure11Lienig Positive slack at all outputs means the circuit meets timing
Static Timing Analysis KLMH8.2.1Combinational circuit as DAG(0.15)ay (2)(0.2)w (2)(0.2)f(0.1)(0.1) x (1)(0.3)z (2)(0.1)a (0)(0)(0)y (2)(0.15)(0.1)b (0) (0.1)(0.2)w (2) (0.2)x (1)(0.3)(0.6)c (0)(0.1)VLSI Physical Design: From Graph Partitioning to Timing Closuref (0)(0.25)z (2)Chapter 8: Timing Closure12Lienigcs(0.25) 2011 Springer Verlagb
Static Timing Analysis KLMH8.2.1Compute AATs at each node:AAT (v) max ( AAT (u ) t (u, v) )u FI ( v )where FI(v) is the fanin nodes, and t(u,v) is the delay between u and v(AATs of inputs are given)y (2)(0.15)A 3.2(0)s(0)A0(0.1)b (0) (0.1)A0w (2) (0.2)x (1)A 1.1(0.6)c (0)(0.2)A 5.65(0.3)(0.1)A 0.6VLSI Physical Design: From Graph Partitioning to Timing Closuref (0)A 5.85(0.25)z (2)A 3.4Chapter 8: Timing Closure13LienigA0 2011 Springer Verlaga (0)
Static Timing Analysis KLMH8.2.1Compute RATs at each node:RAT (v) min (RAT (u ) t (u, v) )u FO ( v )where FO(v) are the fanout nodes, and t(u,v) is the delay between u and v(RATs of outputs are given)y (2)(0.15)R 3.1(0)s(0)R -0.35(0.1)b (0) (0.1)R -0.35w (2) (0.2)x (1)R 0.75(0.6)c (0)(0.2)R 5.3(0.3)(0.1)R 0.95VLSI Physical Design: From Graph Partitioning to Timing Closuref (0)R 5.5(0.25)z (2)R 3.05Chapter 8: Timing Closure14LienigR 0.95 2011 Springer Verlaga (0)
Static Timing Analysis KLMH8.2.1Compute slacks at each node:slack (v) RAT (v) AAT (v)A0R -0.35S -0.35(0)b (0) (0.1)(0.6)A0R -0.35S -0.35c (0)A 3.2(0.1) R 3.1 (0.2)S -0.1w (2) (0.2)x (1)A 1.1R 0.75 (0.3)S -0.35(0.1)A 0.6R 0.95S 0.35VLSI Physical Design: From Graph Partitioning to Timing ClosureA 5.65(0.25) R 5.3S -0.35f (0)A 5.85R 5.5S -0.35z (2)A 3.4R 3.05S -0.35Chapter 8: Timing Closure15Lienigs(0)A0R 0.95S 0.95y (2)(0.15) 2011 Springer Verlaga (0)
Delay Budgeting with the Zero-Slack Algorithm KLMH8.2.2 Establish timing budgets for nets Gate and wire delays must be optimized during timing driven layout design Wire delays depend on wire lengths Wire lengths are not known until after placement and routing Delay budgeting with the zero-slack algorithm Let vi be the logic gates Let ei be the nets Let DELAY(v) and DELAY(e) be the delay of the gate and net, respectivelyVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure16Lienig Define the timing budget of a gate TB(v) DELAY(v) DELAY(e)
Delay Budgeting with the Zero-Slack Algorithm KLMH8.2.2Input: timing graph G(V,E)Output: timing budgets TB for each v V1. do2.(AAT,RAT,slack) STA(G)3.foreach (vi V)4.TB[vi] DELAY(vi) DELAY(ei)5.slackmin 6.foreach (v V)7.if ((slack[v] slackmin) and (slack[v] 0))8.slackmin slack[v]9.vmin v10. if (slackmin )11.path vmin12.ADD TO FRONT(path,BACKWARD PATH(vmin,G))13.ADD TO BACK(path,FORWARD PATH(vmin,G))14.s slackmin / path 15.for (i 1 to path )16.node path[i]// evenly distribute17.TB[node] TB[node] s// slack along pathVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure17Lienig18. while (slackmin )
Delay Budgeting with the Zero-Slack Algorithm KLMH8.2.2Forward Path Search (FORWARD PATH(vmin,G))Input: node vmin with minimum slack slackmin, timing graph GOutput: maximal downstream path path from vmin such that no node v V affectsthe slack of path1. path vmin2. do3.flag false4.node LAST ELEMENT(path)5.foreach (fanout node fo of node)6.if ((RAT[fo] RAT[node] TB[fo]) and (AAT[fo] AAT[node] TB[fo]))7.ADD TO BACK(path,fo)8.flag true9.break10. while (flag true)VLSI Physical Design: From Graph Partitioning to Timing Closure// remove vminChapter 8: Timing Closure18Lienig11. REMOVE FIRST ELEMENT(path)
Delay Budgeting with the Zero-Slack Algorithm KLMH8.2.2Backward Path Search (BACKWARD PATH(vmin,G))Input: node vmin with minimum slack slackmin, timing graph GOutput: maximal upstream path path from vmin such that no node v V affects theslack of path1.path vmin2.do3.flag false4.node FIRST ELEMENT(path)5.foreach (fanin node fi of node)6.if ((RAT[fi] RAT[node] – TB[fi]) and (AAT[fi] AAT[node] – TB[fi]))7.ADD TO FRONT(path,fi)8.flag true9.break10. while (flag true)VLSI Physical Design: From Graph Partitioning to Timing Closure// remove vminChapter 8: Timing Closure19Lienig11. REMOVE LAST ELEMENT(path)
Timing-Driven Placement KLMH8.38.1Introduction8.2Timing Analysis and Performance Constraints8.2.1 Static Timing Analysis8.2.2 Delay Budgeting with the Zero-Slack Algorithm8.3 Timing-Driven Placement8.3.1 Net-Based Techniques8.3.2 Embedding STA into Linear Programs for Placement8.4 Timing-Driven Routing8.4.1 The Bounded-Radius, Bounded-Cost Algorithm8.4.2 Prim-Dijkstra Tradeoff8.4.3 Minimization of Source-to-Sink Delay8.5 Physical Synthesis8.5.1 Gate Sizing8.5.2 Buffering8.5.3 Netlist Restructuring8.6 Performance-Driven Design FlowVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure20Lienig8.7 Conclusions
Timing-Driven Placement KLMH8.3 Timing-driven placement optimizes circuit delay Let T be the set of all timing endpoints Circuit delay is measured by worst negative slack (WNS)WNS min(slack ( τ) )τ Τ Or total negative slack (TNS)TNS slack (τ)τ Τ, slack ( τ ) 0Classifications: net-based, path-based, integratedVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure21Lienig
Net-Based Techniques KLMH8.3.1 Net weights are added to each net – placer optimizes weighted wirelength Static net weights: computed before placement (never changes) ω1 if slack 0w Discrete net weights:where ω1 0, ω2 0, and ω2 ω1slackωif 0 2slack Continuous net weights: w 1 t αwhere t is the longest path delayand α is a criticality exponent Based on net sensitivity to TNS and slackVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure22Lienigw wo α( slack target slack ) s wSLACK β s wTNS
Net-Based Techniques KLMH8.3.1 Dynamic net weights: (re)computed during placement Estimate slack at every iteration:slack k slack k 1 s LDELAY Lwhere L is the change in wirelength 1 2 (υ k 1 1) if among the top 3% of critical nets Update net criticality: υ k 1 υ k 1otherwise 2 Update net weight:Variations include updating every j iterations, different relationsbetween criticality and net weightVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure23Lienig wk wk 1 (1 υ k )
Embedding STA into Linear Programs for Placement KLMH8.3.2 Construct a set of constraints for timing-driven placement Physical constraints define locations of cells Timing constraints define slack requirements Optimize an optimization objective Improving worst negative slack (WNS) Improving total negative slack (TNS)VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure24Lienig Improving a combination of both WNS and TNS
Embedding STA into Linear Programs for Placement KLMH8.3.2 For physical constraints, let: xv and yv be the center of cell v V Ve be the set of cells connected to net e E left(e), right(e), bottom(e), and top(e) respectively be the coordinatesof the left, right, bottom, and top boundaries of e’s bounding boxVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure25Lienig δx(v,e) and δy(v,e) be pin offsets from xv and yv for v’s pin connected to e
Embedding STA into Linear Programs for Placement KLMH8.3.2 Then, for all v Ve:left(e) xv δ x (v, e)right(e) xv δ x (v, e)bottom(e) yv δ y (v, e)top(e) yv δ y (v, e) Define e’s half-perimeter wirelength (HPWL):VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure26LienigL(e) right (e) left (e) top (e) bottom (e)
Embedding STA into Linear Programs for Placement KLMH8.3.2 For timing constraints, let tGATE(vi,vo) be the gate delay from an input pin vi to the output pin vo for cell v tNET(e,uo,vi) be net e’s delay from cell u’s output pin uo to cell v’s input pin viVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure27Lienig AAT(vj) be the arrival time on pin j of cell v
Embedding STA into Linear Programs for Placement KLMH8.3.2 For every input pin vi of cell v :AAT (vi ) AAT (u o ) t NET (u o , vi ) For every output pin vo of cell v :AAT (vo ) AAT (vi ) tGATE (vi , vo ) For every pin τp in a sequential cell τ:slack ( τ p ) RAT ( τ p ) AAT ( τ p )Ensure that every slack(τp) 0VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure28Lienig
Embedding STA into Linear Programs for Placement KLMH8.3.2 Optimize for total negative slack:max : slack (τp)τ p Pins ( τ ), τ Τ Optimize for worst negative slack:max : WNS Optimize for both TNS and WNS:min : L(e) α WNSVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure29Lienige E
Timing-Driven Routing KLMH8.48.1Introduction8.2Timing Analysis and Performance Constraints8.2.1 Static Timing Analysis8.2.2 Delay Budgeting with the Zero-Slack Algorithm8.3 Timing-Driven Placement8.3.1 Net-Based Techniques8.3.2 Embedding STA into Linear Programs for Placement8.4 Timing-Driven Routing8.4.1 The Bounded-Radius, Bounded-Cost Algorithm8.4.2 Prim-Dijkstra Tradeoff8.4.3 Minimization of Source-to-Sink Delay8.5 Physical Synthesis8.5.1 Gate Sizing8.5.2 Buffering8.5.3 Netlist Restructuring8.6 Performance-Driven Design FlowVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure30Lienig8.7 Conclusions
Timing-Driven Routing KLMH8.4 Timing-driven routing seeks to minimize: Maximum sink delay: delay from the source to any sink in a net Total wirelength: routed length of the net For a signal net net, let s0 be the source node sinks {s1, ,sn} be the sinks G (V,E) be a corresponding weighted graph where: V {v0,v1, ,vn} represents the source and sink nodes of net, andVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure31Lienig the weight of an edge e(vi,vj) E represents the routing cost between vi and vj
Timing-Driven Routing KLMH8.4 For any spanning tree T over G, let: radius(T) be the length of the longest source-sink path in T cost(T) be the total edge weight of T Trade off between “shallow” and “light” trees “Shallow” trees have minimum radius Shortest-paths tree Constructed by Dijkstra’s Algorithm “Light” trees have minimum cost Minimum spanning tree (MST)VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure32Lienig Constructed by Prim’s Algorithm
Timing-Driven Routing KLMH8.423223366755s0s0radius(T) 8cost(T) 20radius(T) 13cost(T) 13radius(T) 11cost(T) 16“Shallow”“Light”Tradeoff betweenshallow and lightVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure33Lienigs0 2011 Springer Verlag5
The Bounded-Radius, Bounded-Cost Algorithm KLMH8.4.1 Trades off radius for cost by setting upper bounds on both In the bounded-radius, bounded-cost (BRBC) algorithm, let: TS be the shortest-paths tree TM be the minimum spanning tree TBRBC is the tree constructed with parameter ε that satisfies:radius (TBRBC ) (1 ε ) radius (TS )and When ε 0, TBRBC has minimum radius When ε , TBRBC has minimum costVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure34Lienig 2 cost (TBRBC ) 1 cost (TM ) ε
Prim-Dijkstra Tradeoff KLMH8.4.2 Prim-Dijkstra Tradeoff based on Prim’s algorithm and Dijkstra’s algorithm From the set of sinks S, iteratively add sink s based on different cost function Prim’s algorithm cost function: Dijkstra’s algorithm cost function: Prim-Dijkstra Tradeoff cost function:cost ( s0 , si ) cost ( si , s j )γ cost ( s0 , si ) cost ( si , s j )γ is a constant between 0 and 1VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure35Lienig cost ( si , s j )
Prim-Dijkstra Tradeoff KLMH8.4.2447117s09s0radius(T) 19cost(T) 35radius(T) 15cost(T) 39γ 0.25γ 0.75VLSI Physical Design: From Graph Partitioning to Timing Closure7Chapter 8: Timing Closure36Lienig98 2011 Springer Verlag8
Minimization of Source-to-Sink Delay KLMH8.4.3 Iteratively forms a tree by adding sinks, and optimizes for critical sink(s) In the critical-sink routing tree (CSRT) problem, minimize:n α(i) t (s , s )0ii 1VLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure37Lienigwhere α(i) are sink criticalities for sinks si, and t(s0,si) is the delay from s0 to si
Minimization of Source-to-Sink Delay KLMH8.4.3 In the critical-sink Steiner tree problem, construct aminimum-cost Steiner tree T for all sinks except for the most critical sink sc Add in the critical sink by: H0: a single wire from sc to s0 H1: the shortest possible wire that can join sc to T, so long as the pathfrom s0 to sc is the shortest possible total lengthVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure38Lienig HBest: try all shortest connections from sc to edges in T and from sc to s0.Perform timing analysis on each of these trees and pick the onewith the lowest delay at sc
Physical Synthesis KLMH8.58.1Introduction8.2Timing Analysis and Performance Constraints8.2.1 Static Timing Analysis8.2.2 Delay Budgeting with the Zero-Slack Algorithm8.3 Timing-Driven Placement8.3.1 Net-Based Techniques8.3.2 Embedding STA into Linear Programs for Placement8.4 Timing-Driven Routing8.4.1 The Bounded-Radius, Bounded-Cost Algorithm8.4.2 Prim-Dijkstra Tradeoff8.4.3 Minimization of Source-to-Sink Delay8.5 Physical Synthesis8.5.1 Gate Sizing8.5.2 Buffering8.5.3 Netlist Restructuring8.6 Performance-Driven Design FlowVLSI Physical Design: From Graph Partitioning to Timing ClosureChapter 8: Timing Closure39Lienig8.7 Conclusions
Physical Synthesis KLMH8.5 Physical synthesis is a collection of timing optimiza
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 2 KLMH Lienig Chapter 8 –Timing Closure 8.1 Introduction 8.2 Timing Analysis and Performance Constraints 8.2.1 Static Timing Analysis 8.2.2 Delay Budgeting with the Zero-Slack Algorit
Part One: Heir of Ash Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Chapter 25 Chapter 26 Chapter 27 Chapter 28 Chapter 29 Chapter 30 .
Timing Closure User Guide www.xilinx.com 9 UG612 (v 14.3) October 16, 2012 Chapter 1 Introduction The Timing Closure User Guide (UG612) addresses timing closure in high-performance applications. The Guide is designed for all FPGA designers, from beginners to advanced. The high performance of today's Xilinx devices can overcome the speed .
timing pulleys timing pulleys with pilot bore type mxl - xl - l - h - xh page 4 export timing pulleys type xl - l - h page 20 taper-lock timing pulleys type l - h page 29 htd timing pulleys with pilot bore type 3m - 5m - 8m - 14m page 38 htd taper lock timing pulleys type 5m - 8m - 14m page 54 gt timing pulleys type 3mr - 5mr page 65 poly chain gt timing pulleys
TO KILL A MOCKINGBIRD. Contents Dedication Epigraph Part One Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Part Two Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18. Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Chapter 25 Chapter 26
practices for timing closure in FPGA designs to resolve any timing violations that exist in the FPGA core. 1 If you are using the Quartus II software version 9.1 SP1 or earlier,Altera strongly recommends upgrading to the latest software version.Achieving timing closure is
DEDICATION PART ONE Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 PART TWO Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 .
Drive Belt Tensioner Drive Belt Tensioner Damper M/T Air Cleaner Duct Oil Filler Cap No.3 Timing Belt Cover Gasket No.2 Timing Belt Cover No.5 Air Hose Water Pump Pulley Drive Belt Camshaft Timing Pulley Drive Belt Tensioner Hold-Down Clamp Idler Pulley Battery Insulator Battery Tray Battery Timing Belt Gasket No.1 Timing Belt Cover Crankshaft .
1) General characters, structure, reproduction and classification of algae (Fritsch) 2) Cyanobacteria : General characters, cell structure their significance as biofertilizers with special reference to Oscillatoria, Nostoc and Anabaena.
