AFBR-5903Z/5903EZ/5903AZ FDDI, Fast Ethernet Transceivers .
AFBR-5903Z/5903EZ/5903AZFDDI, Fast Ethernet Transceiversin 2 x 5 Package StyleData SheetDescriptionFeaturesThe AFBR-5903Z family of trans ceivers from Avago Technologies provide the system designer with productsto implement a range of FDDI and ATM (AsynchronousTransfer Mode) designs at the 100 Mb/s-125 MBd rate. Multisourced 2 x 5 package style with MT-RJreceptacle Single 3.3 V power supply Wave solder and aqueous wash process compatible Full compliance with the optical performancerequirements of the FDDI PMD standard Full compliance with the FDDI LCF-PMD standard Full compliance with the optical performancerequirements of the ATM 100 Mb/s physical layer Full compliance with the optical performancerequirements of 100 Base‑FX version of IEEE 802.3u “RoHS” compliance Receiver output squelch function enabledThe transceivers are all supplied in the new industrystandard 2 x 5 DIP style with a MT-RJ fiber connectorinterface.FDDI PMD, ATM and Fast Ethernet 2 km Backbone LinksThe AFBR-5903Z is a 1300 nm product with optical performance compliant with the FDDI PMD standard. TheFDDI PMD standard is ISO/IEC 9314‑3: 1990 and ANSIX3.166 - 1990.These transceivers for 2 km multimode fiber backbonesare supplied in the small 2 x 5 MT-RJ package style forthose designers who want to avoid the larger MIC/R(Media Interface Connector/Receptacle) defined in theFDDI PMD standard.Avago Technologies also provides several other FDDIproducts compliant with the PMD and SM-PMD standards.These products are available with MIC/R, ST , SC and FCconnector styles. They are available in the 1 x 9, 1 x 13 and2 x 11 transceiver and 16 pin transmitter/receiver package styles for those designs that require these alternateconfigurations.The AFBR-5903Z is also useful for both ATM 100 Mb/sinterfaces and Fast Ethernet 100 Base-FX interfaces. TheATM Forum User-Network Interface (UNI) Standard, Version3.0, defines the Physical Layer for 100 Mb/s MultimodeFiber Interface for ATM in Section 2.3 to be the FDDI PMDStandard. Likewise, the Fast Ethernet Alliance defines thePhysical Layer for 100 Base-FX for Fast Ethernet to be theFDDI PMD Standard.ATM applications for physical layers other than 100Mb/s Multimode Fiber Interface are supported byAvago Technologies. Products are available for boththe single-mode and the multi mode fiber SONET OC-3c(STS‑3c), SDH (STM-1) ATM interfaces and the 155 Mb/s194 MBd multi mode fiber ATM interface as specifiedin the ATM Forum UNI.Applications Multimode fiber backbone links Multimode fiber wiring closet to desktop linksOrdering InformationThe AFBR-5903Z 1300 nm product is avail able for production orders through the Avago Technologies Component Field Sales Offices and Auth orized Distributorsworld wide.AFBR-5903Z 0 C to 70 CNo ShieldAFBR-5903EZ 0 C to 70 CExtended ShieldAFBR-5903AZ -40 C to 85 CNo Shield.Contact your Avago Technologies sales representative for infor ma tion on these alternative FDDI and ATMproducts.
Transmitter SectionsPackageThe transmitter section of the AFBR-5903Z utilizes a 1300nm Surface Emitting InGaAsP LED. This LED is packagedin the optical subassembly portion of the transmittersection. It is driven by a custom silicon IC which convertsdifferential PECL logic signals, ECL referenced (shifted) toa 3.3 V supply, into an analog LED drive current.The overall package concept for the Avago Technologiestransceiver consists of the following basic elements; twooptical subassemblies, an electrical subassembly and thehousing as illustrated in Figure 1.Receiver SectionsThe receiver section of the AFBR-5903Z utilizes an InGaAsPIN photo diode coupled to a custom silicon transimpedance preampli fier IC. It is packaged in the optical sub assembly portion of the receiver.This PIN/preamplifier com bi nation is coupled to a customquantizer IC which provides the final pulse shaping forthe logic output and the Signal Detect function. The Dataoutput is dif ferential. The Signal Detect output is singleended. Both Data and Signal Detect outputs are PECLcompat ible, ECL referenced (shifted) to a 3.3 V powersupply. The receiver outputs, Data Out and Data Out Bar,are squelched at Signal Detect Deassert. That is, when thelight input power decreases to a typical -38 dBm or less,the Signal Detect Deasserts, i.e. the Signal Detect outputgoes to a PECL low state. This forces the receiver outputs,Data Out and Data Out Bar to go to steady PECL levelsHigh and Low respectively.The package outline drawing and pin out are shown in Figures2 and 3. The details of this package outline and pin out arecompliant with the multi source definition of the 2 x 5 DIP.The low profile of the Avago Technologies transceiver designcomplies with the maximum height allowed for the MT-RJconnector over the entire length of the package.The optical subassemblies utilize a high-volume assemblyprocess together with low-cost lens elements which resultin a cost-effective building block.The electrical subassembly con sists of a high volume multilayer printed circuit board on which the IC and varioussurface-mounted passive circuit elements are attached.The receiver section includes an internal shield for the electrical and optical subassemblies to ensure high immunity toexternal EMI fields.The outer housing is electrically conductive and is at receiversignal ground potential. The MT-RJ port is molded of fillednonconductive plastic to provide mechanical strengthand electrical isolation. The solder posts of the AvagoTechnologies design are isolated from the internal circuitof the transceiver.The transceiver is attached to a printed circuit board withthe ten signal pins and the two solder posts which exitthe bottom of the housing. The two solder posts providethe primary mechanical strength to withstand the loadsimposed on the trans ceiver by mating with the MT-RJconnectored fiber cables.RX SUPPLYDATA OUTDATA OUTQUANTIZER ICSIGNALDETECTPIN PHOTODIODEPRE-AMPLIFIERSUBASSEMBLYR X GROUNDMT-RJRECEPTACLETX GROUNDDATA INDATA INLED DRIVER ICTX SUPPLYFigure 1. Block Diagram. LED OPTICALSUBASSEMBLY
13.97(0.55)MIN.4.5 0.2(0.177 0.008)(PCB to OPTICSCENTER LINE)5.15(0.20)(PCB to OVERALLRECEPTACLE CENTERLINE)FRONT VIEWCase TemperatureMeasurement Point9.613.59(0.535) (0.378)MAX. MAX.TOP VIEW10.16(0.4)Pin .07)17.778(0.7) 0-0.2( 000)(0.024)(-008)Ø 0.617.112(0.28)49.56 (1.951) REF.37.56 (1.479) MAX.9.39.8(0.386) (0.366)MAX. MAX.SIDE VIEWMin 2.92(0.115)Ø 1.07(0.042)DIMENSIONS IN MILLIMETERS (INCHES)NOTES:1. THIS PAGE DESCRIBES THE MAXIMUM PACKAGE OUTLINE, MOUNTING STUDS, PINS AND THEIR RELATIONSHIPS TO EACH OTHER.2. TOLERANCED TO ACCOMMODATE ROUND OR RECTANGULAR LEADS.3. ALL 12 PINS AND POSTS ARE TO BE TREATED AS A SINGLE PATTERN.4. THE MT-RJ HAS A 750 µm FIBER SPACING.5. THE MT-RJ ALIGNMENT PINS ARE IN THE MODULE.6. FOR SM MODULES, THE FERRULE WILL BE PC POLISHED (NOT ANGLED).7. SEE MT-RJ TRANSCEIVER PIN OUT DIAGRAM FOR DETAILS.Figure 2. Package Outline DrawingLabelling InformationNote:YYWWCOO Manufactured WorkWeekCountry Of Origin (Philippines)
RXTXMountingStuds/SolderPostsTopViewRECEIVER SIGNAL GROUNDRECEIVER POWER SUPPLYSIGNAL DETECTRECEIVER DATA OUT BARRECEIVER DATA OUTooooo1234510 o9o8o7o6oTRANSMITTER DATA IN BARTRANSMITTER DATA INTRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY)TRANSMITTER SIGNAL GROUNDTRANSMITTER POWER SUPPLYFigure 3. Pin Out Diagram.Pin Descriptions:Pin 1 Receiver Signal Ground VEE RX:Directly connect this pin to the receiver ground plane.Pin 2 Receiver Power Supply VCC RX:Provide 3.3 V dc via the recommended receiver powersupply filter circuit. Locate the power supply filter circuitas close as possible to the VCC RX pin.Pin 3 Signal Detect SD:Normal optical input levels to the receiver result in a logic“1” output.Low optical input levels to the receiver result in a faultcondition indicated by a logic “0” output.Pin 7 Transmitter Signal Ground VEE TX:Directly connect this pin to the transmitter groundplane.Pin 8 Transmitter Disable TDIS:No internal connection. Optional feature for laser basedproducts only. For laser based products connect this pinto 3.3 V TTL logic high “1” to disable module. To enablemodule connect to TTL logic low “0”.Pin 9 Transmitter Data In TD :No internal terminations are provided. See recommendedcircuit schematic.This Signal Detect output can be used to drive a PECLinput on an upstream circuit, such as Signal Detect inputor Loss of Signal-bar.Pin 10 Transmitter Data In Bar TD-:Pin 4 Receiver Data Out Bar RD-:Mounting Studs/Solder PostsNo internal terminations are provided. See recommendedcircuit schematic.The mounting studs are provided for transceiver mechanical attachment to the circuit board. It is recommendedthat the holes in the circuit board be connected to chassisground.Pin 5 Receiver Data Out RD :No internal terminations are provided. See recommendedcircuit schematic.Pin 6 Transmitter Power Supply VCC TX:Provide 3.3 V dc via the recommended transmitter powersupply filter circuit. Locate the power supply filter circuitas close as possible to the VCC TX pin. No internal terminations are provided. See recommendedcircuit schematic.
Application InformationThe following information is provided to answer some of themost common questions about the use of these parts.Transceiver Optical Power Budget versus Link LengthOptical Power Budget (OPB) is the available optical powerfor a fiber optic link to accommodate fiber cable losses pluslosses due to in-line connectors, splices, optical switches,and to provide margin for link aging and unplanned lossesdue to cable plant reconfiguration or repair.Figure 4 illustrates the pre dicted OPB associated with thetransceiver specified in this data sheet at the Beginningof Life (BOL). These curves represent the attenuation andchromatic plus modal dispersion losses associated withthe 62.5/125 µm and 50/125 µm fiber cables only. The areaunder the curves represents the remaining OPB at any linklength, which is available for overcoming non-fiber cablerelated losses.Avago Technologies LED technol ogy has produced 1300nm LED devices with lower aging characteristics than normally associated with these technologies in the industry.The industry conven tion is 1.5 dB aging for 1300 nm LEDs.The Avago Technologies 1300 nm LEDs will experience lessthan 1 dB of aging over normal com mer cial equip mentmission life periods. Contact your Avago Technologiessales repre sentative for additional details. 10OPTICAL POWER BUDGET (dB)The Applications Engineering group is available to assistyou with the technical under standing and design trade-offsassociated with these trans ceivers. You can contact themthrough your Avago Technologies sales representative.12HFBR-5903, 62.5/125 µm86HFBR-590350/125 µm4201.01.52.00.3 0.5FIBER OPTIC CABLE LENGTH (km)2.5Figure 4. Typical Optical Power Budget at BOL versus Fiber Optic CableLength.Figure 4 was generated with a Avago Technologies fiberoptic link model containing the current industry conventions for fiber cable specifications and the FDDI PMDand LCF-PMD optical parameters. These parameters arereflected in the guaranteed performance of the transceiver specifications in this data sheet. This same modelhas been used extensively in the ANSI and IEEE committees, including the ANSI X3T9.5 committee, to establishthe optical performance require ments for various fiberoptic interface standards. The cable parameters usedcome from the ISO/IEC JTC1/SC 25/WG3 Generic Cablingfor Customer Premises per DIS 11801 docu ment and theEIA/TIA-568-A Commercial Building Telecom municationsCabling Standard per SP-2840.
Transceiver Signaling Operating Rate Range and BER Care should be used to avoid shorting the receiver data orsignal detect outputs directly to ground without properPerformanceThe transceivers may be used for other applications atsignal ing rates outside of the 10 MBd to 125 MBd rangewith some penalty in the link optical power budget primarily caused by a reduction of receiver sensitivity. Figure5 gives an indication of the typical performance of these1300 nm products at different rates.These transceivers can also be used for applications whichrequire different Bit Error Rate (BER) performance. Figure6 illustrates the typical trade-off between link BER and thereceivers input optical power level.Transceiver Jitter PerformanceThe Avago Technologies 1300 nm transceivers are designedto operate per the system jitter allocations stated in TableE1 of Annex E of the FDDI PMD and LCF-PMD standards.The Avago Technologies 1300 nm transmitters will toleratethe worst case input electrical jitter allowed in these tableswithout violating the worst case output jitter requirementsof Sections 8.1 Active Output Interface of the FDDI PMDand LCF-PMD standards.The Avago Technologies 1300 nm receivers will tolerate theworst case input optical jitter allowed in Sections 8.2 ActiveInput Interface of the FDDI PMD and LCF-PMD standardswithout violating the worst case output electrical jitterallowed in Table E1 of Annex E.The jitter specifications stated in the following 1300 nmtransceiver specification tables are derived from the valuesin Table E1 of Annex E. They represent the worst case jittercontribution that the trans ceivers are allowed to maketo the overall system jitter without violating the Annex Eallocation example. In practice the typical contribution ofthe Avago Technologies trans ceivers is well below thesemaximum allowed amounts.Solder and Wash Process CompatibilityThe transceivers are delivered with protective processplugs inserted into the MT-RJ connector receptacle. Thisprocess plug protects the optical subassemblies duringwave solder and aqueous wash processing and acts as adust cover during shipping.These transceivers are compat ible with either industrystandard wave or hand solder processes.Shipping ContainerThe transceiver is packaged in a shipping container designed to protect it from mechanical and ESD damageduring shipment or storage.1 x 10 -21 x 10 -3BIT ERROR RATEWhen used in FDDI and ATM 100 Mb/s applications theperformance of the 1300 nm transceivers is guaranteedover the signaling rate of 10 MBd to 125 MBd to the full conditions listed in individual product specification tables.current limiting impedance.1 x 10 -41 x 10 -6Avago Technologies recommends that normal staticprecautions be taken in the handling and assembly of these transceivers to prevent damage whichmay be induced by electrostatic discharge (ESD).The AFBR-5903Z series of transceivers meet MIL-STD-883CMethod 3015.4 Class 2 products. CENTER OF SYMBOL1 x 10 -71 x 10 -81 x 10 -91 x 10 -101 x 10 -111 x 10 -12-6-4-202RELATIVE INPUT OPTICAL POWER - dB4CONDITIONS:1. 125 MBd2. PRBS 2 7 -13. CENTER OF SYMBOL SAMPLING4. TA 25 C5. VCC 3.3 V dc6. INPUT OPTICAL RISE/FALL TIMES 1.0/ 2.1 ns.Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.2.521.510.50-0.5-1Recommended Handling PrecautionsHFBR-5903 SERIES1 x 10 -5TRANSCEIVER RELATIVE POWER BUDGETAT CONSTANT BER (dB)For purposes of definition, the symbol (Baud) rate, alsocalled signaling rate, is the reciprocal of the shortestsymbol time. Data rate (bits/sec) is the sym bol rate divided by the encoding factor used to encode the data(symbols/bit).0255075100125150175200SIGNAL RATE (MBd)CONDITIONS:1. PRBS 2 7-12. DATA SAMPLED AT CENTER OF DATA SYMBOL.3. BER 10 -64. TA 25 C5. VCC 3.3 V dc6. INPUT OPTICAL RISE/FALL TIMES 1.0/ 2.1 ns.Figure 5. Transceiver Relative Optical Power Budget at Constant BER vs.Signaling Rate.
Board Layout - Decoupling Circuit, Ground Planes andTermination CircuitsIt is important to take care in the layout of your circuit boardto achieve optimum perform ance from these transceivers.Figure 7 provides a good example of a schematic for apower supply decoupling circuit that works well with theseparts. It is further recommended that a continuous groundplane be provided in the circuit board directly under thetransceiver to provide a low inductance ground for signalreturn current. This recommen dation is in keeping withgood high frequency board layout practices. Figures 7 and8 show two recommended termination schemes.Board Layout - Hole PatternThe Avago Technologies trans ceiver complies with thecircuit board“Common Transceiver Footprint”hole patterndefined in the original multisource announce ment whichdefined the 2 x 5 package style. This drawing is repro ducedin Figure 9 with the addition of ANSI Y14.5M compliantdimensioning to be used as a guide in the mechani callayout of your circuit board.PHY DEVICEV CC( 3.3 V)TERMINATE ATTRANSCEIVER INPUTS1001 µHo RD V CCTX oo RD-N/C oV EE T X oTD oo SD3451LVPECLTD 130 Ω6TD- o72TXRX8o VCC R X9TD-Z 50 Ωo V EE R X10Z 50 ΩC2130 ΩV CC( 3.3 V)C310 µFV CC( 3.3 V)1 µHRD C1Z 50 Ω100 ΩLVPECLRD-Z 50 Ω130 Ω130 ΩZ 50 ΩV CC( 3.3V)130 ΩSD82 ΩNote: C1 C2 C3 10 nF or 100 nFFigure 7. Recommended Decoupling and Termination Circuits TERMINATE ATDEVICE INPUTS
TERMINATE ATTRANSCEIVER INPUTSPHY DEVICEV CC( 3.3 V)V CC( 3.3 V)10 nF130 Ω130 ΩZ 50 ΩTDLVPECLZ 50 Ω123482 Ω682 ΩV CCT X oV CC( 3.3V)1 µHV CC( 3.3 V)10 µF130 ΩRD 1 µHLVPECLZ 50 ΩRDV CC ( 3.3V)Z 50 Ω130 ΩZ 50 Ω10 nFTERMINATE AT DEVICE INPUTSØ 1.4 0.1(0.055 0.004)Spacing Of FrontHousing Leads Holes7.11Ø 1.4 0.1KEEP OUT AREA (0.055 0.004)(0.28)FOR PORT PLUG7(0.276)3.56(0.14)Holes ForHousingLeadsØ 1.4 0.1(0.055 0.004)10.16(0.4) 13.97(0.55)MIN.10.8(0.425)3.08(0.121)13.34 .112(0.28)9.59(0.378 )2(0.079)Ø 2.29(0.09)Ø 0.81 0.1(0.032 0.004)3.08(0.121)DIMENSIONS IN MILLIMETERS (INCHES)NOTES:1. THIS FIGURE DESCRIBES THE RECOMMENDED CIRCUIT BOARD LAYOUT FOR THE MT-RJTRANSCEIVER PLACED AT .550 SPACING.2. THE HATCHED AREAS ARE KEEP-OUT AREAS RESERVED FOR HOUSING STANDOFFS. NOMETAL TRACES OR GROUND CONNECTION IN KEEP-OUT AREAS.3. 10 PIN MODULE REQUIRES ONLY 16 PCB HOLES, INCLUDING 4 PACKAGE GROUNDING TABHOLES CONNECTED TO SIGNAL GROUND.4. THE SOLDER POSTS SHOULD BE SOLDERED TO CHASSIS GROUND FOR MECHANICALINTEGRITY AND TO ENSURE FOOTPRINT COMPATIBILITY WITH OTHER SFF TRANSCEIVERS.Figure 9. Recommended Board Layout Hole Pattern 82 Ω82 ΩFigure 8. Alternative Termination Circuits3(0.118)6(0.236)82 ΩSDNote: C1 C2 C3 10 nF or 100 nF27(1.063)130 Ω5C13(0.118)V CC( 3.3 V)10 nFC3C2o RD o RD-o V EE R Xo V CC R XTXRX7N/C oV EE T X oTD o8o SD9TD- o10TD
Regulatory ComplianceElectromagnetic Interference (EMI)These transceiver products are intended to enable commercial system designers to develop equipment that complies with the various international regulations governingcertifica tion of Information Technology Equipment. Seethe Regulatory Compliance Table for details. Additionalinformation is available from your Avago Technologiessales representative.Most equipment designs utilizing this high speed trans ceiver from Avago Technologies will be required to meetthe require ments of FCC in the United States, CENELECEN55022 (CISPR 22) in Europe and VCCI in Japan.Electrostatic Discharge (ESD)There are two design cases in which immunity to ESDdamage is important.The first case is during handling of the transceiver priorto mount ing it on the circuit board. It is important to usenormal ESD handling precautions for ESD sensitive devices.These pre cautions include using grounded wrist straps,work benches, and floor mats in ESD controlled areas.The second case to consider is static discharges to the exterior of the equipment chassis con taining the transceiverparts. To the extent that the MT-RJ connector is exposed tothe outside of the equipment chassis it may be subject towhatever ESD system level test criteria that the equipmentis intended to meet.ImmunityEquipment utilizing these transceivers will be subject toradio-frequency electromagnetic fields in some environments. These transceivers have a high immunity to suchfields.Transceiver Reliability and Performance QualificationDataThe 2 x 5 transceivers have passed Avago Technologies’reliabil ity and performance qualification testing and areundergoing ongoing quality and reliability monitoring.Details are avail able from your Avago Technologies salesrepresentative.Applications Support MaterialsContact your local Avago Technologies Component FieldSales Office for information on how to obtain evaluationboards for the 2 x 5 transceivers.Regulatory Compliance TableFeatureTest MethodPerformanceElectrostatic Discharge(ESD) to the Electrical PinsMIL-STD-883CMethod 3015.4Meets Class 2 (2000 to 3999 Volts).Withstand up to 2200 V applied between electrical pins.Electrostatic DischargeVariation ofESD) to the MT-RJ Receptacle IEC 801-2Typically withstand at least 25 kV without damage when the MTRJ Connector Receptacle is contacted by a Human Body Modelprobe.ElectromagneticInterference (EMI)FCC Class BCENELEC CEN55022VCCI Class 2Typically provide a 10 dB margin to the noted standards,however, it should be noted that final margin depends on thecustomer’s board and chasis design.ImmunityVariation of IEC61000-4-3Eye SafetyIEC 825 Issue 1 1993:11Class 1CENELEC EN60825 Class 1RoHS Compliance Typically show no measurable effect from a 10 V/m field sweptfrom 10 to 450 MHz applied to the transceiver when mounted toa circuit card without a chassis enclosure.Compliant per Avago Technologies testing under single faultconditions.TUV Certification: LED Class 1Reference to EU RoHS Directive 2002/95/EC
3.8(0.15 )10.8 0.1(0.425 0.004)1(0.039)9.8 0.1(0.386 0.004)0.25 0.1(0.01 0.004)(TOP OF PCB TOBOTTOM OFOPENING)13.97(0.55)MIN.14.79(0.589)DIMENSIONS IN MILLIMETERS (INCHES)Figure 10. Recommended Panel Mounting2001601401203.01.52.03.52.53.0t r/f - TRANSMITTEROUTPUT OPTICAL3.5100RELATIVE INPUT OPTICAL POWER (dB) λ - TRANSMITTER OUTPUT OPTICALSPECTRAL WIDTH (FWHM) - nm18061200RISE/FALL TIMES - ns13001320134013601380λ C - TRANSMITTER OUTPUT OPTICALCENTER WAVELENGTH - nmHFBR-5903 FDDI TRANSMITTER TEST RESULTSOF λC, λ AND tr/f ARE CORRELATED ANDCOMPLY WITH THE ALLOWED SPECTRAL WIDTHAS A FUNCTION OF CENTER WAVELENGTH FORVARIOUS RISE AND FALL TIMES.Figure 11. Transmitter Output Optical Spectral Width (FWHM) vs. Transmitter Output Optical Center Wavelength and Rise/Fall Times.542.5 x 10 -10 BER321.0 x 10-12 BER10-4-3-2-101234EYE SAMPLING TIME POSITION (ns)CONDITIONS:1.TA 25 C2. VCC 3.3 V dc3. INPUT OPTICAL RISE/FALL TIMES 1.0/2.1 ns.4. INPUT OPTICAL POWER IS NORMALIZED TOCENTER OF DATA SYMBOL.5. NOTE 19 AND 20 APPLY.Figure 13. Relative Input Optical Power vs. Eye Sampling Time Position.10
LATIVE AMPLITUDE100% TIMEINTERVAL40 0.70.50 0.725 0.7250% 54.400.52510.04.85080 500 ppmTIME - nsTHE AFBR-5903 OUTPUT OPTICAL PULSE SHAPE SHALL FIT WITHIN THE BOUNDARIES OF THEPULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.Figure 12. Output Optical Pulse Envelope.-31.0 dBmP A (P O 1.5 dB P A -31.0 dBm)MIN (P O 4.0 dB OR -31.0 dBm)OPTICAL POWERPO MAX (PS OR -45.0 dBm)(PS INPUT POWER FOR BER 10 2 )INPUT OPTICAL POWER( 1.5 dB STEP INCREASE)INPUT OPTICAL POWER( 4.0 dB STEP DECREASE)-45.0 dBmSIGNALDETECTOUTPUTSIGNAL DETECT(ON)ANS MAXAS MAXSIGNAL DETECT (OFF)TIMEAS MAX - MAXIMUM ACQUISITION TIME (SIGNAL).AS MAX IS THE MAXIMUM SIGNAL DETECT ASSERTION TIME FOR THE STATION.AS MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS MAX IS 100.0 µs.ANS MAX - MAXIMUM ACQUISITION TIME (NO SIGNAL).ANS MAX IS THE MAXIMUM SIGNAL DETECT DEASSERTION TIME FOR THE STATION.ANS MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS MAX IS 350 µs.Figure 14. Signal Detect Thresholds and Timing.111.5250.525
Absolute Maximum RatingsStresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to eachparameter in isolation, all other parameters having values within the recommended operating conditions. It should notbe assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposureto the absolute maximum ratings for extended periods can adversely affect device reliability.ParameterSymbolMinimumStorage TemperatureTS-40Lead Soldering TemperatureTypicalMaximumUnit 100 CTSOLD 260 CLead Soldering TimetSOLD10sec.Supply VoltageVCC-0.53.6VData Input VoltageVI-0.5VCCVDifferential Input Voltage (p-p)VD2.0VOutput CurrentIO50mAReferenceNote 1Recommended Operating ConditionsParameterSymbolMinimum TypicalMaximum UnitReferenceAmbient Operating Temperature AFBR-5903/5903EAFBR-5903ATATA0-40 70 85 C CNote ANote BSupply VoltageVCC3.1353.465VData Input Voltage - LowVIL - VCC-1.810-1.475VData Input Voltage - HighVIH - VCC-1.165-0.880VData and Signal Detect OutputLoadRL50WDifferential Input Voltage (p-p)VD0.800VNote 2Notes:A. Ambient Operating Temperature corresponds to transceiver case temperature of 0 C mininum to 85 C maximum with necessary airflowapplied. Recommended case temperature measurement point can be found in Figure 2.B. Ambient Operating Temperature corresponds to transceiver case temperature of -40 C mininum to 100 C maximum with necessary airflowapplied. Recommended case temperature measurement point can be found in Figure 2.12
Transmitter Electrical CharacteristicsAFBR-5903Z/5903EZ (TA 0 C to 70 C, VCC 3.135 V to 3.465 V)AFBR-5903AZ (TA -40 C to 85 C, VCC 3.135 V to 3.465 V)ParameterSymbolSupply mANote 3Power DissipationPDISS0.450.60WNote 5aData Input Current - LowIILData Input Current - HighIIH-350-218µA350µAReceiver Electrical CharacteristicsAFBR-5903Z/5903EZ (TA 0 C to 70 C, VCC 3.135 V to 3.465 V)AFBR-5903AZ (TA -40 C to 85 C, VCC 3.135 V to 3.465 V)ParameterSymbolSupply CurrentTypicalMaximum UnitReferenceICC65120mANote 4Power DissipationPDISS0.2250.415WNote 5bData Output Voltage - LowVOL - VCC-1.83-1.55VNote 6Data Output Voltage - HighVOH - VCC-1.085-0.88VNote 6Data Output Rise Timetr0.352.2nsNote 7Data Output Fall Timetf0.352.2nsNote 7Signal Detect Output Voltage - LowVOL - VCC-1.83-1.55VNote 6Signal Detect Output Voltage - HighVOH - VCC-1.085-0.88VNote 6Signal Detect Output Rise Timetr0.352.2nsNote 7Signal Detect Output Fall Timetf0.352.2nsNote 7Power Supply Noise RejectionPSNR13Minimum50mV
Transmitter Optical CharacteristicsAFBR-5903Z/5903EZ (TA 0 C to 70 C, VCC 3.135 V to 3.465 V)AFBR-5903AZ (TA -40 C to 85 C, VCC 3.135 V to 3.465 V)ParameterSymbolMinimumTypicalMaximum UnitReferenceOutput Optical Power BOL62.5/125 µm, NA 0.275 Fiber EOLPO-19-20-15.7-14dBm avgNote 11Output Optical Power BOL50/125 µm, NA 0.20 Fiber EOLPO-22.5-23.5-20.3-14dBm avgNote 1110-10%dBNote 12-45dBm avgNote 131380nmNote 14Figure 11nmNote 14Figure 11Optical Extinction RatioOutput Optical Power atLogic Low “0” StatePO (“0”)Center WavelengthlCSpectral Width - FWHM- RMSDlOptical Rise Timetr0.61.93.0nsNote 14/15Figure 11,12Optical Fall Timetf0.61.63.0nsNote 14/15Figure 11,12Duty Cycle Distortion Contributedby the TransmitterDCD0.160.6ns p-pNote 16Data Dependent Jitter Contributedby the TransmitterDDJ0.070.6ns p-pNote 17Random Jitter Contributedby the TransmitterRJ0.120.69ns p-pNote 181270130814763Receiver Optical and Electrical CharacteristicsAFBR-5903Z/5903EZ (TA 0 C to 70 C, VCC 3.135 V to 3.465 V)AFBR-5903AZ (TA -40 C to 85 C, VCC 3.135 V to 3.465 V)ParameterSymbolMaximum UnitReferenceInput Optical PowerMinimum at Window EdgePIN Min (W)Minimum Typical-33.5-31dBm avgNote 19Figure 13Input Optical PowerMinimum at Eye CenterPIN Min (C)-34.5-31.8dBm avgNote 20Figure 13Input Optical Power MaximumPIN Max-14dBm avgNote 19Operating Wavelengthl1270Duty Cycle Distortion Contributedby the ReceiverDCDData Dependent Jitter Contributedby the Receiver-11.81380nm0.090.4ns p-pNote 8DDJ0.21.0ns p-pNote 9Random Jitter Contributed by the ReceiverRJ0.112.14ns p-pNote 10Signal Detect - AssertedPAPD 1.5 dB-33dBm avgNote 21, 22Figure 14Signal Detect - DeassertedPD-45dBm avgNote 23, 24Figure 14Signal Detect - HysteresisPA - PD1.52.4dBFigure 14Signal Detect Assert Time(off to on)AS Max02100µsNote 21, 22Figure 14Signal Detect Deassert Time(on to off )ANS Max05350µsNote 23, 24Figure 1414
Notes:1. This is the maximum voltage that can be applied across the Differen tial Transmitter Data Inputs to prevent damage to the input ESDprotection circuit.2. The outputs are terminated with 50 Ω connected to VCC -2 V.3. The power supply current needed to operate the transmitter isprovided to differential ECL circuitry. This circuitry maintains a nearlycon stant current flow from the power supply. Constant currentoperation helps to prevent unwanted electrical noise from beinggenerated and conducted or emitted to neighboring circuitry.4. This value is measured with the out puts terminated into 50 Ω connected to VCC - 2 V and an Input Optical Power level of -14 dBmaverage.5a. The power dissipation of the transmitter is calculated as the sum ofthe products of supply voltage and current.5b. The power dissipation of the receiver is calcu lated as the sum ofthe products of supply voltage and currents, minus the sum of theproducts of the output voltages and currents.6. This value is measured with respect to VCC with the output terminatedinto 50Ω connected to VCC - 2 V.7. The output rise and fall times are measured between 20% and 80%levels with the output connected to VCC -2 V through 50 Ω.8. Duty Cycle Distortion contributed by the receiver is measured atthe 50% threshold using an IDLE Line State, 125 MBd (62.5 MHzsquare-wave), input signal. The input optical power level is -20 dBmaverage. See Appli cation Information - Transceiver Jitter Section forfurther information.9. Data Dependent Jitter contributed by the receiver is specified withthe FDDI DDJ test pattern described in the FDDI PMD Annex A.5.The input optical power level is -20 dBm average. See ApplicationInforma tion - Tra
Mb/s Multimode Fiber Interface are supported by Avago Technologies. Products are available for both the single-mode and the multimode fiberSONET OC-3c (STS-3c), SDH (STM-1) ATM interfaces and the 155 Mb/s-194 MBd multimode fiber ATM interface as specified in the ATM Forum UNI. Contact y
Ultra Short Link Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver Data Sheet Description The AFBR-732BWZ transmitter and AFBR-742BZ receiver are high performance fiber optic modules for parallel optical data communication applications. Thes
optics Tx3 Tx1 Tx0 O Array (4ch) Rx2 Rx3 Rx1 Rx0 Micro-optics MM ribbon Fiber cable. Avago Compatible AFBR-79EIPZ MPO, 850nm,MMF, 150m . Transmitter optical characteristics are measured with a single mode fiber. Avago Compatible AFBR-79EIPZ Optical Characteristics - Receiver Parameter S
These transceivers for 2-km multimode fiber backbones are supplied in the small 1 9 duplex SC or ST package style. The AFBR-5803AQZ/ATQZ is useful for both ATM 100-Mb/s interfaces and Fast Ethernet 100BASE-FX interfaces. The ATM Forum User-Network Interface (UNI) Standard, Version 3.0, defines the Phy
The Applications Engineering group in the Avago Tech-nologies Fiber Optics Communication Divis ion is available to as s is t you with the technical unders tanding and des ign trade-offs as s ociated with thes e trans ceivers . You can contact them through your
Twelve Channel, Parallel Fiber Optics Modules Data Sheet Description The AFBR-811VxyZ Twelve Channel, Pluggable, Parallel Fiber Optics Transmitter and AFBR-821VxyZ Twelve Channel, Pluggable, Parallel Fiber Optics Receiver are high performance ber optics modules for short-range parallel multi-
These transceivers for 2-km multimode fiber backbones are supplied in the small 1 9 duplex SC or ST package style. The AFBR-5803Z/5803TZ is useful for both ATM 100 Mb/s interfaces and Fast Ethernet 100BASE-FX interfaces. The ATM Forum User-Network Interface (UNI) Standard, Version 3.0, defines the Phy
Compliant to the InfiniBand Architecture Release 1.2.1 QDR Specification Compliant to the industry standard INF-8436i QSFP Transceiver Specification Revision 1.0 High Channel Capacity: up to 40 Gbps per module, bi-directional operation Operates up to 10 Gbps with 8b/10b compatible coded data Backwards compatible to 5Gbps DDR IB and 2.5 Gbps .
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