QorIQ T1024 Reference Design Board User Guide
QorIQ T1024 Reference Design BoardUser GuideDocument Number: T1024RDBUGRev. 0, 04/2015
QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/20152Freescale Semiconductor, Inc.
ContentsSection numberTitlePageChapter 1Overview1.1Related documentation.51.2Acronyms and abbreviations.61.3T1024RDB board features. 7Chapter 2Architecture2.1Processor. 92.2Power. 92.3Deep sleep control.122.4Reset.122.5Clocks. 132.6DDR. 142.7SerDes port.162.7.1PCI Express support.172.7.2XFI support. 172.7.3SGMII support. 182.8Ethernet controllers .182.9Ethernet Management Interface (EMI).192.10 I2C.202.11 SPI interface .212.12 IFC. 222.12.1 Virtual banks. 232.13 SDHC interface.232.14 USB interface.242.15 UART.252.16 TDM riser card interface.272.17 JTAG/COP port. 27QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.3
Section numberTitlePage2.18 Connectors, Headers, Jumper, Push buttons, and LEDs.282.18.1 Connectors. 292.18.2 Headers.292.18.3 Jumpers. 292.18.4 Push buttons. 302.18.5 LEDs. 302.19 Temperature. 302.20 DIP switch definition. 31Chapter 3CPLD Specification3.1CPLD Memory Map/Register Definition. 353.1.1Chip ID1 Register (CPLD CHIPID1). 363.1.2Chip ID2 Register (CPLD CHIPID2). 363.1.3Hardware Version Register (CPLD HWVER). 363.1.4Software Version Register (CPLD SWVER). 373.1.5Reset Control Register (CPLD RSTCON).373.1.6Reset Control Register (CPLD RSTCON2).383.1.7Interrupt Status Register (CPLD INTSR). 393.1.8Flash Control and Status Register (CPLD FLHCSR). 403.1.9Fan Control and Status Register (CPLD FANCSR). 403.1.10 Panel LED Control and Status Register (CPLD LEDCSR).413.1.11 SDHC Card Status Register (CPLD SDSR). 413.1.12 Miscellanies Control and Status Register (CPLD MISCCSR). 423.1.13 Boot Configuration Override Register (CPLD BOOTOR).423.1.14 Boot Configuration Register 1 (CPLD BOOTCFG1).433.1.15 Boot Configuration Register 2 (CPLD BOOTCFG2).43QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/20154Freescale Semiconductor, Inc.
Chapter 1OverviewThe T1024 Reference Design Board (T1024RDB) is a high-performance computingevaluation, development, and test platform supporting the QorIQ T1024 PowerArchitecture processor. The T1024RDB is optimized to support the high-bandwidthDDR3L memory and a full complement of high-speed SerDes ports.1.1 Related documentationThe table below lists and explains the additional documents that you can refer to, formore information about T1024RDB.Some of the documents listed below may be available only under a non-disclosureagreement (NDA). To request access to these documents, contact your local fieldapplications engineer or sales representative.Table 1-1. Useful referencesDocumentDescriptionQorIQ T1024, T1014 Data Sheet(T1024EC)Provides specific data regarding bus timing, signal behavior, and AC, DC, and thermalcharacteristics, as well as other design considerations.QorIQ T1024 Reference Manual(T1024RM)Provides a detailed description on T1024 QorIQ multicore processor, and on some ofits features, such as memory map, serial interfaces, power supply, chip features, andclock information. The T1024 QorIQ processor combines two 64-bit ISA PowerArchitecture processor cores with high-performance datapath acceleration logic andnetwork peripheral bus interfaces, required for networking and telecommunications.This chip can be used in applications, such as routers, switches, Internet accessdevices, firewall and other packet filtering processors, and general-purpose embeddedcomputing. Its high-level integration offers significant performance benefits and greatlyhelps to simplify board design.T1024 Product Brief (T1024PB)Provides an overview of the T1024 features and its usage examples.QorIQ T1024 Reference DesignBoard User Guide(T1024RDBPAUG)Describes the features and operation of T1024 performance reference platform, whichsupports QorIQ Power Architecture processors.Table continues on the next page.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.5
Acronyms and abbreviationsTable 1-1. Useful references (continued)DocumentDescriptionQorIQ Data Path AccelerationArchitecture (DPAA) ReferenceManual (DPAARM)Describes the core set of DPAA functionality implemented in many QorIQ chips, andidentifies those portions of the DPAA whose implementation varies from chip to chip.The QorIQ data path acceleration architecture (DPAA) provides the infrastructure tosupport simplified sharing of networking interfaces and accelerators by multiple CPUcores. These resources are abstracted into enqueue/dequeue operations by means ofa common DPAA Queue Manager (QMan) driver.1.2 Acronyms and abbreviationsThe table below lists and explains the acronyms and abbreviations used in this document.Table 1-2. Acronyms and abbreviationsUsageDescriptionCOPCommon On-chip ProcessorCPCCoreNet Platform CacheCPLDComplex Programmable Logic DeviceDIMMDual In-Line Memory ModuleDIPDual In-Line PackageDIUDisplay Interface UnitDMADirect Memory AccessDPAAData Path Acceleration ArchitectureDRAMDynamic Random Access MemoryDUTDevice Under TestECEthernet ControllersEDCError Detection and CorrectionEEPROMElectrically Erasable Programmable Read-Only MemoryEMIEthernet Management InterfaceseMMCembedded MultiMediaCardeSDHCenhanced Secure Digital Host ControllereSPIenhanced Serial Peripheral InterfaceFETField Effect TransistorHDLCHigh-level Data Link ControlI2CInter-Integrated CircuitIFCIntegrated Flash ControllerJTAGJoint Test Action GroupMPICMulticore Programmable Interrupt ControllerPCIe/PEXPCI ExpressPLDProgrammable Logic DevicePORPower On ResetTable continues on the next page.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/20156Freescale Semiconductor, Inc.
Chapter 1 OverviewTable 1-2. Acronyms and abbreviations (continued)UsageDescriptionSATASerial Advanced Technology AttachmentSDSecure DigitalSDRAMSynchronous Dynamic Random-Access MemorySDHCSecure Digital High CapacitySerDesSerializer/DeserializerSGMIISerial Gigabit Media Independent InterfaceSPISerial Peripheral InterfaceSYSCLKSystem ClockTDMTime-Division MultiplexingUARTUniversal Asynchronous Receiver/TransmitterVCCVoltage for CircuitVTTVoltage for Terminal1.3 T1024RDB board featuresThe T1024RDB board features are as follows: SerDes connections XFI PCI Express x1: supports Gen 1 and Gen 2 Two mini PCI Express x1 SGMII 2.5G DDR controller Data rates of up to 1600 MHz are supported One DDR3L DIMM of single, dual, or quad-rank types is supported 1.35 V DDR power supply to all devices with automatic tracking of VTT IFC NAND flash: 8-bit, asynchronous, up to 1 GB NOR flash: 16-bit, non-multiplexed, up to 128 MB; NOR devices support 8virtual banks Ethernet Two on-board RGMII 10/100/1G Ethernet ports; PHY #0 remains powered upduring deep sleep One on-board XFI 10G EDC for 10GBase-T port One on-board SGMII 2.5G Ethernet portQorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.7
T1024RDB board featuresNOTEDue to RCW limitations, SGMII 2.5G Ethernet port cannotwork with XFI 10GBase-T port and MAC3 RGMIIethernet port in the same mode. CPLD Manages system power and reset sequencing Configures DUT, board, and clock with dynamic shmoo Reset and interrupt monitor and control General fault monitoring and logging Sleep mode control Clocks System and DDR clock or single differential clock SerDes clocks: : Clocks are provided to all SerDes blocks and slots. Supportedclock frequencies are: 100 MHz 125 MHz 156.25 MHz USB Supports two USB 2.0 ports with integrated PHYs SDHC SDHC port connects directly to an adapter card slot SPI On-board support of two different devices Other IO Two serial ports with RJ45 interface Two I2C portsNOTEFor details on T1024 silicon features and block diagram, seeQorIQ T1024 Reference Manual.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/20158Freescale Semiconductor, Inc.
Chapter 2ArchitectureThis chapter explains the architecture of T1024RDB: ProcessorPowerResetClocksDDRSerDes portEthernet controllersEthernet Management Interface (EMI)I2CSPI interfaceIFCSDHC interfaceUSB interfaceUARTJTAG/COP portConnectors, Headers, Jumper, Push buttons, and LEDsTemperatureDIP switch definition2.1 ProcessorThe T1024RDB supports many features of the T1024 processor, as detailed in thefollowing sections. The boards and supporting hardware are all identical, but the abilityto use various features depends on the device installed.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.9
Power2.2 PowerThe power supply system of the T1024RDB systems uses power from a standard ATXPSU to provide power to the numerous processor, CPLD, and peripheral devices. Tomeet the required power specifications, the following goals guide the power supplyarchitecture: Monolithic power supply for VCC (powering internal cores and platform logic). DUT-specific power rails are instrumented for current measurement. Automatic collection of voltage, current, and power is performed for critical supplies. Mounting holes of sufficient size are provided, to allow on-board supplies to bereplaced by bench supplies. All power supplies can be sequenced as per hardware specifications.The following table indicates the total power consumption of the T1024RDB.The following figure shows the power supply architecture.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201510Freescale Semiconductor, Inc.
Chapter 2 ArchitectureATX PS12V SLPVCORE SLP (8A)IR34755V0 SLP5.1ohm1V8 SLP5.1ohm1V35VCOREIOPWR EN5V0 SLPIR34755V0 SLP1V35 SLPIR34733V3 SLP(9A)(Always On)IOPWR EN3V32V5 SLP(2A)(Always On)IOPWR EN2V5VTT1V8 SLP5V0 SLPIOPWR EN5V0 SLP1V2 (3A)(Switchable)IR3473IOPWR EN5V0 SLP2V1 (3A)(Switchable)EVDDIR3473IOPWR ENCPLD0V85 (3A)(Switchable)IR3473IOPWR EN3V31V8VDD SD1V35 SLP3V3VTTMREF SLP3V3IOPWR EN1V866.67M OSCDDR refclk1V8 SLP24M OSCUSB refclk1V8 SLP3V3 SLPBEAT XVDDVCORE1V8 SLP3V3VDDVDD SPDDDR3 DIMMVTTVREFCA(DQ)VCCNOR FLASHJS28F00AM29EWHAVCCSPI FLASHMT25Q512ABA1ESF5V0 SLP3V3USB OVDD[1:2]1V35VCC/VCCQNAND FLASHMT29F8G08ABBAWPVDD SD3V3 SLPDS1339(RTC)1V22V10V852V5AT24C256(I2C EEPROM)3V33V3 SLPUSB HVDD[1:2]1V0SVIO100M OSCSys refclkIDT9FGV0641(CLK Buffer)USB SVDD[1:2]BEATSVDD1V812V1V8 SLPBEAT1V83V31V8 SLP1V8VCORE ENVDD ENIOPWR ENDDRPWR ENEVDD SEL1V8EVDD EN12V SLPBEAT1V8(Switchable)5V0 SLP3V3S1VDD[1:7]X1VDD[1:4]T10241V5 (1.5A)IR3473AVDD CGA1AVDD CGA2BEAT1V8 SLPDDRPWR EN1V0SMIC47100VDD ENAVDD PLATO1VDD[1:3]MVREFMVREF SLPTPS51200AVDD D15.1ohm1V81V8 SLP(1.5A)(Always On)AVDD SD1 PLL25.1ohm1V81V35 SLP(4A)(Always On)DDRPWR ENIR34731V8VCORE(Switchable)VDD ENIR34755V0 SLPAVDD SD1 PLL10.33ohm5V0 SLPVCORE EN0.33ohm1V355V0 SLPVDD SD CardINUSB: V33V32V52V5 SLP1V35VCOREVCORE SLP3V33V33V3 SLP2V5 SLP3V32V5OVDD[1:6]D1 MVREFTH VDDFA VLPROG MTRPROG 9]VDD[1:31]VDDC[1:12]VDD MAX3232*2VDD RTL8211E-VBU36DVDD(15/21)3V312VTDM Riser Card3V312VPCIEX1 SLOT1V53V3MINI PCIE SLOT*212VFAN Conn *4ADT7461(Thermal sensor)Figure 2-1. Power supplyQorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.11
Deep sleep controlNOTE1. Set RGMII limits to LVDD 2.5 V.2. Supply PROG SFP/PROG MTR with 1.8 V only duringthe secure boot fuse programming.2.3 Deep sleep controlThe T1024 processor has the ability to enter into the deep-sleep mode. Once theprocessor has readied itself for the deep-sleep mode, setting the CPLD registerPWR CTL[SLP] 1 causes the power sequencer to begin an orderly shutdown of severalpower supplies, while others remain active.Once ready, PWR MSTAT[STATE] will indicate the system is asleep. However, theprocessor is already in the idle state, so this may not be needed by the system software.Perform the following steps to send the T1024 processor to the deep-sleep mode: Prepare the CPLD to ignore the external signals. For example, some interrupt pinswill power down, so the CPLD masks these pins from presenting valid interrupts. Prepare the DDR subsystem for self-refresh by forcing RST MEM B high, forcingthe CKE# “clamp” FETs low. Gate the secondary powers to the DUT. Any power supply marked as “sleeps” in thepower section diagrams are enable-disable, or can be gated.Once the above steps are completed, the system enters into the deep-sleep mode. Thesystem software has the timers or interrupt controllers programmed such that importantevents can wake the processor (which will be powered only by VDDC) and can decide ifsituations warrant returning to sleep, or activating full power.2.4 ResetThe CPLD manages the reset signals to and from the T1024 processor and other deviceson the T1024RDB. The following figure shows an overview of the reset architecture.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201512Freescale Semiconductor, Inc.
Chapter 2 ArchitectureCPLDATX PSPWR GODDMIC811(Power-on RST)GNDPWR RST NPush-ButtonCOP SRST NCOP ITF COP HRST NHESET REQ NSoft reset registerSW RST RSTCON1 & RSTCON27 6 5 4 3 2 1 0EC1 RST NRGMIIGE PHY1EC2 RST NRGMIIGE PHY2XGT2 RST N 10GBASE-TPHY(AQR105)XGT1 RST N 10GBASE-TPHY(AQR105)TDMR RST N TDM RiserSLOTResetSourceselectRST CTLPEX RSTPEX SLOTHRSET NMPEX1 RST MINI PEXSLOTPORESET NMPEX2 RST MINI PEXSLOTT1024NOR RSTNNORFLASHDDR RSTNDDR3/DDR3LFigure 2-2. Reset architecture2.5 ClocksThe clock circuitry provides the following clocks for the processor: SYSCLK DDRCLK (single-ended and differential) SerDes clocks Ethernet clocks USB clockThe architecture of the clock section is shown in the following figure.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.13
DDRSYSCLK (100MHz)OSC-100MHzOSC-66.66MHzDDRCLK (100MHz)USB REFCLK (24MHz)OSC-24MHzT1024SD REFCLK1 P/N(156.25MHz or 125 MHz)IDT9FGV064125MHzSYS REFCLK P/N(100M)SD REFCLK1 P/N(100M)PEX REFCLK P/N(100M)DIFSYSCLK OE(CPLD)IDT9FGV0641MPEX1 REFCLK P/N(100M)PEXCLK OE(CPLD)MPEX2 REFCLK P/N(100M)PEXSLOT25MHzMINIPEXSLOTMINIPEXSLOTFigure 2-3. Clock architecture2.6 DDRThe T1024RDB supports high-speed DRAM, with an unbuffered DDR3 (240-pin) socket(UDIMM) that features single-, dual-, and quad-rank support. The memory interfaceincludes all the necessary termination and I/O power, and it is routed to achievemaximum performance by the memory bus, as shown in the following figure.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201514Freescale Semiconductor, Inc.
Chapter 2 ArchitectureDIMMDDR DQ[0:63]DDR ECC[0:7]DDR MA[0:15]DDR MDQS[0:8]DDR MDM[0:8]DDR MBA[0:2]DDR MDOT[0:1],DDR MAPAR OUT,DDR MPAR ERRDDR: DIMM SOCKET 240PINDDR MCS[0:3]DDR MCK P[0:1] P/NT1024DDR CAS,DDR RAS,DDR WEDDR MCKE[0:1]1V35 SLPCKE ISO EN(CPLD)1V35 SLPD1 MDIC1D1 MDIC0DDR RST N(CPLD)For T1040:R-162OhmFor T2081:R-187OhmI2C1 SCL,I2C1 SDA(SPD ADDR 0X51)MV REFIR3475TPS51200VTT1V35 SLPFigure 2-4. Memory interfaceQorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.15
SerDes portAlthough the platforms support all types, ranks, and speeds of DIMMs, but not all thecombinations of these three exist in the memory market. Hence, the system is shippedwith a “representative” DIMM, as noted in the below table. Other suitable memoryDIMMs can be purchased and installed if needed. However, Freescale only supplies thedevice shown in the below table.Table 2-1. Freescale supported DIMMPlatformTypeT1024RDBSpeedsDDR3LRanks1600 MT/sDIMMDualMicron MT18KSF51272AZ-1G6K14GB, x72, CL 102.7 SerDes portThe T1024 SerDes block provides a four high-speed serial communication lanes,supporting a variety of protocols, including: XFI 1X 10.3125G bit/s PCI Express (PEX) Gen 1 1X 2.5 Gbit/s PCI Express (PEX) Gen 2 1X 5 Gbit/s SGMII 2.5G bit/sAn overview of the SerDes protocols supported on the T1024RDB is shown in Table 2-2.Table 2-2. SerDes protocolsSRDS PRTCL S1ABCDEC1EC2Per lane PLL mapping0X095XFI1(MAC1) PEXc x1PEXb x1PEXa x1RGMII(MAC4)RGMII(MAC3)12220X135AuroraPEXb x1PEXa x1RGMII(MAC4)N/A12112.5SGMII(MAC3)To comply with the T1024 application, some multiplexers are used to re-route and groupthe SerDes lanes as shown in the below figure.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201516Freescale Semiconductor, Inc.
Chapter 2 ArchitectureXFI RX/TX[0] P/N(AQR105)AQR105SD1 RX/TX[0:3] P/N(PEX[0:3])PCIe SLOTT1024SGMIISD1 RX/TX[4] P/N(MPEX[1])SD1 RX/TX[5] P/N(MPEX[2])Mini PCIeSLOTMini PCIeSLOTFigure 2-5. SerDes distribution of T1024RDB2.7.1 PCI Express supportThe T1024 processor supports evaluation of PCI Express using any standard PCI ExpressGen 1 or Gen 2.2.7.2 XFI supportThe T1024 processor only supports the evaluation of the XFI protocol using AquantiaAQR105 single port 10GBase-T PHY. 10G data is carried over the XFI interface. Thebelow figure shows the connectivity of the XFI interface.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.17
Ethernet controllersT1024XFIXFIEMI2AQR10510G Base-TPHYMDIMagneticsRJ46Figure 2-6. XFI interface2.7.3 SGMII supportThe T1024 processor supports evaluation of the 2.5G SGMII protocol for serializedEthernet PHYs using Aquantia AQR105 PHY. Ethernet data is carried over the SGMIIinterface.The below figure shows the connectivity of the SGMII /MDCRJ-46 PortFigure 2-7. SGMII interface2.8 Ethernet controllersThe T1024 processor supports two Ethernet Controllers (EC), which can connect toEthernet PHYs using MII or RGMII protocols. On the T1024RDB, the EC1 and EC2ports only operate in the RGMII mode. Both ports are connected to Realtek RTL8211PHYs. The T1024RDB supports Energy Efficient Ethernet (EEE) on EC1 and sleepmode on EC2.The below figure shows the connectivity of the EC1/EC2 interface.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201518Freescale Semiconductor, Inc.
ETH, Cntr. 1Chapter 2 ArchitectureRGMIIRGMIIRTL8211E VBTransformerMDIO/MDCEMI1(MAC4)RJ-45 PortETH, Cntr. 2T1024RGMIIRGMIIRTL8211E VBTransformerMDIO/MDCEMI1(MAC3)RJ-45 PortFigure 2-8. EC1/EC2 interface connectivity2.9 Ethernet Management Interface (EMI)The T1024 processor has two Ethernet Management Interfaces (EMI), EMI1 and EMI2.EMI2 is only used with 10G Base-T PHY and 2.5G SGMII PHY, which uses 1.2 V pullup. EMI1 is used with RGMII PHYs. There are two working modes in the T1024RDBPC. The following tables represents the configurations for 10GBase-T and 2.5G SGMIIworking modes:Workingmode10GBase-TImage inFlashBank 0(Default)2.5G SGMII Bank4WorkingmodeSW3 [1:8]SerDesProtocalOn 0ETH0ETH1ETH2ETH3PCIe erDesProtocalLane ALane BLane CLane DEC1EC210GBase-T0x95XFI (MAC1)PEXcPEXbPEXaMAC4MAC32.5G SGMII0x135AuroraSGMII(MAC3)PEXbPEXaMAC4N/AThe below figure shows the EMI hardware block diagram.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.19
I2C2V5 SLPEMI1 MDC SLPEMI1 MDCEMI1 MDIO SLPEMI1 MDIORTL8211E-VL(RGMII PHY)PHY ADDR 0X02(MAC4)2V574LVC1G66*2OERTL8211E-VL(RGMII PHY)T1024IV2EMI2 MDCEMI2 MDIOEMI2 MDCEMI2 MDIOAQR105(10G BASE-T PHY)AQR105(2.5G SGMII PHY)PHY ADDR 0X06(MAC3)PHY ADDR 0X01(MAC1)PHY ADDR 0X02(MAC3)Figure 2-9. EMI hardware block2.10 I2CThe T1024 devices supports up to four I2C buses, to make the I2C resources equallyavailable to both local and remote systems. The T1024RDB uses I2C1 port to access onboard devices, such as DDR3 DIMM, thermal sensor (ADT7461), EEPROM, RTC, andclock PLL. The I2C2 bus uses multiplexers to partition the I2C bus into several channels.Two mini PCIe slots use channels 0 and 1, and the PCIe slot uses channel 3.The following figure shows the I2C subsystem.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201520Freescale Semiconductor, Inc.
Chapter 2 Architecture3V3I2C1 SCLI2C1I2C1 SDAAT24C256I2C ADDR-0X50FET Isolation(IRLML6346)3V3 SLPI2C1 SCL SLPI2C1 SDA SLPT1024DDR3 DIMMI2C ADDR-0X51ADT7461(Thermal Sensor)I2C ADDR 0X4CDS1339URTCI2C ADDR 0X68IDT9FGV06413V3I2C1 SCLI2C2I2C1 SDAI2C ADDR 0X6AChannel 0I2C2 MPEX1 SCLI2C2 MPEX1 SDAMini PCIe SLOTChannel 1I2C2 MPEX2 SCLI2C2 MPEX2 SDAMini PCIe SLOTI2C2 PEX SCLI2C2 PEX SDAPCIe SLOTPCA9546Channel 2Channel 3I2C ADDR 0X77Figure 2-10. I2C subsystem2.11 SPI interfaceThe T1024 Serial Peripheral Interface (SPI) pins are used for the following purposes:QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.21
IFC On-board SPI device accessing various SPI memory devices Off-board TDM riser card plug-in on J43 slotSPI CS0 is used to access a SPI memory device, with the remaining chip selects used toselect additional on-board SPI devices, and a TDM device present on the TDM riser card.The below figure shows the overall connections of the SPI portion.SPISPI MOSI/MISO CLKSPI CS0MT25QL512(64MB FLASH)T1024TDMR SPI CS0/CS1TDM Riser card connectorFigure 2-11. SPI interface2.12 IFCThe T1024 Integrated Flash Controller (IFC) supports 32-bit addressing and 8- or 16-bitdata widths for a variety of devices to effectively manage all the resources withmaximum performance and flexibility. The below figure shows an overview of the IFCbus.ADDR,DATA,ControlNAND Flash(MT29F8G08ABABAWP)(1.8 V)T1024CPLDNAND CSXORsNOR CSCfg vbank[0:2]IFC A5-A7IFC VA5-A7NOR Flash(JS28F00AM29EWHA)Figure 2-12. IFC busQorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/201522Freescale Semiconductor, Inc.
Chapter 2 Architecture2.12.1 Virtual banksThe virtual bank feature is available when the NOR flash is connected to IFC CS0 N. Inthat case, the value of VBANK[0:2] will be driven into three XOR gates, which togglethe MSB's of the NOR address, as shown in the below figure.DUTNOR flashLATCHB IFCIFC A[30:8]A[0:22]IFC A[7:5]A[23:25]cfg vbank[0:2]Figure 2-13. Virtual bank interfaceWhen VBANK[0:2] 000, the IFC A[7:5] is not altered, and the NOR flash behavesnormally. If VBANK[0:2] 100, the LB A[5] is toggled and effectively swaps the topand bottom halves of the NOR flash. If program "A" was stored in the bottom half andprogram "B" in the top half then, while selecting different VBANK settings, “A” and “B”will get their VBANKs changed as given in the below table.Table 2-3. Virtual bank settingsNOR zonesVBANK(1/8 of BANOTEIn the above table, the NOR flash has been partitioned intoeight 16 MB zones, which can be arranged under the control ofVBANK.QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015Freescale Semiconductor, Inc.23
USB interface2.13 SDHC interfaceThe enhanced SD Host Controller (eSDHC) provides an interface between host systemand SD/MMC cards. The Secure Digital (SD) card is specifically designed to meet thesecurity, capacity, performance, and environmental requirements, inherent in emergingaudio and video consumer electronic devices. Booting from eSDHC interface issupported using the processor’s on-chip ROM.On the T1024RDB, a single connector is used for both SD and MMC memory cards, asshown in the below figure.1.8 V or 3.3 V3.3 VClampingDiodesT1024SD WPWPSD CDCDSDHC CLKCLKCMDCMDSD CardDAT[0:3]DAT[0:3]Figure 2-14. SDHC interface2.14 USB interfaceThe T1024RDB systems have two integrated USB 2.0 controllers (USB1 and USB2), thatallow direct connection to USB ports with appropriate protectio
DDR_refclk 100M OSC Sys_refclk IR3473 IR3473 IR3473 5V0_SLP 1V8 1V8_SLP IOPWR_EN (Always_On) 3V3_SLP(9A) IOPWR_EN (Always_On) 1V8_SLP(1.5A) DDRPWR_EN (Always_On) 1V35_SLP(4A) VDD_EN (Switchable) DDRPWR_EN VDD VDD_SPD VTT VREFCA(DQ) DDR3 DIMM J10 J9 Figure 2-1. Pow
Boot (Firmware Authenticity Verification), Run Time Integrity Check, Data Security Kit (E) (HDD Overwrite Mode and HDD Data Encryption), Common Criteria (ISO15408 EAL2), IEEE 2600.2 Print Specifications Standard Controller: Freescale QorIQ T1024 (Dual Core) / 1.2GHz; Freescale QorIQ T1024 (Dual Core) / 1.0GHz for the 3253ci & 2553ci
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