LECTURE 32 IMPROVED OPEN-LOOP COMPARATORS AND
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-1LECTURE 32 – IMPROVED OPEN-LOOP COMPARATORS ANDLATCHESLECTURE ORGANIZATIONOutline Autozeroing Hysteresis Simple Latches SummaryCMOS Analog Circuit Design, 3rd Edition ReferencePages 469-488CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-2AUTOZEROINGPrinciple of AutozeroingUse the comparator as an op amp to sample the dc input offset voltage and cancel theoffset during operation.Comments: The comparator must be stable in the unity-gain mode (self-compensating comparatorsare ideal, the two-stage comparator would require compensation to be switched induring the autozero cycle.) Complete offset cancellation is limited by charge injectionCMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-3Differential Implementation of Autozeroed ComparatorsCMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-4Single-Ended Autozeroed ComparatorsNoninverting:Inverting:Comment on autozeroing:Need to be careful about noise that gets sampled onto the autozeroing capacitor andis present on the comparison phase of the process.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-5HYSTERESISInfluence of Input Noise on the ComparatorComparator without hysteresis:Comparator with VTRP voutVOHtVOLtFig. 8.4-6A VOLFig. 8.4-6BVoltage Regulator with input voltage having too large of source resistance, RS: RS VIN-EnableVoltageRegulatorVONCLRL150604-01CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-6Use of Hysteresis for Comparators in a Noisy EnvironmentTransfer curve of a comparator with hysteresis:vOUTvOUTVOHVTRP vINVTRP-VOLCounterclockwise BistableVOHR1(V -V )R2 OH OL00VTRP-VTRP vINVOLClockwise BistableFig. 8.4-5Hysteresis is achieved by the use of positive feedback Externally InternallyCMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-7Noninverting Comparator using External Positive FeedbackCircuit:Upper Trip Point:Assume that vOUT VOL, the upper trip point occurs when,R1 R1 R2 VOL VTRP0 VTRP - VOLR2 R1 R2 R1 R2 Lower Trip Point:Assume that vOUT VOH, the lower trip point occurs when,R1 R1 R2 0 R R VOH R R VTRP VTRP - R VOH 1 2 1 2 2Width of the bistable characteristic: R1 Vin VTRP -VTRP VOH -VOL R2 CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-8Inverting Comparator using External Positive FeedbackCircuit:Upper Trip Point:vIN VTRP R1 R R VOH 1 2 Lower Trip Point:vIN VTRP- R1 R R VOL 1 2 Width of the bistable characteristic: R1 VOH -VOL R1 R2 Vin VTRP -VTRP- CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-9Horizontal Shifting of the CCW Bistable CharacteristicCircuit:Upper Trip Point:VREF R1 R2 R R VOL R R VTRP 1 2 1 2 VTRP R1 R1 R2 R VREF - R VOL 2 2Lower Trip Point:VREF R1 R2 VTRP VOH R RR R 1 2 1 2 VTRP-R1 R1 R2 VREF - VOHR2 R2 Shifting Factor: R1 R2 R VREF2 CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-10Horizontal Shifting of the CW Bistable CharacteristicCircuit:Upper Trip Point:vIN VTRP R1 R2 R R VOH R R VREF 1 2 1 2 Lower Trip Point:vIN VTRP- R1 R2 VREF VOL R RR R 1 2 1 2 Shifting Factor: R2 R R VREF 1 2 CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-11Example 32-1 Design of an Inverting Comparator with HysteresisUse the inverting bistable to design a high-gain, open-loop comparator having anupper trip point of 1V and a lower trip point of 0V if VOH 2V and VOL -2V.SolutionPutting the values of this example into the above relationships gives R1 R2 2 VREF1 R RR R 1 2 1 2 and R1 R2 0 R R (-2) R R VREF 1 2 1 2 Solving these two equations gives 3R1 R2 and VREF (2/3)V.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-12Hysteresis using Internal Positive FeedbackSimple comparator with internal positive feedback:VDDM3IBiasM6M4M7vo1vi1M8vo2M2M1M5VSSCMOS Analog Circuit Designvi2Fig. 8.4-11 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-13Internal Positive Feedback - Upper Trip PointVDDAssume that the gate of M1 is on ground and theinput to M2 is much smaller than zero. Theresulting circuit is:M3 M6M7 M4vo1vo2M1 on, M2 off M3 on, M6 on (active), M4and M7 off. vo2 is high.M2M1i1 i3i 2 i6W6/L6vinM6 wants to source the current i6 W /L i1M53 3I5As vin begins to increase towards the trip point, theFig. 8.4-12Acurrent flow through M2 increases. When i2 i6,VSSthe upper trip point will occur.W6/L6 I5 W6/L6 i3 i3 1 i1 i3 I5 i1 i2 i3 i6 i3 W/LW/L1 [(W6/L6)/(W3/L3)]3 3 3 3 Also, i2 I5 - i1 I5 - i3Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives2i22i1 VTRP vGS2 - vGS1 VT2 - VT1 2CMOS Analog Circuit Design 1 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-14Internal Positive Feedback - Lower Trip PointAssume that the gate of M1 is on ground and the inputto M2 is much greater than zero. The resulting circuitis:M2 on, M1 off M4 and M7 on, M3 and M6 off. vo1 is high.W7/L7M7 wants to source the current i7 W /L i24 4VDDvo1vi1M3 M6M1M7 M4M2vo2vi1i2 i4i1 i7vinI5M5VSSFig. 8.4-12BAs vin begins to decrease towards the trip point, thecurrent flow through M1 increases. When i1 i7, the lower trip point will occur.W7/L7 i5 W7/L7 i4 i4 i4 1 i2 i4 i5 i1 i2 i7 i4 W/LW/L1 [(W7/L7)/(W4/L4)]4444 Also, i1 i5 - i2 i5 - i4Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives2i22i1VTRP vGS2 - vGS1 VT2 - VT12CMOS Analog Circuit Design1 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-15Example 32-2 - Calculation of Trip Voltages for a Comparator with HysteresisConsider the circuit shown. If KN’ 110µA/V2,VDDKP’ 50µA/V2, and VTN VTP 0.7V,M4M3M6 M7IBiascalculate the positive and negative thresholdvo1vo2points if the device lengths are all 1 m and thewidths are given as: W1 W2 W6 W7 10 mvi2vi1M2and W3 W4 2 m. The gate of M1 is tied toM1ground and the input is the gate of M2. Thecurrent, i5 20 AM8M5SolutionFig. 8.4-11VSSTo calculate the positive trip point, assumethat the input has been negative and is heading positive.i5(W/L)620 Ai6 (W/L) i3 (5/1)(i3) i3 1 [(W/L) /(W/L) ] i1 1 5 3.33 A363 2·3.33 1/2 2i1 1/2i2 i5 i1 20 3.33 16.67 A vGS1 VT1 (5)110 0.7 0.81V 1 2·16.67 1/2 2i2 1/2 vGS2 VT2 0.7 0.946V (5)110 2 VTRP vGS2 vGS1 0.946 0.810 0.136VCMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-16Example 32-2 - ContinuedDetermining the negative trip point, similar analysis yieldsi4 3.33 Ai1 16.67 AvGS2 0.81VvGS1 0.946VVTRP- vGS2 vGS1 0.81 0.946 0.136VPSPICE simulation results of this circuit are shown below.2.6Remember the simpleSAH model does not doa good job of modelingthe knee or S Analog Circuit Design1-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2vin (volts)0.3 0.4 0.5Fig. 8.4-13 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-17Complete Comparator with Internal 112.6M52.4VSSFig. 8.4-142.22vout1.8(volts)1.61.41.21-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2vin (volts)CMOS Analog Circuit Design0.3 0.4 0.5120524-03 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-18Schmitt TriggerThe Schmitt trigger is a circuit that has better defined switching points.Consider the following circuit:How does this circuit work?VDDAssume the input voltage, vin, is low and the output voltage,M5vout , is high.M4M3vinM2voutM6M1120524-04M3, M4 and M5 are on and M1, M2 and M6 are off.When vin is increased from zero, M2 starts to turn on causing M3to start turning off. Positive feedback causes M2 to turn onfurther and eventually both M1 and M2 are on and the output is atzero.The upper switching point, VTRP is found as follows:When vin is low, the voltage at the source of M2 (M3) isvS2 VDD-VTN3VTRP vin when M2 turns on given as VTRP VTN2 vS2VTRP occurs when the input voltage causes the currents in M3 and M1 to be equal.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-19Schmitt Trigger – ContinuedThus,iD1 ( VTRP - VTN1)2 ( VDD - vS2- VTN3) 2 iD3which can be written as, assuming that VTN2 VTN3, ( VTRP - VTN1)2 ( VDD – VTRP )2 VTN1 3/ 1 VDDVTRP 1 3/ 1The switching point, VTRP- is found in a similar manner and is: ( VDD - VTRP- - VTP5)2 ( VTRP-)2 The bistable characteristic is,VTRP- 5/ 6(VDD- VTP5)1 5/ 6voutVDD0 0VTRP-VTRP VDDvinFig. 8.4-16CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-20SIMPLE LATCHESRegenerative ComparatorsRegenerative comparators use positive feedback to accomplish the comparison of twosignals. Latches can have a faster switching speed than the previous comparators.NMOS and PMOS latch:VDDI1I2vo1M2NMOS latchM2M1vo2M1CMOS Analog Circuit DesignVDDvo1I1vo2I2PMOS latchFig. 8.5-3 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-21Operating Modes of the LatchThe latch has two modes of operation – enable or latch and Enable (enable bar) orLatch (latch bar).1.) During the Enable bar, the latch is turned off (currents are removed) and theunknown inputs are applied to it. The parasitic capacitance at the latch nodes hold theunknown voltage.2.) During Enable, the latch is turned on, and the positive feedback acts on the appliedinputs and causes one side of the latch to go high and the other side to go low.Enable bar:VDDVo1ʼI1EnableVDDI2Vo2ʼ Vo1ʼM2M1NMOS latchM2M1EnableEnableEnableVo2ʼI1I2PMOS latch060808-09The inputs are initially applied to the outputs of the latch.Vo1’ initial input applied to vo1CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Step Response of a Latch (Enable)VDDVDDCircuit:Ri and Ci are theI1I2 C1vo2resistance and capacitanceVo1vo1Vo2seen to ground from theVo1'M1M2gm1Vo2 R1 sgm2Vo1i-th transistor.Nodal equations:Vo1’ gm1Vo2 G1Vo1 sC1 Vo1- s gm1Vo2 G1Vo1 sC1V o1-C1Vo1’ 0 Vo2’ gm2Vo1 G2Vo2 sC2 Vo2- s gm2Vo1 G2Vo2 sC2V o2-C2Vo2’ 0 Solving for Vo1 and Vo2 gives,R1C1gm1R1 1gm1R1Vo1 sR C 1 Vo1’ - sR C 1 Vo2 Vo1’ Vo2s 1s 11 11 111R2C2gm2R2 2gm2R2Vo2 sR C 1 Vo2’ - sR C 1 Vo1 V ’Vs 2 1 o2 s 2 1 o12 22 2Defining the output, Vo, and input, Vi, as Vo Vo2-Vo1 and Vi Vo2’-Vo1’CMOS Analog Circuit DesignPage 32-22C2Vo2'R2 s Vo2Fig. 8.5-4 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-23Step Response of the Latch - ContinuedSolving for Vo gives,or Vi Vo Vo2-Vo1 gmR Vi V os 1s 1 V i1-gmR ’ Vi V o s (1-gmR)s s ’ 1 11-gmRwhere ’ 1-g RmTaking the inverse Laplace transform gives vo(t) Vi e-t/ ’ Vi e-t(1-gmR) / egmRt/ Vi,Define the latch time constant as0.67WLCox C L ’ g R g 0.67Cox2K’(W/L)Immif C Cgs. Vout(t) et/ L ViCMOS Analog Circuit Designif gmR 1.WL32K’I P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-24Step Response of a Latch - ContinuedNormalize the output voltage by (VOH-VOL) to get Vout(t)VOH-VOL et/ L V iVOH-VOLwhich is plotted as, VOH- VOL The propagation delay time is tp L ln 2 V i Note that the larger the Vi, the faster the response.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-25Example 32-3 - Time Domain Characteristics of a Latch.Find the propagation time delay for the NMOS if the W/L of the latch transistors is5µm/0.5µm and the latch dc current is 10µA when Vi 0.1(VOH-VOL) and Vi 0.01(VOH-VOL).SolutionThe transconductance of the latch transistors isgm 2·120·10·10 155µSThe output conductance is 0.6µS which gives gmR of 93V/V. Since gmR is greater than1, we can use the above results. Therefore the latch time constant is found as L 0.67CoxWL3-4) 0.67(60.6x102K’I(5·0.5)x10-24 0.131ns2·120x10-6·10x10-6Since the propagation time delay is the time when the output is 0.5(VOH-VOL), thenusing the above results or Fig. 8.5-5 we find for Vi 0.01(VOH-VOL) that tp 3.91 L 0.512ns and for Vi 0.1(VOH-VOL) that tp 1.61 L 0.211ns.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-26Comparator using a Latch with a Built-In Reference†How does it operate?1.) Devices in shaded region operate in the triode region.2.) When the latch/reset goes high, the upper cross-coupled inverter-latch regenerates.The drain currents of M5 and M6 are steered to obtain a final state determined by themismatch between the R1 and R2 resistances.W2 W1 1 R1 KN L (vin - VT) L (VREF - VT) andW2 W1 1 R2 KN L (vin - VT) L (VREF - VT) 3.) The input voltage which causes R1 R2 isvin(threshold) (W2/W1)VREFW2/W1 1/4 generates a threshold of 0.25VREF.Performance †20Ms/s & 200µWT.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March1995.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-27Simple, Low Power Latched Comparator†Dissipated 50µW when clocked at 2MHz.Self-referenced†A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Tail-Referenced LatchThe previous two latches experience poor input offsetvoltage characteristics because the input devices areworking in the linear region during the latch phase.The latch below keeps the input devices in the saturation region. The resulting larger gain of the inputdevices reduces the input offset voltage as shown.The input offset voltage of the tail referencedlatch is compared between two latches with thereferenced latch for 100 samples. The x-axis is thedeviation from the mean of the first latch and the yaxis is the deviation of the mean of the second latch.CMOS Analog Circuit DesignPage 32-28VDDLatchLatchvout-vout vin M1Latch070511-01Vref Vref-M2vin-All transistors are3.5µm/0.4µm exceptM1 and M2 P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-29CMOS LatchCircuit:Input offset voltage distribution:CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-30CMOS Latch with Different Inputs and OutputsWhen Latch bar is high, M5 and M6 are off, M7 is on, and the latch is disabled and theoutputs are shorted together.When Latch bar is low, the input voltages stored at the sources of M1 and M2 will causeone of the latch outputs to be high and the other to be low.The source of M1 and M2 that is higher will have a larger source-gate voltageresulting in a larger transconductance and more gain than the other transistor.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14)Page 32-31MetastabilityMetastability is the condition where the latch cannot make a decision in the timeallocated. Normally due to the fact that the input is small (within the input resolutionrange).Metastability can be improved (reduced) by increasing the gain of the comparator bypreceding it with an amplifier to keep the signal input to the latch as large as possibleunder all conditions. The preamplifier also reduced the input offset voltage.CMOS Analog Circuit Design P.E. Allen - 2016
Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14) Page 32-32SUMMARYThe performance of open-loop comparators can be improved by the use of autozeroingand hysteresisDiscrete-time comparators must work with clocksRegenerative comparators (latches) use positive feedbackThe propagation delay of the regenerative comparator is slow at the beginning andspeeds up rapidly as time increasesThe highest speed comparators will use a combination of open-loop comparators andlatchesCMOS Analog Circuit Design P.E. Allen - 2016
Example 32-1 Design of an Inverting Comparator with Hysteresis Use the inverting bistable to design a high-gain, open-loop comparator having an upper trip point of 1V and a lower trip point of 0V if V OH 2V and V OL -2V. Solution Putting the values of this example
Introduction of Chemical Reaction Engineering Introduction about Chemical Engineering 0:31:15 0:31:09. Lecture 14 Lecture 15 Lecture 16 Lecture 17 Lecture 18 Lecture 19 Lecture 20 Lecture 21 Lecture 22 Lecture 23 Lecture 24 Lecture 25 Lecture 26 Lecture 27 Lecture 28 Lecture
K. Webb ESE 499 15 Open-Loop Frequency Response & Stability Open-loop Bode plot can be used to assess stability But, we need to know if system is closed-loop stable for low gain or high gain Here, we'll assume open-loop-stable systems Closed-loop stable for low gain Open-loop Bode plot can tell us: Is a system closed-loop stable? If so, how stable?
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power system: the automatic load frequency control loop (ALFC) and the automatic voltage control loop (AVR). There is little interaction from the ALFC loop to the AVR loop but the AVR loop does affect the ALFC loop to a certain extent. The AVR loop tends to be much faster than the ALFC loop with time constants of much less than one second.
the opinions of those with direct ties to the West Loop. I live in the West Loop I work in the West Loop I own property in the West Loop I own a business in the West Loop I am generally interested in the West Loop* Other (please specify) * 0 20 40 60 80 100 23.6% 59.7% 5.6% 4.9% 85.4% 32.6% 18 West Loop Design Guidelines Community Feedback 1 .
The Do-While and For loop structures are pretest loops. In a posttest loop, the condition is evaluated at the end of the repeating section of code. This is also called an exit-controlled loop. The Do/Loop Until construct is a posttest loop. Do While Loop The while loop allows you to di
while loop Format: while condition: loop body loop body 18 one or more instructions to be repeated condition loop body false true After the loop condition becomes false during the loop body, the loop body still runs to completion (before its check before the next turn) and exit the loop and go on with the next step.
Lecture 1: A Beginner's Guide Lecture 2: Introduction to Programming Lecture 3: Introduction to C, structure of C programming Lecture 4: Elements of C Lecture 5: Variables, Statements, Expressions Lecture 6: Input-Output in C Lecture 7: Formatted Input-Output Lecture 8: Operators Lecture 9: Operators continued
