The MIPS Register Set - Holy Cross
The MIPS Register SetThe MIPS R2000 CPU has 32 registers. 31 of these are general-purpose registers that canbe used in any of the instructions. The last one, denoted register zero, is defined to containthe number zero at all times.Even though any of the registers can theoretically be used for any purpose, MIPSprogrammers have agreed upon a set of guidelines that specify how each of the regis- tersshould be used. Programmers (and compilers) know that as long as they follow theseguidelines, their code will work properly with other MIPS code.Symbolic Namezeroatv0 - v1a0 - a3t0 - t9s0 - s7k0 - k1gpspfpraNumber012-34-78 - 15, 24 - 2516 - 2326 - 2728293031UsageConstant 0.Reserved for the assembler.Result Registers.Argument Registers 1 · · · 4.Temporary Registers 0 · · · 9.Saved Registers 0 · · · 7.Kernel Registers 0 · · · 1.Global Data Pointer.Stack Pointer.Frame Pointer.Return Address.The MIPS Instruction SetThis section briefly describes the MIPS assembly language instruction set.In the description of the instructions, the following notation is used: If an instruction description begins with an , then the instruction is not amember of the native MIPS instruction set, but is available as a pseudoin- struction.The assembler translates pseudoinstructions into one or more native instructions. If the op contains a (u), then this instruction can either use signed or unsignedarithmetic, depending on whether or not a u is appended to the name of theinstruction. For example, if the op is given as add(u), then this instruction caneither be add (add signed) or addu (add unsigned). des must always be a register. src1 must always be a register. reg2 must always be a register. src2 may be either a register or a 32-bit integer. addr must be an address.
Arithmetic InstructionsOp absadd(u)anddiv(u) div(u) mul mulomult(u) neg(u)nor notor rem(u) rol rorsllsrasrlsub(u)xorOperandsdes, src1des, src1, src2des, src1, src2src1, reg2Descriptiondes gets the absolute value of src1.des gets src1 src2.des gets the bitwise and of src1 and src2.Divide src1 by reg2, leaving the quotient in registerlo and the remainder in register hi.des, src1, src2 des gets src1 / src2.des, src1, src2 des gets src1 src2.des, src1, src2 des gets src1 src2, with overflow.src1, reg2Multiply src1 and reg2, leaving the low-order wordin register lo and the high-order word in registerhi.des, src1des gets the negative of src1.des, src1, src2 des gets the bitwise logical nor of src1 and src2.des, src1des gets the bitwise logical negation of src1.des, src1, src2 des gets the bitwise logical or of src1 and src2.des, src1, src2 des gets the remainder of dividing src1 by src2.des, src1, src2 des gets the result of rotating left the contents ofsrc1 by src2 bits.des, src1, src2 des gets the result of rotating right the contents ofsrc1 by src2 bits.des, src1, src2 des gets src1 shifted left by src2 bits.des, src1, src2 Right shift arithmetic.des, src1, src2 Right shift logical.des, src1, src2 des gets src1 - src2.des, src1, src2 des gets the bitwise exclusive or of src1 and src2.Comparison Instructions Opseqsnesge(u)sgt(u)sle(u)slt(u)Operandsdes, src1, src2des, src1, src2des, src1, src2des, src1, src2des, src1, src2des, src1, src2Descriptiondes 1 if src1 src2,des 1 if src1 6 src2,des 1 if src1 src2,des 1 if src1 src2,des 1 if src1 src2,des 1 if src1 .otherwise.otherwise.
Branch and Jump InstructionsBranch lezbltzbgezalOperandslabsrc1, src2, labsrc1, src2, labsrc1, src2, labsrc1, src2, labsrc1, src2, labsrc1, src2, labsrc1, labsrc1, labsrc1, labsrc1, labsrc1, labsrc1, labsrc1, labbgtzalsrc1, labbltzalsrc1, labDescriptionUnconditional branch to lab.Branch to lab if src1 src2 .Branch to lab if src1 6 src2 .Branch to lab if src1 src2 .Branch to lab if src1 src2 .Branch to lab if src1 src2 .Branch to lab if src1 src2 .Branch to lab if src1 0.Branch to lab if src1 6 0.Branch to lab if src1 0.Branch to lab if src1 0.Branch to lab if src1 0.Branch to lab if src1 0.If src1 0, then put the address of the next instruction into ra and branch to lab.If src1 0, then put the address of the next instruction into ra and branch to lab.If src1 0, then put the address of the next instruction into ra and branch to riptionJump to label lab.Jump to location src1.Jump to label lab, and store the address of the next instruction in ra.Jump to location src1, and store the address of the nextinstruction in ra.
Load, Store, and Data MovementThe second operand of all of the load and store instructions must be an address. TheMIPS architecture supports the following addressing modes: Format(reg)constconst(reg)symbolsymbol constsymbol const(reg)MeaningContents of reg.A constant address.const contents of reg.The address of symbol.The address of symbol const.The address of symbol const contents of reg.LoadThe load instructions, with the exceptions of li and lui, fetch a byte, halfword, orword from memory and put it into a register. The li and lui instructions load aconstant into a register.All load addresses must be aligned on the size of the item being loaded. Forexample, all loads of halfwords must be from even addresses, and loads of words fromaddresses cleanly divisible by four. The ulh and ulw instructions are provided to loadhalfwords and words from addresses that might not be aligned properly.Op lalb(u)lh(u) liluiOperandsdes, addrdes, addrdes, addrdes, constdes, constlwlwllwr ulh(u)des,des,des,des, ulwdes, addraddraddraddraddrDescriptionLoad the address of a label.Load the byte at addr into des.Load the halfword at addr into des.Load the constant const into des.Load the constant const into the upper halfword of des,and set the lower halfword of des to 0.Load the word at addr into des.Load the halfword starting at the (possibly unaligned)address addr into des.Load the word starting at the (possibly unaligned) address addr into des.
StoreThe store instructions store a byte, halfword, or word from a register into memory.Like the load instructions, all store addresses must be aligned on the size of theitem being stored. For example, all stores of halfwords must be from even addresses,and loads of words from addresses cleanly divisible by four. The swl, swr, ush andusw instructions are provided to store halfwords and words to addresses which mightnot be aligned properly.OpsbshswswlOperandssrc1, addrsrc1, addrsrc1, addrsrc1, addrswrsrc1, addr ushsrc1, addr uswsrc1, addrDescriptionStore the lower byte of register src1 to addr.Store the lower halfword of register src1 to addr.Store the word in register src1 to addr.Store the upper halfword in src to the (possibly unaligned) address addr.Store the lower halfword in src to the (possibly unaligned)address addr.Store the lower halfword in src to the (possibly unaligned)address addr.Store the word in src to the (possibly unaligned) addressaddr.Data MovementThe data movement instructions move data among registers. Special instructions areprovided to move data in and out of special registers such as hi and lo.Op movemfhimflomthimtloOperandsdes, src1desdessrc1src1DescriptionCopy the contentsCopy the contentsCopy the contentsCopy the contentsCopy the contentsofofofofofsrc1 to des.the hi register to des.the lo register to des.the src1 to hi.the src1 to lo.Exception onReturn from exception.Makes a system call. See 4.6.1 for a list of the SPIMsystem calls.Used by the debugger.An instruction which has no effect (other than taking acycle to execute).
The MIPS AssemblerSegment and Linker DirectivesName.dataParametersaddrDescriptionThe following items are to be assembled into the datasegment. By default, begin at the next available addressin the data segment. If the optional argument addr ispresent, then begin at addr.textaddrThe following items are to be assembled into the textsegment. By default, begin at the next available address in the text segment. If the optional argumentaddr is present, then begin at addr. In SPIM, the onlyitems that can be assembled into the text segment areinstructions and words (via the .word directive).externsym sizeDeclare as global the label sym, and declare that it is sizebytes in length (this information can be used by theassembler).globlsymDeclare as global the label sym.Data .byte.half.spacebyte1 · · · byteNhalf1 · · · halfNsize.wordword1 · · · wordNDescriptionAlign the next item on the next 2n -byte boundary.align 0 turns off automatic alignment.Assemble the given string in memory. Do not nullterminate.Assemble the given string in memory. Do nullterminate.Assemble the given bytes (8-bit integers).Assemble the given halfwords (16-bit integers).Allocate n bytes of space in the current segment. In SPIM, this is only permitted in the datasegment.Assemble the given words (32-bit integers).The Native MIPS Instruction SetMany of the instructions listed here are not native MIPS instructions. Instead, theyare pseudoinstructions– macros that the assembler knows how to translate into nativeMIPS instructions. Instead of programming the “real” hardware, MIPS programmersgenerally use the virtual machine implemented by the MIPS assembler, which is mucheasier to program than the native machine.
The MIPS Instruction Set This section brie y describes the MIPS assembly language instruction set. In the description of the instructions, the following notation isused: If an instruction description begins with an, then the instruction is not a member of the native MIPS instruction set, but is available as a pseudoin-
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bits, gọi là MIPS-64. MIPS xem xét trong môn học này là MIPS làm việc với các thanh ghi chỉ 32 bit, gọi là MIPS-32. ÞTrong phạm vi môn học này, MIPS dùng chung sẽ hiểu là MIPS-32 Tóm lại, chỉ có 3 loại toán hạng trong một lệnh của MIPS 1. Toán hạng thanh ghi (Register Operands) 2.
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Table 1: How 2020 MIPS Final Scores Relate to 2022 MIPS Payment Adjustments Final Score Points MIPS Payment Adjustment 0.00 – 11.25 points Negative (-) MIPS payment adjustment of -9% 11.26 – 44.99 points Negative (-) MIPS payment adjustment, between 0% and -9%, on a linear sliding scale 45.00 points (Performance threshold 45.00 points)
Performance on EEMBC benchmarks aggregate for Consumer, Telecom, Office, Network, based on ARM1136J-S (Freescale i.MX31), ARM1026EJ-S, Tensilica Diamond 570T, T1050 and T1030, MIPS 20K, NECVR5000). MIPS M4K, MIPS 4Ke, MIPS 4Ks, MIPS 24K, ARM 968E-S, ARM 966E-S, ARM926EJ-S, ARM7TDMI-S scaled by ratio of Dhrystone MIPS within architecture family.
