Altera DE0 Board

DE0 User ManualThe ability to set arbitrary values into simple display devices is not needed in typical designactivities. However, it gives the user a simple mechanism for verifying that these devices arefunctioning correctly in case a malfunction is suspected. Thus, it can be used for troubleshootingpurposes.3.3Switches and ButtonsChoosing the Button tab leads to the window in Figure 3.6. The function is designed to monitor thestatus of switches and buttons in real time and show the status in a graphical user interface. It can beused to verify the functionality of the switches and buttons.Press the Start button to start button/switch status monitoring process, and button caption ischanged from Start to Stop. In the monitoring process, the status of buttons and switches on theboard is shown in the GUI window and updated in real time. Press Stop to end the monitoringprocess.Figure 3.6.Monitoring switches and buttons.The ability to check the status of button and switch is not needed in typical design activities.However, it provides users a simple mechanism for verifying if the buttons and switches arefunctioning correctly. Thus, it can be used for troubleshooting purposes.13

DE0 User Manual3.4SDRAM and Flash Controller and ProgrammerThe Control Panel can be used to write/read data to/from the SDRAM and FLASH chips on theDE0 board. Click on the Memory tab and select “SDRAM” to reach the window in Figure 3.7.Please note to erase the flash memory before writing data to it.Figure 3.7.Accessing the SDRAMA 16-bit word can be written into the SDRAM by entering the address of the desired location,specifying the data to be written, and pressing the Write button. Contents of the location can beread by pressing the Read button. Figure 3.7 depicts the result of writing the hexadecimal value7eff into location 000000, followed by reading the same location.The Sequential Write function of the Control Panel is used to write the contents of a file into theSDRAM as follows:1. Specify the starting address in the Address box.2. Specify the number of bytes to be written in the Length box. If the entire file is to beloaded, then a checkmark may be placed in the File Length box instead of giving thenumber of bytes.3. To initiate the writing of data, click on the Write a File to Memory button.4. When the Control Panel responds with the standard Windows dialog box asking for thesource file, specify the desired file in the usual manner.14

DE0 User ManualThe Control Panel also supports loading files with a .hex extension. Files with a .hex extension areASCII text files that specify memory values using ASCII characters to represent hexadecimalvalues. For example, a file containing the line0123456789ABCDEFdefines four 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loaded consecutivelyinto the memory.The Sequential Read function is used to read the contents of the SDRAM and place them into a fileas follows:1. Specify the starting address in the Address box.2. Specify the number of bytes to be copied into the file in the Length box. If the entirecontents of the SDRAM are to be copied (which involves all 8 Mbytes), then place acheckmark in the Entire Memory box.3. Press Load Memory Content to a File button.4. When the Control Panel responds with the standard Windows dialog box asking for thedestination file, specify the desired file in the usual manner.Users can use the similar way to access the Flash. Please note that users need to erase the flashbefore writing data to it.3.5PS2 DeviceThe Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time. Thereceived scan-codes are translated to ASCII code and displayed in the control window. Only visibleASCII codes are displayed. For control key, only “Carriage Return/ENTER” key is implemented.This function can be used to verify the functionality of the PS2 Interface. Please follow the stepsbelow to exercise the PS2 device:1. Choosing the PS2 tab leads to the window in Figure 3.8.2. Plug a PS2 Keyboard to the FPGA board. Then,3. Press the Start button to start PS2Keyboard input receiving process; Button caption ischanged from Start to Stop.4. In the receiving process, users can start to press the attached keyboard. The input data willbe displayed in the control window in real time. Press Stop to terminate the monitoringprocess.15

DE0 User ManualFigure 3.8.3.6Reading the PS2 KeyboardsSD CARDThe function is designed to read the identification and specification of the SD card. The 1-bit SDMODE is used to access the SD card. This function can be used to verify the functionality ofSD-CARD Interface. Follow the steps below to exercise the SD card:1. Choosing the SD-CARD tab leads to the window in Figure 3.9.2. Insert a SD card to the DE0 board, then press the Read button to read the SD card. The SDcard’s identification and specification will be displayed in the control window.16

DE0 User ManualFigure 3.9.3.7Reading the SD card Identification and SpecificationVGADE0 control panel provides VGA pattern function that allows users to output color pattern toLCD/CRT monitor using the DE0 FPGA board. Please follow the steps below to generate the VGApattern function:1. Choosing the VGA tab leads to the window in Figure 3.10.2. Plug a D-sub cable to the VGA connector of the DE0 board and LCD/CRT monitor.3. The LCD/CRT monitor will display the same color pattern on the control panel window.4. Click the drop down menu shown in Figure 3.10 where you can output the selected colorindividually.17

DE0 User ManualFigure 3.10. Controlling VGA display18

DE0 User ManualChapter 4Using the DE0 BoardThis chapter gives instructions for using the DE0 board and describes each of its I/O devices.4.1Configuring the Cyclone III FPGAThe procedure for downloading a circuit from a host computer to the DE0 board is described in thetutorial Getting Started with Altera's DE0 Board. This tutorial is found in the user manaul folder onthe DE0 System CD-ROM. The user is encouraged to read the tutorial first, and to treat theinformation below as a short reference.The DE0 board contains a serial EEPROM chip that stores configuration data for the Cyclone IIIFPGA. This configuration data is automatically loaded from the EEPROM chip into the FPGA eachtime power is applied to the board. Using the Quartus II software, it is possible to reprogram theFPGA at any time, and it is also possible to change the non-volatile data that is stored in the serialEEPROM chip. Both types of programming methods are described below.1. JTAG programming: In this method of programming, named after the IEEE standards JointTest Action Group, the configuration bit stream is downloaded directly into the Cyclone IIIFPGA. The FPGA will retain this configuration as long as power is applied to the board;the configuration is lost when the power is turned off.2. AS programming: In this method, called Active Serial programming, the configuration bitstream is downloaded into the Altera EPCS4 serial EEPROM chip. It provides non-volatilestorage of the bit stream, so that the information is retained even when the power supply tothe DE0 board is turned off. When the board's power is turned on, the configuration data inthe EPCS4 device is automatically loaded into the Cyclone III FPGA.The sections below describe the steps used to perform both JTAG and AS programming. For bothmethods the DE0 board is connected to a host computer via a USB cable. Using this connection, theboard will be identified by the host computer as an Altera USB Blaster device. The process forinstalling on the host computer the necessary software device driver that communicates with theUSB Blaster is described in the tutorial Getting Started with Altera's DE0 Board. This tutorial isavailable on the DE0 System CD-ROM.19

DE0 User ManualConfiguring the FPGA in JTAG ModeFigure 4.1 illustrates the JTAG configuration setup. To download a configuration bit stream into theCyclone III FPGA, perform the following steps: Ensure that power is applied to the DE0 boardConnect the supplied USB cable to the USB Blaster port on the DE0 board (see Figure 2.1)Configure the JTAG programming circuit by setting the RUN/PROG switch (see Figure 4.2)to the RUN position. The FPGA can now be programmed by using the Quartus II Programmer module to select aconfiguration bit stream file with the .sof filename extensionUSB Blaster CircuitQuartus IIProgrammerPROG/RUNMAX IIEPM240JTAG UARTJTAG Config Signals RUN Figure 4.1. The JTAG configuration schemeFigure 4.2. The RUN/PROG switch (SW2) is set in JTAG modeConfiguring the EPCS4 in AS ModeFigure 4.3 illustrates the AS configuration set up. To download a configuration bit stream into theEPCS4 serial EEPROM device, perform the following steps: Ensure that power is applied to the DE0 board20

DE0 User Manual Connect the supplied USB cable to the USB Blaster port on the DE0 board (see Figure 2.1)Configure the JTAG programming circuit by setting the RUN/PROG switch (see Figure 4.4)to the PROG position. The EPCS4 chip can now be programmed by using the Quartus II Programmer module toselect a configuration bit stream file with the .pof filename extension Once the programming operation is finished, set the RUN/PROG switch back to the RUNposition and then reset the board by turning the power switch off and back on; this actioncauses the new configuration data in the EPCS4 device to be loaded into the FPGA chip.Quartus IIProgrammerAS ModeUSB Blaster CircuitAuto Power-onConfigPROG/RUNMAX IIEPM240 PROG AS ModeConfigEPCS4SerialConfigurationDeviceFigure 4.3. The AS configuration schemeFigure 4.4. The RUN/PROG switch(SW2) is set in AS mode21

DE0 User ManualIn addition to its use for JTAG and AS programming, the USB Blaster port on the DE0 board canalso be used to control some of the board's features remotely from a host computer. Details thatdescribe this method of using the USB Blaster port are given in Chapter 3.4.2Using the LEDs and SwitchesThe DE0 board provides three pushbutton switches. The three outputs called BUTTON0, BUTTON1, and BUTTON2 are connected directly to the Cyclone III FPGA. Each switch provides a highlogic level (3.3 volts) when it is not pressed, and provides a low logic level (0 volts) whendepressed.There are also 10 slide switches (sliders) on the DE0 board. These switches are not debounced, andare intended for use as level-sensitive data inputs to a circuit. Each switch is connected directly to apin on the Cyclone III FPGA. When a switch is in the DOWN position (closest to the edge of theboard) it provides a low logic level (0 volts) to the FPGA, and when the switch is in the UP positionit provides a high logic level (3.3 volts).There are 10 user-controllable LEDs on the DE0 board. Each LED is driven directly by a pin on theCyclone III FPGA; driving its associated pin to a high logic level turns the LED on, and driving thepin low turns it off. Figure 4.5 and Figure 4.6 show the connections between the push buttons, slideswitches, and Cyclone III FPGAA list of the pin names on the Cyclone III FPGA that are connected to the toggle switches is givenin Table 4.1. Similarly, the pins used to connect to the pushbutton switches and LEDs are displayedin Table 4.2 and Table 4.3, respectively.3.3VBUTTON0H2BUTTON1G3BUTTON2F1Figure 4.5. Connections between the pushbutton and Cyclone III FPGA22

DE0 User ManualD2E4E3H7J7G5G4H6H5J6Logic 1 SW9SW8 SW7Figure 4.6.SW6 SW5 SW4SW3 SW2 SW1 SW0Logic 0 Connections between the toggle switches and Cyclone III EDG7LEDG8LEDG8LEDG9LEDG9Figure 4.7. Connections between the LEDs and Cyclone III FPGA23

DE0 User ManualTable 4.1.Pin assignments for the slide switchesSignal NameFPGA Pin No.DescriptionSW[0]PIN J6Slide Switch[0]SW[1]PIN H5Slide Switch[1]SW[2]PIN H6Slide Switch[2]SW[3]PIN G4Slide Switch[3]SW[4]PIN G5Slide Switch[4]SW[5]PIN J7Slide Switch[5]SW[6]PIN H7Slide Switch[6]SW[7]PIN E3Slide Switch[7]SW[8]PIN E4Slide Switch[8]SW[9]PIN D2Slide Switch[9]Table 4.2. Pin assignments for the pushbutton switchesSignal NameFPGA Pin No.DescriptionBUTTON [0]PIN H2Pushbutton[0]BUTTON [1]PIN G3Pushbutton[1]BUTTON [2]PIN F1Pushbutton[2]Table 4.3. Pin assignments for the LEDsSignal NameFPGA Pin No.DescriptionLEDG[0]PIN J1LED Green[0]LEDG[1]PIN J2LED Green[1]LEDG[2]PIN J3LED Green[2]LEDG[3]PIN H1LED Green[3]LEDG[4]PIN F2LED Green[4]LEDG[5]PIN E1LED Green[5]LEDG[6]PIN C1LED Green[6]LEDG[7]PIN C2LED Green[7]LEDG[8]PIN B2LED Green[8]LEDG[9]PIN B1LED Green[9]24

DE0 User Manual4.3Using the 7-segment DisplaysThe DE0 board has four 7-segment displays. These displays are arranged into two pairs and a groupof four, with the intent of displaying numbers of various sizes. As indicated in Figure 4.8, the sevensegments are connected to pins on the Cyclone III FPGA. Applying a low logic level to a segmentcauses it to light up, and applying a high logic level turns it off.Each segment in a display is identified by an index from 0 to 6, with the positions given in Figure4.9. In addition, the decimal point is identified as DP. Table 4.4 shows the connections between theFPGA pins to the 7-segment displays.HEX0HEX0 D0HEX0 D5HEX0 D0HEX0 D1HEX0 D2HEX0 D3HEX0 D1E11F11H12H13HEX0 D6HEX0 D4HEX0 D4HEX0 D5HEX0 D6HEX0 DPHEX0 D2HEX0 D3HEX0 DPG12F12F13D13Figure 4.8. Connections between the 7-segment displays and Cyclone III FPGA056412DP3Figure 4.9. Position and index of each segment in a 7-segment display25

DE0 User ManualTable 4.4. Pin assignments for the 7-segment displays.Signal NameFPGA Pin No.DescriptionHEX0 D[0]PIN E11Seven Segment Digit 0[0]HEX0 D[1]PIN F11Seven Segment Digit 0[1]HEX0 D[2]PIN H12Seven Segment Digit 0[2]HEX0 D[3]PIN H13Seven Segment Digit 0[3]HEX0 D[4]PIN G12Seven Segment Digit 0[4]HEX0 D[5]PIN F12Seven Segment Digit 0[5]HEX0 D[6]PIN F13Seven Segment Digit 0[6]HEX0 DPPIN D13Seven Segment Decimal Point 0HEX1 D[0]PIN A13Seven Segment Digit 1[0]HEX1 D[1]PIN B13Seven Segment Digit 1[1]HEX1 D[2]PIN C13Seven Segment Digit 1[2]HEX1 D[3]PIN A14Seven Segment Digit 1[3]HEX1 D[4]PIN B14Seven Segment Digit 1[4]HEX1 D[5]PIN E14Seven Segment Digit 1[5]HEX1 D[6]PIN A15Seven Segment Digit 1[6]HEX1 DPPIN B15Seven Segment Decimal Point 1HEX2 D[0]PIN D15Seven Segment Digit 2[0]HEX2 D[1]PIN A16Seven Segment Digit 2[1]HEX2 D[2]PIN B16Seven Segment Digit 2[2]HEX2 D[3]PIN E15Seven Segment Digit 2[3]HEX2 D[4]PIN A17Seven Segment Digit 2[4]HEX2 D[5]PIN B17Seven Segment Digit 2[5]HEX2 D[6]PIN F14Seven Segment Digit 2[6]HEX2 DPPIN A18Seven Segment Decimal Point 2HEX3 D[0]PIN B18Seven Segment Digit 3[0]HEX3 D[1]PIN F15Seven Segment Digit 3[1]HEX3 D[2]PIN A19Seven Segment Digit 3[2]HEX3 D[3]PIN B19Seven Segment Digit 3[3]HEX3 D[4]PIN C19Seven Segment Digit 3[4]HEX3 D[5]PIN D19Seven Segment Digit 3[5]HEX3 D[6]PIN G15Seven Segment Digit 3[6]HEX3 DPPIN G16Seven Segment Decimal Point 326

DE0 User Manual4.4Clock CircuitryThe DE0 board includes a 50 MHz clock signals. This clock signal is connected to the FPGA thatare used for clocking the user logic. In addition, all these clock

This tutorial is available in the directory DE0\DE0_user_manual on the DE0 System CD-ROM . 2. Connect the 7.5V adapter to the DE0 board 3. Connect a VGA monitor to the VGA port on the DE0 board 4. Turn the RUN/PROG switch on the left edge of the DE0 board to RUN position; the PROG position is used only for the AS Mode programming .File Size: 2MBPage Count: 54