Capacitor Voltage Balancing In Multilevel flying Capacitor .
Capacitor voltage balancing in multilevelflying capacitor inverters by rule-basedswitching pattern selectionL. Zhang and S.J. WatkinsAbstract: A rule-based scheme is investigated for capacitor voltage balancing in a multilevelflying capacitor inverter (MFCI). Without using voltage feedback, the scheme determines thebest switching pattern for maintaining nil mean current in all capacitors, hence minimisingthe capacitor voltage fluctuation. The method is developed to work with the selective harmonicelimination (SHE) technique for sinusoidal voltage generation applied to control static VARcompensators. The method has been designed using a four-cell five-level MFCI as an example.The selected pattern has been shown to give superior performance in load-voltage total-harmoniesdistortion level and mean capacitor voltage fluctuation. The method is validated experimentallyfor this form of MFCI.1IntroductionThe multilevel flying capacitor inverter (MFCI), a relativelynew type of power converter topology, has attractedworldwide attention for high power applications such asstatic power conditioners and large motor drives. Intereststems from the work of Meynard and Foch [1, 2] whoapplied the basic switched capacitor bridge principle toenable voltage clamping in multiple level power converters.Fig. 1 shows an example of a three-phase four-cell circuitsupplying an inductive load. Each phase limb consists ofa series of connected cells nested inwardly toward theload from the DC link. Each cell has a capacitor for clamping the node voltage and two bidirectional power switchesthat operate in a complementary fashion. A greater numberof possible output voltage levels requires more cells in eachphase limb and a greater total capacitor count. An importantadvantage of this circuit is that many switch state combinations produce the same voltage level. This gives flexibilityin choosing switching control strategies for optimised outputperformance. It also has a simple arrangement with modularbuilding blocks employing fewer switching devices, andsnubberless operation is possible.Use of MFCIs has been reported for high voltage staticVAR compensators [3, 4]. With the flexibility of multiplevoltage levels, and if the capacitor voltages are ideally constant, the circuit can regulate the amplitude of the desiredsinusoidal voltage by simple staircase control with a verylow switching frequency (one state change per switch percycle) and low harmonic distortion. The well-known selective harmonic elimination (SHE) scheme [5] is often used todetermine the electrical angles at which each voltage levelis applied. These angles set the fundamental voltage atsome specific magnitude and simultaneously suppress# The Institution of Engineering and Technology 2007doi:10.1049/iet-epa:20060270Paper first received 7th July and in revised form 12th October 2006The authors are with the School of Electronic and Electrical Engineering,University of Leeds, Leeds, LS2 9JT, UKE-mail: l.zhang@leeds.ac.ukIET Electr. Power Appl., 2007, 1, (3), pp. 339 –347certain selected harmonics. For closed-loop operation alook-up table can be established to generate switchingangles for different sinusoidal amplitudes desired by thecontroller. This scheme has been widely applied even forlarge variable speed drives [6]. Of course, in a practicalMFCI, with finite capacitor sizes the voltages across thecell capacitors do vary, but the capacitor values need tobe minimised for reasons of size and cost. With low switching frequencies the consequent drawback is in the increasedvoltage swings on the intermediate voltage levels. Thiscauses excessive voltage stress on the switching devicesand the voltage ripple works against low harmoniccontent in the voltage waveform.In ensuring proper operation of an MFCI, therefore, themain challenge is to maintain the correct voltage acrossthe floating or cell capacitor. It is essential to appreciatethat the MCFI is inherently stable under constant (positiveresistance) load conditions. Closed-loop control of capacitorvoltages is not fundamentally necessary, because, for asteady load, they automatically settle at a stable fractionof the DC-link voltage. However, closed-loop control canbe used to reduce the capacitor voltage swings and toimprove response speed at transient load changes. Forexample, Meynard’s group reported a fuzzy logic controllerto improve closed-loop capacitor voltage balance [7]. Theyalso developed a voltage observer for use in active cellcapacitor voltage regulation [8, 9]. Other significant workis from the group at Grenoble on a sliding-mode capacitorvoltage control (CVC) algorithm [10]. Researchersat Eindhoven investigated capacitor voltage balancingusing system modelling [11]. Nearly all these approachesrequire capacitor voltage measurement, although someresort to mathematical models which are complicatedto implement. The concern is that these approachesrequire a large number of capacitor voltage feedbackloops, in addition to the output load voltage measurement.For example the converter of Fig. 1 requires nine additionalcapacitor voltage feedback loops. This number increaseswith an increasing number of voltage levels andthe control strategy for load voltage/current becomescomplicated.339
Fig. 1Five-level flying-capacitor inverter circuitThe present paper investigates a rule-based switchingstrategy for capacitor voltage balance without cell-capacitorvoltage feedback controls. The scheme employs a switchingpattern selection mechanism which, not only maintains nilmean current flowing in all capacitors, but also minimisesthe inevitable fluctuation in the voltage across capacitorsof finite value. The scheme is simple compared with theconventional feedback approach. It requires load voltageand current measurements to determine the load powerfactor and current direction. As these are already availablein an inverter system, no additional sensors are required.The method is developed for sinusoidal voltage generationusing the SHE technique and devices are switched only ator near fundamental frequency. Though the analysis andsimulation studies of the method described here are concentrated on steady-state operation, the method can be used foroutput voltage feedback control, such as in high– voltageVAR compensators. Experimental results will demonstratethat balanced capacitor voltages are obtained, and hencetotal harmonic distortion (THD) of output line voltage/current is significantly reduced.2Switching states and sequences for balancingrequirement2.1DC voltage levels from zero to Vdc , at the load terminal withrespect to the negative DC link voltage. When two limbs areconfigured as a full-bridge inverter it can apply 2N þ 1 distinct voltage levels across the load. In a balanced inverter,the floating cell-capacitor average voltages are ideallykept at multiples of Vdc/N, therefore, the cell-capacitor voltages will range between Vdc/N and (N 2 1)Vdc/N, with thelowest voltage across the capacitor associated with thecomplementary switch pair nearest the load terminal.The number of switching states M capable of producingany particular intermediate voltage level (including zerovolts) can be calculated by the formula [12]Mk ¼NY k 11 ð2 N nÞ forðN kÞ!n¼00 k,Nð1Þwhere k defines the level number and is equal to 0 for the 0 Vlevel. Thus, for example, for a two-cell full bridge circuit togenerate an output voltage equal to 2Vdc/2, Mk ¼ 4. Whenthe number of cells N ¼ 4, as in Fig. 1, Mk ¼ 15 for anoutput voltage of 2Vdc/4. This above relationship quantifiesthe complexity of the operating modes available in flyingcapacitor inverters. This increases greatly as the number oflevels is increased as is illustrated in Table 1.Switching states2.2As shown in Fig. 1, for an N-cell flying capacitor inverter,each limb has 2 N bidirectional switches (IGBT and antiparallel diode combination) and can provide N þ 1 distinctSelective harmonic elimination (SHE) schemeTo synthesise a desired sinusoidal waveform, the flexibilityof multiple voltage levels allows simple staircase control,Table 1: Single-phase full-bridge flying-capacitor inverter switching statesLevel (N þ 1)340SwitchesCapacitorTotal no. ofSwitch modescellsswitch statesfor 0V3821664123642051642547062051024252IET Electr. Power Appl., Vol. 1, No. 3, May 2007
scheme maintains the output as an odd function of time,as implied in this Fourier series and as shown in Fig. 2.For the four-cell five-level circuit, only two angles aredetermined to perform control with the fundamental regulated and one harmonic eliminated. Numerical techniquesare applied to solve the nonlinear equationsb1 ¼4 VDC ðcosða1 Þ þ cosða2 ÞÞ ¼ ma 2 VDC ð3ÞpandFig. 2 Ideal phase and line voltages, normalised to Vdc , for SHEcontrol (ma ¼ 0.85)whereby each voltage level is applied across the load atpredefined electrical angles in a fundamental cycle. Usingthe selective harmonic elimination (SHE) scheme, theswitching angles of the inverter can be determined to setthe fundamental voltage at some specific magnitude andsimultaneously suppress certain harmonics. In its simplestcontrol form, the resultant waveform for the phase voltageof the inverter in Fig. 1 has the shape of a staircase asshown in Fig. 2. SHE determines each of the switchingangles according to the Fourier series expressed asV ðvtÞ ¼1Xbn sinðn vtÞð2Þn¼1where1bn ¼pðpf ðvtÞ sinðn vtÞ dðvtÞ pwhere the time origin is placed, for convenience, at the zerocrossing of the fundamental component. The controlb5 ¼4 VDC ðcosð5 a1 Þ þ cosð5 a2 ÞÞ ¼ 05 pð4Þfor a1 and a2 which are 26.138 and 60.978, respectively.Fig. 2 shows the resultant staircase shaped phase andline voltage waveforms when the peak magnitude of thefundamental component is set to 85% of Vdc .2.3Switching sequencesIt has already been shown that there is more than oneswitching state capable of providing an intermediate levelvoltage at the load terminal of the inverter. For ideal cellcapacitors with infinite capacitance, choosing the switchingstate at each voltage level would be relatively simple.However, in a real system, the different switching states ata given voltage level lead to different current paths withinthe flying-capacitor inverter circuit. The current flowingthrough the cell-capacitors will cause the voltages to varyand this variation is proportional to the amplitude, polarityand conduction duration of the current. In addition thepower devices’ switching losses need to be kept as low aspossible, for high efficiency, and their level of usage shouldalso balance. Thus, the selection criteria obey the following:Fig. 3 Control of a two-cell three-level flying-capacitor invertera Four switching states for a single limbb Full-bridge circuitIET Electr. Power Appl., Vol. 1, No. 3, May 2007341
(1) allow one independent switch changing state pervoltage transition;(2) maintain capacitor voltage balancing;(3) maintain equal switch device usage, hence thermalbalance.Items 2 and 3 are related; i.e. achieving capacitor voltagebalance ensures the inverter is thermally balanced with allswitches having the same average loss.The flying-capacitor inverter can operate with inherentcapacitor voltage balancing so long as the control utilisesall the modes of charging and discharging at an intermediatevoltage level [1, 2]. This can be illustrated using the simplestcase where a two cell three-level inverter supplies a resistiveload. Fig. 3a shows all the possible switching states, hencecurrent paths, for the inner cell of one limb of such acircuit. States 0 and 3, and states 1 and 2 form, respectively,complementary pairs where their correct usage can ensurebalancing of the capacitor voltages and device power loss.In a steady state, states 1 and 2 can be used for equal timeswithin a half cycle, if they are used in turn at the points ofrising and of falling voltage. With the resistive load, theload current will be the same at these two instants, so thenet change in capacitor charge will be balanced to zeroafter only one half cycle. Average device losses will alsobe the same. States 0 and 3 do not affect the capacitorcharge, but their complementary usage must ensure thatthey occur at times where the load current, even if the loadis reactive, is of equal and opposite polarity, and thisensures the same average losses in each power device.Another useful illustration is the two-cell full-bridgeinverter shown in Fig. 3b. There are four independentswitches S12 , S11 , S22 , S21 and their combined state canbe represented as 4 binary bits in the same order. Initially,a suitable switching state sequence for synthesisingthe positive half cycle of a sine wave may be[0000] ! [0100] ! [1100] ! [1000] ! [0000]. Likewisethe switching state sequence for the negative half cyclemay be [0000] ! [0001]! [0011]! [0010]! [0000].Even for a partly reactive load, such a sequence, ensuresthat capacitor voltages are balanced within one completeTable 2:342Fig. 4 One phase limb of four-cell MFCI of Fig. 1a Simplified four-cell inverter phase-limb circuit andb its allowable transitions between level statessinusoidal cycle, as charging and discharging of each of thecapacitors takes place at the same voltage and current levelsfor the same length of time. Meanwhile the total turn-on durations for devices at the same current level but in differentlimbs are also equal, hence achieving overall thermal balance.3Switching pattern selection for N-cell invertersApplying the stated principle, an MFCI with N capacitorcells will require N cycles, hence N switching sequences,to balance the capacitor voltages and equalise the conduction losses in the switches [12]. We refer to a set of NCapacitor voltage net change for each inverter limb switching stateSwitching stateOutput ge(þVE)/discharge( 2 VE)discharge( 2 VE)discharge( 2 VE)C3C2C12VEþVE0000 (0)21.00001 (1)20.50010 (2)20.50100 (4)20.52VEþVE2VE1000 (8)20.50011 (3)00101 (5)02VE0110 (6)02VEþVE2VE1001 (9)0þVE1010 (A)0þVE1100 (C)00111 (7)þ0.52VE1011 (B)þ0.5þVE1101 (D)þ0.51110 (E)þ0.51111 (F)þ1.0þVE2VEþVE2VE2VEþVEþVE2VE2VEþVE2VEIET Electr. Power Appl., Vol. 1, No. 3, May 2007
Table 3:24 groups of switching sequencesLevel 0Switching sequence groups7 E D BB 7E DB 7 E DD B 73 þ C and 6 þ 93; 6; C ; 93; 6; C ; 91 249; 3; 6; C1 2 489; 3; 6; C7 B D EB E7 D7 B DED 73; A; 5; C3; A; 5; C5; 3; C ; A5; 3; C ; A7 B E DD E7 BB 7 D ED E 7 B5; A; 6; 95; A; 6; 99; 6; 5; A1 2 489; 6; 5; A7 B D7 B EB 7 DEB 73 þ C and 5 þ A6 þ 9 and 5 þ A3þC5þA6þ91 2112244884 8E11224884 8D1 248E1 2 48EB1 28481 2 4ED3; 3; C ; C3; 3; C ; C3; 3; C ; C1 243; 3; C ; C1 247 B D E7 E D BD B7 ED E5; A; 5; A5; A; 5; A5; A; 5; A7 B5; A; 5; AB 7 E DB E 7 DD 7 E BD E 7 B9; 6; 6; 99; 6; 6; 99; 6; 6; 99; 6; 6; 91 21244881 2 4 81 21244881 2 4 8124881 2 4 8128481 2 4 8switching sequences as a switching pattern, and the criteriafor a good switching pattern are:switching sequences are listed as follows† having no switching states which cause a capacitor to becharged and subsequently discharged, or vice versa, at peakcurrent;† switching states being well matched to ensure nil netcharge accumulations in all cell capacitors.3; 3; 5; 5; 9; 9; 3; 3; 6; 6; A; A; 5; 5; 6; 6; C ; C ; 9; 9; A; A; C ; C7 B 7 D B D 7 B 7 E B E 7 D 7 E D E B D B E D EA rule-based selection scheme is now accordingly developed and tested, using a four-cell five-level inverter as anexample. The method can be extended to an MFCI of anynumber of levels.3.1 Switching states and sequences in a four-cellinverterA simplified diagram for one phase-limb of the four-cellMFCI given in Fig. 1 is shown in Fig. 4a. There are 16 distinct switching states for this circuit. Table 2 lists all ofthem, represented as 16 binary numbers, their corresponding normalised output voltage level and net chargingeffect, on each of the cell capacitors, for a positive loadcurrent. The most significant bit of these binary numbers controls the outer complementary switch pair nearest the DC link(S4). ‘1’ indicates that the upper switch is in conduction andcorresponds to a nonzero voltage level at the relevant inverteroutput terminal. As can be seen in the Table, the switchingstates for the normalised voltage levels 20.5 and 0.5 alllead to different charging effects in the three cell capacitors,hence causing the voltage swings.Considering the charging and discharging characteristic forall capacitors in this inverter, the switching states for 0 voltagelevel can be grouped in three complementary pairs, i.e. states 3& C, states 5 & A and states 6 & 9, as shown in Table 3.Synthesising a sinusoidal cycle using the SHE staircaserequires the inverter stepping through a set of three intermediate states, i.e. a switching sequence, from voltage levels 21 toþ1. The possible switching sequences are limited first byselection condition 1 listed in Section 2, so the number ofallowable transitions between switching states in this inverteris as illustrated in Fig. 4b. In total there are four possible pathsbetween level 21 and a level 20.5, three between any forlevel 20.5 and a level 0, two between any for levels 0 and alevel þ0.5 and one between any level for þ0.5 and levelþ1. Thus, 24 different sequences of switching states can beused when stepping up the norminal voltage level from 21to þ1. For instance, the switching states to be used in onecycle may be 0 [0000], 1 [0001], 9 [1001], D [1101] and F[1111], in hexadecimal notation. This is a switching sequence1 1 1 1 1 1 2 2 2 2 23.22 4 4 4 4 44 8 8 8888Valid switching patterns and their selectionsA pattern for a four-cell inverter consists of four switchingstate sequences for four cycles. To choose the best pattern, itis necessary to investigate the total number of valid patternsfor this inverter. Also, in this study, it is assumed that theload is inductive, so the current waveform is sinusoidaland the phase current lags the phase voltage fundamentalcomponent.A good starting point in identifying valid balancingswitching patterns is to keep the individual level switchingstates the same over one complete cycle, thus using one outof the 24 sequences given in Section 3.1. The subsequent threesequences can be chosen according to the three complimentary pairs of level 0 switching states, it is clear that there aregroups of 6 pattern permutations made up of just 4 individualsequences, where the sequence order is varied. These groupsof sequences are listed in Table 3, with the level 0 contributingstates shown as reference. The basic requirement is that allfour 20.5 and þ0.5 level states are used, but the level 0states can be taken from either one complementary pair setor two sets out of the six. Thus, there are in fact 24 differentgroups of switching sequences. By permutation, each has 6different patterns, so we have a grand total of 144 valid balancing patterns that meet the minimum switching transition criteria. Taking the upper left group in Table 3 as an example, the6 pattern permutations in this group are as follows7 E D B 7 EB D 7 D EB 7 D BE 7 BE D 7 B D E36C 9; 369C ; 3C 69; 3C 96; 396C ; 39C 612 4 8 128 41 4 28 1 4 82 182 418 4 2With such a large number of possible balancing patterns, thetwo rules stated earlier in this Section have been applied toDlabelled as 9. Adapting this labelling method, the 24 possible1IET Electr. Power Appl., Vol. 1, No. 3, May 2007Fig. 5 Ideal phase V/I waveforms with 458 lagging current343
previous level þ0.5 state. For instance, state 8 [1000]should not follow state 7 [0111]. According to thisrule the following consecutive sequences pairs are notpreferred7 YE YDYB YZ 8Z 1Z 2Z 4X X ; X X ; X X and X XFig. 6 Current flowing through C3 when using switchingsequence 4,7,5select the best one. The first avoids those switching patternswhich cause the same capacitor to be charged and subsequently discharged, or vise versa at peak current. Fig. 5shows that the phase current magnitudes are peaked atlevels þ0.5 and 20.5, respectively. Hence, these regionswill have the largest levels of capacitor voltage variation.So, if state 7[0111] is used at þ0.5 level in the firstsequence, the voltage drop on C3 would be the maximumdue to the peak current discharging. Subsequently, if applying state 8[1000] at 20.5 level in the immediate sequence,C3 would be charged with the most negative current causingits voltage to reduce further. Thus, the preferred switchingstate at level 20.5 should not cause the voltage across C3to change in the same direction as that due to the previoussequence at level þ0.5. This can be obtained by excludingthe next level 20.5 state being the 1’s complement of theIn this notation, symbols X, Y, Z indicate indifferent stateswhich need not be the same in consecutive columns.The second rule considers the charging/discharging ofcapacitors within one sinusoidal cycle due to the switchingsequence used. The aim is to ensure that a particular capacitor is in the same current path over this cycle, so that thecapacitor concerned has no, or as little as possible, netcharge accumulation. As shown in Table 2, when adjacentswitches are in the opposite state, the capacitor betweenthem lies in the load current path, and so its voltagewould swing. Again, with regard to the peak and troughof the current occurring around level þ0.5 and level20.5, respectively, it is preferable if as many cells as possible are in the same state at both levels. Priority for this rulecan be assigned to the higher voltage capacitor, i.e. C3 , as itwill see the largest voltage change. For example, if at level20.5 the switching state is 4 [0100], then state 7 [0111] ispreferred for level þ0.5. In both sequences, C3 lies in theload current path and is in discharging mode. Fig. 6.shows the resultant current flowing through C3 . As can beseen, there is symmetry in the cell-capacitor current, andso the mean current is zero leading to no net change in cellcapacitor voltage. Applying the same rule, states 8 [1000]and B [1011] are also preferred within a sequence as C3 isin charging mode for both voltage stepping-up and downcases. As only one pair of switching devices is allowed tochange state at a time, only four sequences would bepreferred for minimising the voltage variation on C3 overTable 4: Comparison between two switching patterns and ideal caseParameterSwitching patternsIdealPattern 1Pattern 2Actual modulation depth, ma1.0001.0291.030Power factor0.6940.6970.686Phase voltage THD, %19.2516.9223.81Line voltage THD, %14.5313.0719.881.763.499.41Phase current THD, %Ideal voltageCapacitor mean voltages (% ofunit cell voltage)Actual voltage%Voltage rippleActual voltage%Voltage 12.14333.2400.0400.00401.9Mean ripple voltage, %110.471.759.255Capacitor peak voltages100.0110.410.4105.15.1(% of unit cell 25.1400.0418.24.55431.0Mean peak voltage, %Switch peak blocking voltages(% of unit cell .1100.0167.8205.9100.0137.2140.3IET Electr. Power Appl., Vol. 1, No. 3, May 2007
one sequence cycle, and, in each case, C3 is in the samecurrent path throughout the cycle. These are7 7 BB4 4 885; 6; 9 and AAccording to this rule there are 4 sequences, shown asfollows, preferred within a pattern7 7 BB4 4 885; 6; 9 and AWhen applying this second rule to C2 , and to C1 , states inthe adjacent cells around C3 must not be complements,otherwise this rule will be broken, therefore this meansthat the following 4 sequences are preferred for use in apattern:D D EE425; C ; 6 and A42Applying the preceding two rules, one particular pattern outof 144 is judged to offer the best performance, namely7E D B36C 912 4 8ðPattern 1ÞThis pattern does not have any consecutive states whichbreak the first rule governing the level þ0.5 followed bylevel 20.5. It also contains 2 sequences from the secondrule which have preferred state combinations for levels20.5 and þ0.5.The various balancing patterns have been screened forones which are likely to cause poor overall performance.One such pattern, which breaks the first rule only, has onegood sequence from the second rule for C1 and is as follows7B ED3AC 528 41ðPattern 2ÞThe same rule-based analysis can be done for other loadcharacteristics. In the case of a leading phase currentangle, the second rule governing a sequence still applies;the first rule’s reasoning is the same but applied this timeto a sequence level 20.5 state followed by the nextsequence level þ0.5 state.The overall pattern, thus derived, is repeated once everyfour cycles (number of cells), with different switch statesused at the same voltage level of each cycle.4Fig. 7 Comparison of two switching patterns; PATTERN 1(upper), PATTERN 2 (lower)abcdLine voltage waveformsLine voltage spectraLoad phase current spectraCapacitor voltagesComparison of balanced switching patternsTo confirm that the rules governing the pattern selectionare valid, simulation studies of all the preceding-listed144 switching patterns were carried out [13], but, tosave space, only results for switching patterns 1 and 2identified in Section 3 are presented in Table 4. Theseare also compared with the ideal case when constantcapacitor voltages are always maintained. The performancecriteria for the best pattern are the minimum THDvalues, for both load voltage and current, and lowest percentage capacitor voltage variations. In simulation theDC link voltage was set to 400 V and control settingswere ma ¼ 1 and a fundamental frequency of 50 Hz, using5th harmonic elimination angles for staircase SHEcontrol. The phase voltage fundamental is therefore 141.4V(RMS) and the line voltage fundamental is 244.9 V(RMS). The load model used has component valuesR ¼ 2.5 V and L ¼ 7.958 mH, and the individual cellcapacitance is 10 mF. The nominal output power for anIET Electr. Power Appl., Vol. 1, No. 3, May 2007Fig. 8 Experimental four-cell five-level flying-capacitor inverterassembly345
equivalent ideal sinusoidal system is 12 kW with powerfactor 0.707.The results obtained, as can be seen in Table 4, confirm7E D Bour prediction; Pattern 1,36C 9 , offers lower output12 4 8waveform harmonic distortion compared to Pattern 2,7B ED3AC 5 , with THD values for phase voltage being28 4116.92% against 23.81%, and for line-line voltage13.07% against 19.88% . Its phase and line voltageTHDs are even lower than the ideal case. The phasecurrent THD is also significantly lower than that resultingfrom Pattern 2. Figs. 7a and b show the line voltagewaveforms and their spectra for the two cases, with thefrequency components normalised to the fundamental.Clearly, Pattern 1 gives better waveform with lowerTHD level than its counterpart. Notice that a 12.5 Hzcomponent is present in the voltage spectrum for bothpatterns, and its magnitude is higher for the inferiorPattern 2. This component is due to the balancingpattern control strategy which repeats every four cycles,i.e. 12.5 Hz. Phase current spectra for both patterns areshown in Fig. 7c.Fig. 9The capacitor voltage waveforms, shown in Fig. 7d, arethe most revealing. The individual cell-capacitor voltages(plotted on the same zero axis for reference) of the invertercontrolled by the two balancing pattern schemes are shown.As listed in Table 4 with Pattern 1, voltage ripple is reasonably low with mean ripple voltage only 1.75%, whereasPattern 2 is significantly higher at 9.25%. The mean peakvoltage variance for Pattern 1 is also lower than Pattern 2at 7.1% to 14.5%. The peak blocking voltage for Pattern 1is at 50 % of the nominal values, but, for Pattern 2, it issignificantly higher at around 100% of the nominal level.This is the primary reason for Pattern 2’s poorer waveformperformance.It should be stressed that this proposed method, thoughit does not require capacitor voltage measurements, needsto have information on load current direction, magnitudeand phase angle. These are usually available in a convertersystem. Like the SHE scheme, the method will suit particularly well to high power applications with low switching frequency and dynamics. In particular, it can beapplied in combination with SHE, for closed-loop regulation of the terminal voltage of a static VAR compensatorwith constant frequency. Switching angles for differentComparison of experimental and simulation resultsa Phase current and cell capacitor voltages for PATTERN 1b Phase current and cell capacitor voltages for PATTERN 2346IET Electr. Power Appl., Vol. 1, No. 3, May 2007
sinusoidal magnitudes can be calculated off-line and storedin a ROM. The switching sequences and charging/discharging patterns for each capacitor during previous cyclesneed to be stored and updated every N cycles. Suitableswitching sequences can be selected according to thepresent instantaneous current direction and magnitude.5 Test of a four-cell laboratory prototypeinverterThis rule-based method has been tested on a practical fourcell MFCI. As a design starting point, 5% current harmonicdistortion is acceptable. The maximum load power isassumed to be about 1.0 kW with a lagging power factorof around 0.7. The DC link voltage is 400 V, so the unitcell voltage is 100 V, the required capacitance has to begreater than 1.02 mF to avoid excessive voltages acrossthe switches. For the practical inverter, standard-value1 mF electrolytic capacitors, with a peak voltage capabilityof 200 V, have been used. The power switches need to copewith a peak voltage of at least 150 V. The IRG4PC30KD 30A 600 V IGBT (International Rectifier), incorporating anantiparallel diode of equivalent rating, is appropriate.The assembled inverter is shown in Fig. 8, with the cellcapacitors clearly visible below each set of inverter PCBs.There is also one 1 mF 450 V electrolytic capacitor acrossthe DC link connections to the inverter.The digital gate firing pulse generation and the differentforms of control scheme are implemented on a MemecSpartan-IITM L
Capacitor voltage balancing in multilevel flying capacitor inverters by rule-based switching pattern selection L. Zhang and S.J. Watkins . new type of power converter topology, has attracted . It also has a simple arrangement with modular
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