Cell Today And Tomorrow
Systems and Technology GroupCell today and tomorrowH. Peter Hofstee, Ph. D.Cell Chief Scientist andChief Architect, Cell Synergistic ProcessorIBM Systems and Technology GroupSCEI/Sony Toshiba IBM (STI) Design CenterAustin, Texas 2005 IBM Corporation
Systems and Technology GroupAcknowledgements Cell Broadband Engine (“Cell”) is the result of a deeppartnership between SCEI/Sony, Toshiba, and IBM Cell represents the work of more than 400 peoplestarting in 2001and a design investment of about 400M2 2005 IBM Corporation
Systems and Technology GroupAgenda Basics– Performance: Power wall , Memory/Latency wall– Multicore and specialization Cell– Asynchronous load/store (DMA)– Microarchitecture decisions Cell Performance– Things that work really well– Things that will likely work well– Question marks Cell Systems Future of Cell and things for Academia to look at3 2005 IBM Corporation
Systems and Technology GroupBASICS4 2005 IBM Corporation
Systems and Technology GroupComputing Paradigm ShiftToday:– Single thread performance hitting limits Architecture and process technology saturated Small percentage gains expected to remainBut:– Signs of paradigm shift to applicationspecific system customizationSingle Thread PerformanceSPECintSingle threadperformancegrowth rate slowsdramaticallyHistorical Trend45% CGR Large multiple gains for specific applications Cell– 50x on TRE, 100x on FFT Datapower–XML acceleration Many examples in embedded marketsFuture:– Greater performance demands Immersive Interaction–3D, real-time, gaming inspired applications–Rich media, data-intensive content Sensory Computing–New network tier–Autonomous agents performing intelligent analysis on streaming data A&D: battlefield coordination5 2005 IBM Corporation
Systems and Technology GroupSolutions Memory wall:– More slower threads– Asynchronous loadsINCREASECONCURRENCY:Multi-Core Efficiency wall:– More slower threads– Specialized function Power wall:– Reduce transistor power operating voltage limit oxide thickness scaling limit channel lengthINCREASESPECIALIZATION:Non-Homogeneous– Reduce switching per function6 2005 IBM Corporation
Systems and Technology GroupCELL7 2005 IBM Corporation
Systems and Technology GroupMotivation: Cell Goals Outstanding performance, especially ongame/multimedia applications.– Real time responsiveness to the user and thenetwork.– Challenges: Real-time in an SMP environment, SecurityApplicable to a wide range of platforms.– Challenge: Maintain programmability while increasing performanceSupport an introduction in 2005/6.–8Challenges: Power Wall, Frequency Wall, Memory WallChallenge: Structure innovation such that 5yr. schedule can be met 2005 IBM Corporation
Systems and Technology GroupCell Concept Compatibility with 64b Power Architecture – Builds on and leverages IBM investment and community Increased efficiency and performance– Non Homogenous Coherent Chip Multiprocessor Allows an attack on the “Frequency Wall”– Streaming DMA architecture attacks “Memory Wall”– High design frequency, low operating voltage attacks “Power Wall”– Highly optimized implementation Interface between user and networked world– Flexibility and security– Multi-OS support, including RTOS/non-RTOS– Architectural extensions for real-time management9 2005 IBM Corporation
Systems and Technology GroupCell Architecture is 64b Power Architecture PowerISAMMU/BIUMemoryPower ISAMMU/BIUCOHERENT BUSIOtransl.Incl. coherence/memorycompatible with 32/64b Power Arch. Applications and OS’s10 2005 IBM Corporation
Systems and Technology GroupCell Architecture is 64b Power Architecture PlusPowerPowerMemoryISAISAFlow Control (MFC)Memory RMTMMU/BIUMMU/BIU RMT RMTCOHERENT BUS ( RAG)MMU/DMAMMU/DMA RMT RMT LS AliasLocal StoreLocal StoreLS AliasMemoryMemory 11 RMTIOtransl. 2005 IBM Corporation
Systems and Technology GroupCell Architecture is 64b Power Architecture MFCPlusPowerPowerSynergisticISAISA RMTProcessorsMemory LS Alias12 RMTMMU/BIUMMU/BIU RMT RMTIOCOHERENT BUS ( RAG)Syn.LS Alias Proc.ISAMMU/DMA RMTLocal StoreMemorySyn. Proc.ISAtransl.MMU/DMA RMTLocal StoreMemory 2005 IBM Corporation
Systems and Technology GroupAsynchronous Load/Store (DMA) THE major architectural decision in Cell– Motivated by memory wall– Enabled by a large market Fundamental change to programmers.– Transition from demand-fetch to software controlledprefetch– Bill Dally’s “plumbing project analogy”– “Bucket brigade” analogy13 2005 IBM Corporation
Systems and Technology GroupSPE BLOCK DIAGRAMFloating-Point UnitPermute UnitFixed-Point UnitLoad-Store UnitBranch UnitChannel UnitLocal Store(256kB)Single Port SRAMResult Forwarding and StagingRegister FileInstruction Issue Unit / Instruction Line BufferOn-Chip Coherent Bus8 Byte/Cycle1416 Byte/Cycle128B Read128B WriteDMA Unit64 Byte/Cycle128 Byte/Cycle 2005 IBM Corporation
Systems and Technology GroupOther (Micro)Architectural and Decisions Large shared register file Local store size tradeoffs Dual issue, In order Software branch prediction ChannelsMicroarchitecture decisions, more so than architecture decisionsshow bias towards compute-intensive codes15 2005 IBM Corporation
Systems and Technology Group16 2005 IBM Corporation
Systems and Technology GroupCELL PROCESSOR STATISTICS 250M transistors 235mm2– Lab conditions– Most efficient at 1V 200 GFlops (SP) @3.2GHz 20 GFlops (DP) @3.2GHz Up to 25.6 GB/s memory B/W Up to 70 GB/s I/O B/W– Practical 50GB/s 100 simultaneous bustransactionsFrequency [GHz] Top frequency 4GHzHardware Performance Measurement(85 C)4.5Fmax43.530.911.1Supply Voltage1.2First pass hardware measurement in theLab - Nominal Voltage 1V– 16 8 entry DMA queue per SPE17 2005 IBM Corporation
Systems and Technology GroupCELL PERFORMANCE(AND PROGRAMMING)18 2005 IBM Corporation
Systems and Technology GroupThings that work extremely well today ( up to 100x) Problem can be re-coded Predictable non-trivial memory access pattern– Can build scatter-gather lists Problem can benefit from SIMD Focus on 32b float, or 32b integer Examples:– FFTw ( best result about 100GFlops )– Terrain Rendering Engine– Volume rendering Typical code is double-buffered gather-compute-scatter19 2005 IBM Corporation
Systems and Technology GroupThings that work well today ( about 10-20x) Compute bound codes Small enough to be rewritten Main datatype is 32b float or 32b Int Benefits from SIMD Examples:– Crypto codes ( RSA, SHA, DES, etc. etc. etc.)– Media codes ( MPEG 2, MPEG 4, H.264, JPEG )– many many others 20 2005 IBM Corporation
Systems and Technology GroupThings likely to work well Library . Device/API based applications– Graphics and physics and sound and Scientific codes library based– No rewrite– If granularity is ok21 2005 IBM Corporation
Systems and Technology GroupQuestion marks Can a compiler based approach, without restructuring codespecifically for the SPEs result in a chip-level advantage?– About 3-4x more SPEs in same area or power– But, have to compiler manage local store Interesting benchmarks: SpecFP, MediaBench, EEMBC, etc.– New more explicitly parallel benchmarks? Would you ever use an SPE for a SpecInt-type workload?22 2005 IBM Corporation
Systems and Technology GroupCell based systems23 2005 IBM Corporation
Systems and Technology GroupCell Processor Isn't Just for Games.Innovative Chip is best high-performance embedded processor of 2005We chose the Cell BE as the best high-performance embedded processor of 2005 because of itsinnovative design and future potential.Even if the Cell BE accumulates no more design wins, thePlayStation 3 could drive sales to nearly 100 million units over the likely five-year lifespan of theconsole. That would make the Cell BE one of the most successful microprocessors in history.“ Cell could powerhundreds of new apps,create a new videoprocessing industry andfuel a multibillion-dollarbuild out of tech hardwareover ten years.”-- Forbes24“It was originally conceivedas the microprocessor topower Sony's [PS3], but it isexpected to find a home inlots of other broadbandconnected consumer itemsand in servers too.”-- IEEE Spectrum 2005 IBM Corporation
Systems and Technology GroupCell BE based Systems: SCEI, Mercury, and IBM!25 2005 IBM Corporation
Systems and Technology Group Toshiba Announces Cell Chip Set and Cell Reference Set20 September, 2005 Tokyo--Toshiba Corporation today took major steps toward creating a comprehensive development environment for applications based on the Cellmicroprocessor with the announcement of a Cell Chip Set consisting of the new microprocessor and key peripheral chips, and a Cell Reference Setdevelopment platform. The chip set and the reference set will support development of digital consumer products and communication equipment thatdraw on the powerful broadband capabilities of the Cell microprocessor. "Software developers and other customers will be eager to make full use of Cell's unsurpassed multitasking and real-time processing functions," saidTomotaka Saito, General Manager of Broadband System LSI Division, Toshiba Corporation Semiconductor Company. "The Cell Chip Set and ReferenceSet will support them in developing products and applications that reach new levels of performance and excitement." The Cell Chip Set is composed of the Cell processor, a Super Companion Chip—the interface between Cell and external audio/visual input/outputequipment—and a power supply system chip optimized to drive the Cell microprocessor. The Cell Reference Set development platform consists of a Cell microprocessor, peripheral chips mounted on a printed circuit board with a general-useinterface, peripheral equipment, such as DVD and HDD drives, and cooling equipment required for stable operation, all housed in case. The availablesoftware includes operating systems and middleware and software development tools. This combination of hardware and software reducesdevelopment costs, cuts turnaround time and simplifies testing. Toshiba expects to start marketing the chips set and reference set in April 2006 or later, once it has assured supply of the component chips and allrelated documentation. Toshiba Corporation will showcase the Cell Chip Set and Cell Reference Set, and demonstrate digital media applications on the Cell Reference Set atthe Toshiba booth of CEATEC JAPAN 2005, from October 4 to October 8 at Makuhari Messe. Outlines of Cell Chip Set and Cell Reference Set: Cell Chip Set: Cell microprocessor: Next generation microprocessor jointly developed by IBM, Sony Group and Toshiba. Adopts a multi-core architecture and offerssuper high-speed data transfer capability. The processor is expected to find application in equipment handling data-rich media applications. Super Companion Chip: Cell's peripheral LSI, which houses audio and image interfaces supporting Cell's super high-speed data transfer capability.The chip also supports a group of interfaces for various systems (video, audio input/output, digital AV interface, IEEE1394, digital tuner interface) and agroup of interfaces that make it easier to connect standard input/output devices (standard bus interface, high speed network interface and storagedevice interface.) Highly efficient power supply system: The supply system is optimized to drive the Cell processor. Includes controller LSI, TB6814FLG, which makes itpossible to offer high-speed response and high-accuracy required by Cell. Includes multi-chip module, TB7003FL, which embeds power device in asmall 8mm x 8mm package. Realizes small, high-power and high-efficient power supply system which has 4 phases of 1MHz high-speed switches. Cell Reference Set: Development platform for Cell-based, next generation digital consumer products, High-speed multi-bit wiring technology and wide variety of interfaces that supports broadband system architecture Linux and ITRON are both provided on the hypervisor OS that manages hardware resources. This approach facilitates the reuse of application property. A comprehensive development environment including the Eclipse framework based editor, compiler, debugger, and performance monitor. An audio-visual application model includes simultaneous multiple digital and analog broadcast television reception, recording and playback.SOURCE: TOSHIBA26 2005 IBM Corporation
Systems and Technology GroupFuture of Cell andThings for Academia to look at27 2005 IBM Corporation
Systems and Technology GroupUser Interaction Drives Innovation in ComputingImmersive InteractionOnline GamingLevel of InteractionClient/ServerInternetStand Alone PCWindowsMini-ComputerWYSIWYGGamingMain FrameMultitaskingWWWSpreadsheetMain FrameBatchWordProcessingGreen Screen/TeletypeSource: J.A. KahlePunch CardsTime28 2005 IBM Corporation
Systems and Technology GroupCharacteristics of the Latest Transition in User Interaction Windows Immersive, 3D interactivity Click and wait Real-time Client-centric Distributed User data accessible fromclient only User data accessibleeverywhere Device-centric Device-agnostic Connected Collaborative Wired, sporadic Wireless, always-on E-mail/newsgroups Text messaging/blogs29 2005 IBM Corporation
Systems and Technology GroupSome things for Academia to look at Specialization in computer architectures– Beyond OS/Application, what specialization makes sense ina general-(enough) purpose chip/system multiprocessor? Programming paradigms and compilation techniquesto deal with memory wall New types of applications (often real-time) madepossible by a dramatic jump in performance– E.g. gesture and emotion recognition30 2005 IBM Corporation
Cell today and tomorrow H. Peter Hofstee, Ph. D. Cell Chief Scientist and . –3D, real-time, gaming inspired applications –Rich media, data-intensive content Sensory Computing –New network tier . –Bil
of the cell and eventually divides into two daughter cells is termed cell cycle. Cell cycle includes three processes cell division, DNA replication and cell growth in coordinated way. Duration of cell cycle can vary from organism to organism and also from cell type to cell type. (e.g., in Yeast cell cycle is of 90 minutes, in human 24 hrs.)
UNIT-V:CELL STRUCTURE AND FUNCTION: 9. Cell- The Unit of Life: Cell- Cell theory and cell as the basic unit of life- overview of the cell. Prokaryotic and Eukoryotic cells, Ultra Structure of Plant cell (structure in detail and functions in brief), Cell membrane, Cell wall, Cell organelles: Endoplasmic reticulum, Mitochondria, Plastids,
Sydney Sheldon - If Tomorrow Comes If Tomorrow Comes Sydney Sheldon Hmmm, looks like another genie got out of the bottle Me Fiction Scanned and fully proofed by nihua, 2002-03-24 v4.1 CR/LFs removed and formatting tidied. pdb conversion by bigjoe. IF TOMORROW COMES by Sidney Sheldon, 1985 BOOK ONE Chapter 01 New Orleans THURSDAY, FEBRUARY 20 .
The Cell Cycle The cell cycle is the series of events in the growth and division of a cell. In the prokaryotic cell cycle, the cell grows, duplicates its DNA, and divides by pinching in the cell membrane. The eukaryotic cell cycle has four stages (the first three of which are referred to as interphase): In the G 1 phase, the cell grows.
Many scientists contributed to the cell theory. The cell theory grew out of the work of many scientists and improvements in the . CELL STRUCTURE AND FUNCTION CHART PLANT CELL ANIMAL CELL . 1. Cell Wall . Quiz of the cell Know all organelles found in a prokaryotic cell
Class-XI-Biology Cell Cycle and Cell Division 1 Practice more on Cell Cycle and Cell Division www.embibe.com CBSE NCERT Solutions for Class 11 Biology Chapter 10 Back of Chapter Questions 1. What is the average cell cycle span for a mammalian cell? Solution: The average cell cycle span o
Stent Type Stent Design Free Cell Area (mm2) Wallstent Closed cell 1.08 Xact Closed cell 2.74 Neuroguard Closed cell 3.5 Nexstent Closed cell 4.7 Precise Open cell 5.89 Protégé Open cell 20.71 Acculink Open cell 11.48 Stent Free Cell Area Neuroguard IEP Carotid Stent
Stent Type Stent Design Free Cell Area (mm2) Wallstent Closed cell 1.08 Xact Closed cell 2.74 Neuroguard Closed cell 3.5 Nexstent Closed cell 4.7 Precise Open cell 5.89 Protégé Open cell 20.71 Acculink Open cell 11.48 Neuroguard IEP Carotid Stent Stent Free Cell Area
