Avalon Interface Specifications
Avalon Interface SpecificationsSubscribeSend FeedbackMNL-AVABUSREF2014.06.30101 Innovation DriveSan Jose, CA 95134www.altera.com
TOC-2Avalon Interface SpecificationsContents1. Introduction to the Avalon Interface Specifications.1-11.1 Avalon Properties and Parameters.1-41.2 Signal Roles .1-41.3 Interface Timing .1-41.4 Related Documents .1-42. Avalon Clock and Reset Interfaces .2-12.1 Clock Sink Signal Roles .2-12.2 Clock Sink Properties .2-22.3 Associated Clock Interfaces .2-22.4 Clock Source Signal Roles .2-22.5 Clock Source Properties.2-22.6 Reset Sink .2-32.7 Reset Sink Interface Properties.2-32.8 Associated Reset Interfaces .2-32.9 Reset Source .2-42.10 Reset Source Interface Properties.2-43. Avalon Memory-Mapped Interfaces.3-13.1 Introduction to Avalon Memory-Mapped Interfaces .3-13.2 Signals .3-33.3 Interface Properties .3-73.4 Timing .3-103.5 Transfers .3-103.5.1 Typical Read and Write Transfers .3-113.5.2 Read and Write Transfers with Fixed Wait-States .3-123.5.3 Pipelined Transfers .3-123.5.4 Burst Transfers .3-153.6 Address Alignment .3-183.7 Avalon-MM Slave Addressing .3-184. Avalon Interrupt Interfaces .4-1Altera Corporation
Avalon Interface SpecificationsTOC-34.1 Interrupt Sender .4-14.1.1 Interrupt Sender Signal Roles .4-14.1.2 Interrupt Sender Properties .4-14.2 Interrupt Receiver .4-24.2.1 Interrupt Receiver Signal Roles .4-24.2.2 Interrupt Receiver Properties .4-24.2.3 Interrupt Timing .4-35. Avalon Streaming Interfaces .5-15.1 Terms and Concepts .5-25.2 Avalon-ST Interface Signals .5-25.3 Signal Sequencing and Timing .5-35.3.1 Synchronous Interface .5-35.3.2 Clock Enables .5-45.4 Avalon-ST Interface Properties .5-45.5 Typical Data Transfers .5-55.6 Signal Details .5-55.7 Data Layout .5-65.8 Data Transfer without Backpressure .5-65.9 Data Transfer with Backpressure .5-75.10 Packet Data Transfers .5-95.11 Signal Details .5-95.12 Protocol Details .5-96. Avalon Conduit Interfaces .6-16.1 Conduit Signals .6-26.2 Conduit Properties .6-27. Avalon Tristate Conduit Interface .7-17.1 Tristate Conduit Signals .7-37.2 Tristate Conduit Properties .7-37.3 Tristate Conduit Timing .7-48. Additional Information.8-18.1 How to Contact Altera .8-18.2 Typographic Conventions.8-2Altera Corporation
Introduction to the Avalon Interface SpecificationsSubscribe1Send FeedbackAvalon interfaces simplify system design by allowing you to easily connect components in an Altera FPGA.The Avalon interface family defines interfaces appropriate for streaming high-speed data, reading and writingregisters and memory, and controlling off-chip devices. These standard interfaces are designed into thecomponents available in Qsys. You can also use these standardized interfaces in your custom components.By using these standard interfaces, you enhance the interoperability of your designs.This specification defines all of the Avalon interfaces. After reading it, you should understand which interfacesare appropriate for your components and which signal roles to use for particular behaviors. This specificationdefines the following seven interface roles: Avalon Streaming Interface (Avalon-ST)—an interface that supports the unidirectional flow of data,including multiplexed streams, packets, and DSP data. Avalon Memory Mapped Interface (Avalon-MM)—an address-based read/write interface typical ofmaster–slave connections. Avalon Conduit Interface— an interface type that accommodates individual signals or groups of signalsthat do not fit into any of the other Avalon types. You can connect conduit interfaces inside a Qsys system.Or, you can export them to make connections to other modules in the design or to FPGA pins. Avalon Tri-State Conduit Interface (Avalon-TC) —an interface to support connections to off-chipperipherals. Multiple peripherals can share pins through signal multiplexing, reducing the pin count ofthe FPGA and the number of traces on the PCB. Avalon Interrupt Interface—an interface that allows components to signal events to other components. Avalon Clock Interface—an interface that drives or receives clocks. All Avalon interfaces are synchronous. Avalon Reset Interface—an interface that provides reset connectivity.A single component can include any number of these interfaces and can also include multiple instances ofthe same interface type. For example, in the first figure below, the Ethernet Controller includes the followingsix different interface types: Avalon-MMAvalon-STAvalon ConduitAvalon-TCAvalon InterruptAvalon Clock.Note: Avalon interfaces are an open standard. No license or royalty is required to develop and sell productsthat use, or are based on Avalon interfaces. 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX wordsand logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All otherwords and logos identified as trademarks or service marks are the property of their respective holders as described atwww.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance withAltera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumesno responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.www.altera.com101 Innovation Drive, San Jose, CA 95134ISO9001:2008Registered
1-2Introduction to the Avalon Interface SpecificationsThe following figures illustrate the use of the Avalon interfaces in system designs.Figure 1-1: Avalon Interfaces in a System Design with Scatter Gather DMA Controller and Nios II ProcessorPrinted Circuit BoardSSRAMFlashDDR3CnCnCnCnAltera FPGATristate ConduitBridgeTCSMAvalon-MM MasterCnSAvalon-MM SlaveTCMAvalon-TC MasterSrcAvalon-ST SourceTCSAvalon-TC SlaveSnkAvalon-ST SinkCSrcAvalon Clock SourceCSnkAvalon Clock SinkAvalon ConduitTCMTristate ConduitPin SharerTCSTCSIRQ4IRQ3Nios IIIRQ1UARTIRQ2TimerC1SC1SMC1C1TCMTristate CntrlSSRAMSC1TMSTristate nSrcAvalon-STEthernetControllerFIFO BufferC2CSnk PLLCSrcSnkC2FIFO BufferCSrcRef ClkAvalon-STAvalon-STSnkScatter Gather IRQ4DMASAvalon-STMSrcC2IRQ3Scatter GatherDMAC1C2In this figure, the Nios II processor accesses the control and status registers of on-chip components usingan Avalon-MM interface. The scatter gather DMAs send and receive data using Avalon-ST interfaces. Fourcomponents include interrupt interfaces serviced by software running on the Nios II processor. A PLLaccepts a clock via an Avalon Clock Sink interface and provides two clock sources. Two components includeAvalon-TC interfaces to access off-chip memories. Finally, the DDR3 controller accesses external DDR3memory using an Avalon Conduit interface.Altera CorporationIntroduction to the Avalon Interface SpecificationsSend Feedback
Introduction to the Avalon Interface Specifications1-3Figure 1-2: Avalon Interfaces in a System Design with PCI Express Endpoint and External ProcessorPrinted Circuit BoardPCI ExpressRoot PortExternalCPUAltera FPGAIRQ1IRQ2EthernetMACCustomLogicMC1IRQ3PCI ExpressEndpointMC1MC1IRQ5IRQ4IRQ3IRQ2IRQ1External BusProtocolBridgeMC1Avalon-MMSSSSTristate state CntrlSSRAMIRQ4CustomLogicC2C2TCMTristate ConduitPin SharerTCSTCMCSrcTristate ConduitBridgeRef ClkCnCnCnSSRAMFlashCSnk PLLCSrcC1C2CnSDRAMIn the previous figure, an external processor accesses the control and status registers of on-chip componentsvia an external bus bridge with an Avalon-MM interface. The PCI Express Root Port controls devices onthe printed circuit board and the other components of the FPGA by driving an on-chip PCI Express Endpointwith an Avalon-MM master interface. An external processor handles interrupts from five components. APLL accepts a reference clock via a Avalon Clock sink interface and provides two clock sources. The flashand SRAM memories use an Avalon-TC interface to share FPGA pins. Finally, an SDRAM controller accessesan external SDRAM memory using an Avalon Conduit interface.Introduction to the Avalon Interface SpecificationsSend FeedbackAltera Corporation
1-41.1 Avalon Properties and Parameters1.1 Avalon Properties and ParametersAvalon interfaces use properties to describe their behavior. For example, the maxChannel property ofAvalon-ST interfaces allows you to specify the number of channels supported by the interface. The clockRateproperty of the Avalon Clock interface provides the frequency of a clock signal. The specification for eachinterface type defines all of its properties and specifies the default values.1.2 Signal RolesEach of the Avalon interfaces defines a number of signal roles and their behavior. Many signal roles areoptional. You have the flexibility to select only the signal roles necessary to implement the requiredfunctionality. For example, the Avalon-MM interface includes optional beginbursttransfer and burstcountsignal roles for use in components that support bursting. The Avalon-ST interface includes the optionalstartofpacket and endofpacket signal roles for interfaces that support packets.With the exception of Avalon Conduit interfaces, each interface may include only one signal of each signalrole. Active-low signals are permitted for many signal roles. Active-high signals are generally used in thisdocument.1.3 Interface TimingSubsequent chapters of this document include timing information that describes transfers for individualinterface types. There is no guaranteed performance for any of these interfaces. Actual performance dependson many factors, including component design and system implementation.Most Avalon interfaces must not be edge sensitive to signals other than the clock and reset. Other signalsmay transition multiple times before they stabilize. The exact timing of signals between clock edges variesdepending upon the characteristics of the selected Altera device. This specification does not specify electricalcharacteristics. Refer to the appropriate device documentation for electrical specifications.1.4 Related DocumentsFor more information on related topics in the following documents and design examples, refer to the followingdocuments:Related Information Creating a System with Qsys.For an overview of the Qsys system integration tool Creating Qsys ComponentsFor information about creating Qsys components, composed components, and dynamic file generation Optimizing Qsys System Performance.For information about system design, including: hierarchy, concurrency, pipelining, throughput, reducinglogic utilization and power consumptionAltera CorporationIntroduction to the Avalon Interface SpecificationsSend Feedback
1.4 Related Documents1-5 Component Interface Tcl ReferenceFor information about defining Qsys components and a reference for component Tool CommandLanguage (Tcl Qsys System Design ComponentsFor information about system design components available in the IP Catalog Qsys Tutorial Design ExampleFor tutorial that builds a memory test system using components with Avalon interfacesIntroduction to the Avalon Interface SpecificationsSend FeedbackAltera Corporation
Avalon Clock and Reset Interfaces2Send FeedbackSubscribeAvalon Clock interfaces define the clock or clocks used by a component. Components can have clock inputs,clock outputs, or both. A phase locked loop (PLL) is an example of a component that has both a clock inputand clock outputs.The following figure is a simplified illustration showing the most important inputs and outputs of a PLLcomponent.Figure 2-1: PLL Core Clock Outputs and InputsPLL Corealtpll MegafunctionResetSinkresetClockSinkref clkClockSourceClock OutputInterface1ClockSourceClock OutputInterface2ClockSourceClock OutputInterface n2.1 Clock Sink Signal RolesA clock sink provides a timing reference for other interfaces and internal logic.Table 2-1: Clock Input Signal RolesSignal RoleclkWidthDirectionRequired1InputYesDescriptionA clock signal. Provides synchronization for internal logicand for other interfaces. 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX wordsand logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All otherwords and logos identified as trademarks or service marks are the property of their respective holders as described atwww.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance withAltera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumesno responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.www.altera.com101 Innovation Drive, San Jose, CA 95134ISO9001:2008Registered
2-22.2 Clock Sink Properties2.2 Clock Sink PropertiesTable 2-2: Clock Sink PropertiesNameDefault ValueLegal Values00–232–1clockRateDescriptionIndicates the frequency in Hz of the clock sink interface. If0, the clock rate is not significant.2.3 Associated Clock InterfacesAll synchronous interfaces have an associatedClock property that specifies which clock input on thecomponent is used as a synchronization reference for the interface. This property is illustrated in the followingfigure.Figure 2-2: associatedClock Propertyrx clkrx dataClockSinkSTSinkClockSinkDual Clock FIFOassociatedClock "rx clk"associatedClock "tx clk"STSourcetx clktx data2.4 Clock Source Signal RolesAn Avalon Clock source interface drives a clock signal out of a component.Table 2-3: Clock Source Signal RolesSignal An output clock signal.2.5 Clock Source PropertiesTable 2-4: Clock Source PropertiesNameassociatedDirectClockclockRateAltera CorporationDefault ValueLegal ValuesN/Aa clock name00–232–1DescriptionThe name of the clock input that directly drive thisclock output, if any.Indicates the frequency in Hz at which the clockoutput is driven.Avalon Clock and Reset InterfacesSend Feedback
2.6 Reset SinkNameDefault ValueLegal Valuesfalsetrue, falseclockRateKnown2-3DescriptionIndicates whether or not the clock frequency is known.If the clock frequency is known, this information canbe used to customize other components in the system.2.6 Reset SinkTable 2-5: Reset Input Signal RolesThe reset req signal is an optional signal that you can use to prevent memory content corruption by performingreset handshake prior to processor reset.Signal RoleWidthDirectionRequiredreset reset n1InputYesreset req1inputDescriptionResets the internal logic of an interface orcomponent to a user-defined state. Synchronous tothe clock input in the associated clock interface.Optional Early indication of reset signal. When asserted thecomponent is expected to prepare itself to be reset.2.7 Reset Sink Interface PropertiesTable 2-6: Reset Input Signal EdgesDEASSERTLegal ValuesDescriptiona clock name The name of a clock to which this interface synchronized.Required if the value of synchronousEdges is DEASSERT orBOTH.NONEDEASSERTBOTHIndicates the type of synchronization the reset input requires.The following values are defined: NONE–no synchronization is required because thecomponent includes logic for internal synchronization ofthe reset signal. DEASSERT–the reset assertion is asynchronous anddeassertion is synchronous.BOTH–reset assertion and deassertion are synchronous.2.8 Associated Reset InterfacesAll synchronous interfaces have an associatedReset property that specifies which reset signal resets theinterface logic.Avalon Clock and Reset InterfacesSend FeedbackAltera Corporation
2-42.9 Reset Source2.9 Reset SourceTable 2-7: Reset Output Signal RolesThe reset req signal is an optional signal that you can use to prevent memory content corruption by performingreset handshake prior to processor reset.Signal RoleWidthDirectionRequiredreset reset n1OutputYesreset req1OutputDescriptionResets the internal logic of an interface orcomponent to a user-defined state.Optional Enables reset request generation, which is an earlysignal that is asserted before reset assertion. Onceasserted, this cannot be deasserted until the reset iscompleted.2.10 Reset Source Interface PropertiesTable 2-8: Reset Interface PropertiesNameDefault ValueLegal ValuesassociatedClockN/Aa clock nameThe name of a clock to which this interfacesynchronized. Required if the value ofsynchronousEdges is DEASSERT or BOTH.associatedDirectResetN/Aa reset nameThe name of the reset input that directly drivesthis reset source through a one-to-one link.associatedResetSinksN/Aa reset nameSpecifies reset inputs which will eventually causea reset source to assert reset. For example, a resetsynchronizer ORs a number of reset inputs togenerate a reset output.DEASSERTNONE DEASSERTBOTHindicates the type of synchronization the resetinput requires. The following values are defined:synchronousEdgesDescription NONE–no synchronization is required becausethe component includes logic for internalsynchronization of the reset signal. DEASSERT–the reset assertion is asynchronousand deassertion is synchronous. BOTH–reset assertion and deassertion aresynchronous.Altera CorporationAvalon Clock and Reset InterfacesSend Feedback
Avalon Memory-Mapped InterfacesSubscribe3Send Feedback3.1 Introduction to Avalon Memory-Mapped InterfacesYou can use Avalon Memory-Mapped (Avalon-MM) interfaces to implement read and write interfaces formaster and slave components. The following are examples of component that typically includememory-mapped interfaces: MicroprocessorsMemoriesUARTsDMAsTimersAvalon-MM interfaces range from simple to complex. For example, SRAM interfaces that have fixed-cycleread and write transfers have simple Avalon-MM interfaces. Pipelined interfaces capable of burst transfersare complex. 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX wordsand logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All otherwords and logos identified as trademarks or service marks are the property of their respective holders as described atwww.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance withAltera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumesno responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.www.altera.com101 Innovation Drive, San Jose, CA 95134ISO9001:2008Registered
3-23.1 Introduction to Avalon Memory-Mapped InterfacesFigure 3-1: Focus on Avalon-MM Slave TransfersThe following figure shows a typical system, highlighting the Avalon-MM slave interface connection to theinterconnect fabric.EthernetPHYAvalon-MM SystemProcessorEthernet MACCustom ogicRAMMemoryRS-232Tristate Conduit SlaveTristate Conduit Pin Sharer &Tristate Conduit BridgeTristate Conduit hMemorySRAMMemoryAvalon-MM components typically include only the signals required for the component logic.Figure 3-2: Example Slave ComponentThe 16-bit general-purpose I/O peripheral shown in the following figure only responds to write requests.This component includes only the slave signals required for write transfers.Avalon-MM -MMSlave Port)writeDQpio out[15.0]ApplicationSpecificInterfaceCLK ENclkEach signal in an Avalon-MM slave corresponds to exactly one Avalon-MM signal role. An Avalon-MMport can use only one instance of each signal role.Altera CorporationAvalon Memory-Mapped InterfacesSend Feedback
3.2 Signals3-33.2 SignalsThe following table lists the signal roles that constitute the Avalon-MM interface. The signal roles allow youto create masters that use bursts for reads and writes. You can increase the throughput of your system byinitiating reads with multiple pipelined slave peripherals. In responding to reads, when a slave peripheralhas valid data it asserts readdatavalid . The interconnect enables the connection between the master andslave pair.This specification does not require all signals to exist in an Avalon-MM interface. In fact, there is no onesignal that is always required. The minimum requirements are readdata for a read-only interface orwritedata and write for a write-only interface.Table 3-1: Avalon-MM SignalsAll Avalon signals are active high. Avalon signals that can also be asserted low list n versions of the signal in theSignal role column.Signal RoleWidthDirectionDescriptionFundamental Signalsaddress1 - 64Master SlaveMasters: By default, the address signal represents abyte address. The value of the address must be alignedto the data width. To write to specific bytes within adata word, the master must use the byteenable signal.Refer to the addressUnits interface property for wordaddressing.Slaves: By default, the interconnect translates the byteaddress into a word address in the slave’s addressspace. Each slave access is for a word of data from theperspective of the slave. For example, address 0selects the first word of the slave.Address 1 selects thesecond word of the slave. Refer to the addressUnitsinterface property for byte addressing.begintransfer1Master SlaveAsserted by the interconnect for the first cycle of eachtransfer regardless of waitrequest and other signals.The begintransfer signal is optional. A slave canalways internally calculate the start of the nexttransaction from other signals.Note: Altera recommends that you do not usethis signal. This signal exists to supportlegacy memory controllers.Avalon Memory-Mapped InterfacesSend FeedbackAltera Corporation
3-43.2 SignalsSignal Rolebyteenablebyteenable nWidthDirection2, 4, 8, 16, 32,64, 128Master SlaveDescriptionEnables specific byte lane(s) during transfers on portsof width greater than 8 bits. Each bit in byteenablecorresponds to a byte in writedata and readdata.The master bit n of byteenabl
101 Innovation Drive, San Jose, CA 95134. The following figures illustrate the use of the Avalon interfaces in system designs. Figure 1-1: Avalon Interfaces in a System Design with Scatter Gather DMA Controller and Nios II Processor IRQ1 IRQ2 C1
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101 Innovation Drive San Jose, CA 95134 www.altera.com Avalon Interface Specifications
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