Banafsheh Barabadi Multiscale Transient Thermal Analysis .

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Banafsheh BarabadiDepartment of Mechanical Engineering,Massachusetts Institute of Technology,77 Massachusetts Avenue,Cambridge, MA 02139Satish KumarGeorge W. Woodruff Schoolof Mechanical Engineering,Georgia Institute of Technology,801 Ferst Drive,Atlanta, GA 30332Valeriy SukharevDesign-to-Silicon,Mentor Graphics Corporation,46871 Bayside Parkway,Fremont, CA 94538Yogendra K. Joshi1George W. Woodruff Schoolof Mechanical Engineering,Georgia Institute of Technology,801 Ferst Drive,Atlanta, GA 30332e-mail: yogendra.joshi@me.gatech.edu1Multiscale Transient ThermalAnalysis of MicroelectronicsIn a microelectronic device, thermal transport needs to be simulated on scales rangingfrom tens of nanometers to hundreds of millimeters. High accuracy multiscale models arerequired to develop engineering tools for predicting temperature distributions with sufficient accuracy in such devices. A computationally efficient and accurate multiscalereduced order transient thermal modeling methodology was developed using a combination of two different approaches: “progressive zoom-in” method and “proper orthogonaldecomposition (POD)” technique. The capability of this approach in handling severaldecades of length scales from “package” to “chip components” at a considerably lowercomputational cost, while maintaining satisfactory accuracy was demonstrated. A flipchip ball grid array (FCBGA) package was considered for demonstration. The transienttemperature and heat fluxes calculated on the top and bottom walls of the embedded chipat the package level simulations are employed as dynamic boundary conditions for thechip level simulation. The chip is divided into ten function blocks. Randomly generateddynamic power sources are applied in each of these blocks. The temperature rise in thedifferent layers of the chip calculated from the multiscale model is compared with a finiteelement (FE) model. The close agreement between two models confirms that the multiscale approach can predict temperature rise accurately for scenarios corresponding todifferent power sources in functional blocks, without performing detailed FE simulations,which significantly reduces computational effort. [DOI: 10.1115/1.4029835]Keywords: Joule heating, three-dimensional (3D) architecture, transient thermalanalysis, reduced order modeling, proper orthogonal decomposition, progressive zoomin approachIntroductionThe integrated circuits (IC) industry is driven by scaling tosmaller and higher performing devices to enable lower cost andhigher speed. However, major challenges exist in maintaining performance and reliability while facing fundamental scaling limitations. The current chip and package architectures are subjected tohigher density of the heat dissipating elements and elevated totalpower generation rates. This can result in local hot-spots that arelayout and/or workload dependent, leading to significant variationin the performance and leakage current of devices. Moreover,cyclic thermal events as a result of Joule heating in the metallicinterconnect and transistors can lead to fatigue failure, due to thethermal expansion coefficients mismatch among different materials in the device. Thus, it is essential to develop fast and accuratemultiscale models to calculate the thermal response of circuits foradvanced technology nodes.Various approaches have been proposed in the literature forpredicting temperature distributions with sufficient accuracy inchips and packages [1,2]. Among these multiscale methodologies,the traditional bottom-up approaches are extensively used for transient thermal modeling. Perhaps, the best known of this class ofmethods is the resistance–capacitance network, which is constructed using thermal impedances [3,4]. The accuracy of themodels decreases for complex geometries, complex boundaryconditions, and nonlinearity in the heat conduction equation [5].Another common bottom-up approach utilizes compact models,which can be finite volume (FV) or FE based. In a traditional FEor FV analysis, the domain is discretized in a way that each element is homogeneous. It can, however, have anisotropic thermalconductivity. Compact models do not require conventional bilinear rectangular or homogeneous elements and can have elements1Corresponding author.Contributed by the Electronic and Photonic Packaging Division of ASME forpublication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 2,2013; final manuscript received February 16, 2015; published online April 16, 2015.Assoc. Editor: Amy Fleischer.Journal of Electronic Packagingcomprising both metal and dielectric region. Some of the firstcompact modeling work was done by Kreuger and Bar-Cohen in1992 [6]. They modeled a chip package with a simplified resistornetwork and shorter simulation times. However, the network topography of compact models becomes complex with increase inmodel size, also potentially compromising the accuracy of themodel [7]. Another limitation of such compact models is the difficulty in handling fluid/solid interactions. In general, these bottomup approaches have primarily addressed the steady-state Jouleheating in interconnects. However, pulsed currents and the resulting transient heat conduction in interconnect arrays remain a keyconcern in the design for reliability for the next generation highperformance chips.Top-down approaches are another category of multiscale thermal modeling in microelectronics. A recent approach is behavioral thermal modeling, which is a combination of the generalizedpencil-of-function (GPOF) [8,9] and subspace methods [10,11].GPOF was developed in the communications community to estimate poles of an electromagnetic system by solving a generalizedeigenvalue problem. These methods are mainly used for highperformance multicore microprocessor design. In general, theypotentially suffer from a lack of predictability problems. Therefore, there is a need for the development of a new thermal simulation methodology that overcomes the challenges faced by existingthermal models.In this study, a novel, computationally efficient, and accuratemultiscale reduced order transient thermal modeling methodologyis developed, which comprises two parts: (1) progressive zoom-inand (2) POD. The analyses at various length scales are integratedvia the progressive zoom-in approach, which is illustrated inFig. 1 and will be further discussed in Sec. 2.2. POD is a robustand elegant method of data analysis that provides lowdimensional but accurate descriptions of a high-dimensional system. It was first introduced by Lumley [12] in the field of turbulence; Holmes et al. [13] provided a thorough summary forapplications of POD in various fields. As shown by Barabadi et al.[14], for any linear system, the method is capable of predictingC 2015 by ASMECopyright VSEPTEMBER 2015, Vol. 137 / 031002-1Downloaded From: asme.org/ on 07/27/2015 Terms of Use: http://asme.org/terms

Fig. 1 Flowchart of the hybrid scheme for multiscale thermalmodelingtransient temperature distribution regardless of the temporal orspatial dependence of the applied heat source. This feature provides the ability to predict temperature distributions for arbitraryheat inputs, by using a smaller sample set of applied heat sourcesand power maps, resulting in considerably decreased simulationtime. Combining POD with the progressive zoom-in approach canfurther enhance the computational efficiency.The proposed methodology has the capability of modeling several decades of length scale from package to “chip component”and potentially the “interconnect” (not included here) levels, at asignificantly lower computational cost than currently availablemethods. This characteristic of the method also applies for timescales from seconds down to microseconds, corresponding to various transient thermal events. The suggested approach provides theability to rapidly predict thermal responses under different powerinput patterns, based only on a few representative detailed simulations, while maintaining adequate spatial and temporal accuracy.In this paper, an FCBGA package with an embedded die is considered for thermal modeling. Random dynamic power distributions were considered for the total chip power, as well as for thefunction blocks that compose the entire chip to demonstrate thecapability of the POD method. To validate this methodology, theresults were compared with an FE model developed in COMSOL[15]. It is demonstrated that the computational time is reduced byat least two orders of magnitude at every step of modeling.22.1 Fundamentals of POD Method. POD offers an optimalset of basis functions, also known as POD modes, which areempirically determined from an ensemble of observations. Theseobservations are obtained either experimentally or from numericalsimulation, as in this study. The POD method characterizes andcaptures the overall behavior and complexity of a physical systemby using a reduced number of degrees-of-freedom. This results ina much lower computational cost than a full-field simulationmethod. The most remarkable characteristic of the POD is its optimality, i.e., it provides the most efficient way of capturing thedominant components of an infinite-dimensional process, withonly finite number of basis functions [13]. In developing the PODmodel, data sets are expanded for modal decomposition on empirically determined basis functions in a way that minimizes the leastsquare error between the true solution and the truncated representation of the POD model. Therefore, it makes the POD method themost efficient method of capturing the dominant components of alarge-dimensional system with a finite number of modes [16,17].In this technique, the temperature distribution is determinedfrom the expansionTðx; y; z; tÞ ¼ T0 ðx; y; zÞ þbi ðtÞ/i ðx; y; zÞ(1)i¼1where T0 is the time average of temperature (i.e., the mean vectorof the observation matrix), ui(x, y, z) is the ith POD mode, andbi(t) is the ith POD coefficient [14]. A detailed procedure to generate a two-dimensional (2D) POD based reduced order model isprovided in Ref. [14]. The primary steps to generate a POD basedreduced order model are outlined below:(1) Generating the observation matrix.(2) Calculating basis functions (POD modes).(3) Calculating POD coefficients, bi.As demonstrated in Ref. [14], the POD coefficients, bi, can bedetermined by solving the discretized matrix of coupled ordinarydifferential equations, Eq. (2), using the sixth-order Runge–Kuttamethod shown below:Aij b j ðtÞ Bij bj ðtÞ ðc þ qÞi ¼ 0; i; j ¼ 1; 2; :::; m(2)Coefficients Aij, Bij, ci, and qi in Eq. (2) were derived and presented for 2D POD model in Ref. [14]. For this study, coefficientsin Eq. (2) were determined for 3D analysis asHybrid Scheme for Multiscale Thermal ModelingA hybrid scheme has been developed in this paper, which combines the implementation of POD and progressive zoom-inapproach, as summarized below.mXAij ¼ðuj ui dX(3a)X ð @uj @ui @uj @ui @uj @uiauj r2 ui dX ¼ a þ þ dX@x @x@y @y@z @zXX ð ð ð @u y¼ymax@u x¼xmax@u z¼zmaxþauj idx þauj idyþauj idx@y y¼ymin@x x¼xmin@z z¼zminxyz(3b) @uj @T0 @uj @T0 @uj @T0 þ þ dXcj ¼ auj r T0 dX ¼ a@x @x@y @y@z @zXX y¼ymax x¼xmax ð ð ð @T0@T0@T0 z¼zmaxauj dx þauj dy þauj dzþ@y y¼ymin@x x¼xmin@z z¼zminxyz(3c)Bij ¼ðð2031002-2 / Vol. 137, SEPTEMBER 2015ðTransactions of the ASMEDownloaded From: asme.org/ on 07/27/2015 Terms of Use: http://asme.org/terms

qj ¼ð1uj q000 ðtÞdXqcpXpower maps and types of power sources, without developing any further full-field FE models, which can significantlydecrease computational cost and potentially be used todefine a criterion for the optimal distribution of the currentdensity in the domain.(3) Transferring the solution from package level to the chiplevel: Once the temperature distribution at the packagelevel is obtained, a combination of temperature and heatflux at the top and bottom walls of the chip is extracted andlinearly interpolated on a 2D grid with higher spatial resolution. These data were then applied as boundary conditionsfor the chip level simulation.(4) Chip level thermal simulation: At this level, the chip is nolonger treated as a solid block. It is divided into subdomainscalled function blocks. Each block represents a specificcomponent with unique functionality on the chip and consists of three sublayers: (1) top Si layer, (2) middle devicelayer, and (3) interconnect/dielectric multilayer (see Fig. 2).Function blocks were simulated based on the assignedpower generation and calculated effective material/thermalproperties for each layer within that block. At this level ofthermal simulation, the spatial resolution is limited to thesublayers. Once the chip is divided into subdomains, thepower map needs to be determined at any instant of timefor each individual function block.(5) Continue to the desired resolution on the chip: This methodcan be continued to multiple levels, such that the desiredspatial resolution is achieved. Only representative resultsfor two steps (package and chip level) are presented in thispaper.(3d)The last two terms on the right-hand side of Eqs. (3b) and (3c)are the boundary terms. If the boundary conditions are homogeneous or insulation, these are eliminated and Bij and ci are simplifiedto ð @uj @ui @uj @ui @uj @uiBij ¼ a þ þ dX(4a)@x @x@y @y@z @zX ð @uj @T0 @uj @T0 @uj @T0cj ¼ a þ þ dX(4b)@x @x@y @y@z @zX(4) Generating the POD temperature field.A sufficient number of POD modes and POD coefficients needto be calculated, which can then be used in Eq. (1) for the determination of the temperature field anywhere in the domain and at anyinstant of time.The number of retained POD modes is quite critical in capturing the physics of the problem. It is shown that an insufficientnumber of POD modes can cause significant phenomena not tobe detected [18]. On the contrary, taking too many POD modescan produce unexpected behavior or make the model unstable.The last POD modes are generally associated with low energyterms in the model and have rapid localized fluctuation throughout the domain. If too many modes are considered in the PODreconstruction, the accumulation of these rapid fluctuationsresults in an increase in the numerical error and can potentiallycause the solution to diverge [19,20]. The energy captured by theith basis function in the problem is relative to its correspondingeigenvalue, ki. Sorting these eigenvalues in a descending orderresults in an ordering of the corresponding POD modes [14].Therefore, the first POD mode captures the largest portion ofenergy relative to the other basis functions. To determine thetruncation degree of the POD method, the cumulative correlationenergy, Em, captured by the first m POD modes is defined byBizon et al. [21]mXEm ¼i¼1nXki(5)kii¼1To be able to generate a reliable POD model, in the presentstudy, the number of POD modes is determined in such a way thatthe cumulative energy of the modes, calculated from Eq. (5), islarger than 99.9%.2.2 Progressive Zoom-In Approach. The progressive zoomin method integrates package and chip level analyses, acquiringthe advantages of each. Figure 1 shows a flowchart of theapproach used in this study for multiscale transient thermal modeling of a representative FCBGA package. The overall hybridapproach is outlined below:(1) Thermal simulation at the package level: The first step is tomodel the entire structure, i.e., the package, including thesurrounding mold, underfill, solder bumps, and substrate.This simulation is performed in the commercial code COMSOL. It is important to note that at this level, the chip is modeled as a solid block with effective material and thermalproperties, without considering internal details.(2) Applying POD technique to package level: Once the temperature distribution at package level is determined, a PODmodel is developed. The POD model provides the ability topredict dynamic temperature distribution for differentJournal of Electronic Packaging3Results and DiscussionFigure 2(a) shows the schematic of the simplified FCBGApackage used in this study for the package level modeling. Thismodel is for low power portable systems, where heat sinks andforced cooling are not employed due to the compact form factor.As described in Sec. 2, the first step is to model the package forwhich the material properties and dimensions are required. Table 1lists these for the die, solder bumps, underfill, mold, and substrate.These values were mainly provided by Mentor Graphics Corporation, and the rest were chosen based on Ref. [22]. Reference [23]is used as a guideline for the dimensions of the FCBGA package.Underfill is a specially engineered epoxy that fills the areabetween the die and the carrier surrounding the solder bumps.Effective density and specific heat of the underfill layer are calculated based on volume averaging. It is assumed that 60% of thesurface area between the die and substrate is covered with underfill and 40% is solder bumps. The effective vertical (K veff ) andhorizontal (K heff ) thermal conductivity values are calculated basedon thermal resistor network formulation1 8U 18S 1þ8tot KU 8tot KS AhUAhS¼ KUþ KSAhAhKheff ¼ (6a)Kveff(6b)where 8tot is the entire volume, 8U and 8S are volumes of underfilland solder bumps, respectively. Similarly, AhU and AhS are thecumulative horizontal cross-sectional areas of the underfill andsolder bumps. KU and KS are the thermal conductivities of theunderfill and solder bumps, respectively. Considering that thesolder bumps are made of conductive material and electricallyconnect the chip to the underlying substrate while underfill is aninsulating material, it is expected that the vertical effective thermal conductivity of the underfill layer will be significantly higherthan its horizontal value. The computed values are 20.2 andSEPTEMBER 2015, Vol. 137 / 031002-3Downloaded From: asme.org/ on 07/27/2015 Terms of Use: http://asme.org/terms

Fig. 2 (a) Schematic of a simplified FCBGA for package level modeling and (b)zoomed-in schematic of the die layer used in chip level modelingTable 1DieUnderfillSolder bumpsEffective underfillMoldSubstrateMaterial properties and dimensions of the packageThermal conductivity (W/m K)Density (kg/m3)Specific heat capacity (J/kg K)Dimension (mm3)98.40.6501.47 (horizontal)20.24 (vertical)0.50.72300182085104496721236183214.810 10 0.26610 10 0.140% of the die surface area60% of the die surface area182017002369201.47 W/m K, respectively. The package dimensions, also listed inTable 1, were provided by Mentor Graphics Corporation.Natural convection boundary condition is imposed on the topsurface and vertical boundaries of the package with a heat transfercoefficient of h ¼ 15 W/m2 K in the typical range for air cooling[24]. A constant temperature boundary condition is applied to thebottom surface. The initial temperature and the surrounding temperature were assumed to be equal to the room temperatureTamb ¼ 300 K.A detailed FE model is developed in COMSOL using a time stepof dt ¼ 0.05 s. The convergence of the FE model is verified withrespect to the solver type, time step, and time integration method.The FE model of the package consists of 75,919 elements, ofwhich 343 are for the chip (die). This grid size is determined afterperforming mesh independence analysis. For the grid independence study, the mesh resolution of the model is continuouslyrefined until there is less than 1% difference in the computed temperatures. This analysis indicated that the grid size of 75,919 elements is sufficient. Total chip power is Q ¼ 3 sin 2pt þ 3 (W),which is applied for 1 s. The temperature rise in the simulation domain is represented by DT (K) throughout the paper. Figure 3(a)37 37 1.937 37 1.1shows the spatial distribution of the temperature rise in theFCBGA

Multiscale Transient Thermal Analysis of Microelectronics In a microelectronic device, thermal transport needs to be simulated on scales ranging from tens of nanometers to hundreds of millimeters. High accuracy multiscale models are required to develop engineering tools for predicting temperature distributions with suffi-cient accuracy in such .

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